Professional Documents
Culture Documents
Rev. B
This manual describes the assembly language format, and how to write assembly language
programs for the Intel 8080 microprocessor. Detailed information on the operation of
specific assemblers is available in the Operator's Manual and I nstallation Guide for each
specific assembler.
Rev. B
TERMS
DESCRIPTION
Address
Bit
Byte
Instruction
The smallest single operation that the computer can be directed to execute.
Object Program
A program which can be loaded directly into the computer's memory and
which requires no alteration before execution. An object program is usually
on paper tape. and is produced by assembling (or compiling) a source program. Instructions are represented by binary machine code in an object
program.
Program
Source Program
System Program
User Program
A program written by the user to make the computer perform any desired task.
Word
nnnnB
nnnnD
nnnnO
nnnnQ
nnnnH
ii
INTRODUCTION
'----
CHAPTER 1
COMPUTER ORGANIZATION
WORKING REGISTERS
MEMORY
PROGRAM COUNTER
STACK POINTER
INPUT/OUTPUT
COMPUTER PROGRAM REPRESENTATION
IN MEMORY
MEMORY ADDRESSING
Direct Addressing
Register Pair Addressing
Stack Pointer Addressing
Immediate Addressing
Subroutines and Use of the Stack
for Addressing
CONDITION BITS
Carry Bit
Auxiliary Carry Bit
Sign Bit
Zero Bit
Parity Bit
CHAPTER 2
THE 8080 INSTRUCTION SET
ASSEMBLY LANGUAGE
How Assembly Language is Used
Statement Syntax
Label Field
Code Field
Operand Field
Comment Field
DATA STATEMENTS
Two's Complement Representation
DB Define Byte(s) of Data
DW Define Word (Two Bytes) of Data
DS
Define Storage (Bytes)
CARRY BIT INSTRUCTIONS
STC Set Carry
1
1
2
2
2
2
2
3
3
3
3
4
4
5
5
6
6
6
6
7
7
7
8
8
9
9
12
12
12
13
14
14
14
14
iii
14
14
15
15
15
15
16
16
16
17
17
17
17
18
18
19
19
19
20
20
21
21
21
22
22
22
22
23
24
24
24
24
25
25
25
26
26
27
27
27
CHAPTER 3
PROGRAMMING WITH MACROS
WHAT ARE MACROS?
MACRO TERMS AND USE
Macro Definition
Macro Reference or Call
Macro Expansion
Scope of Labels and Names Within Macros
Macro Parameter Substitution
REASONS FOR USI NG MACROS
USEFUL MACROS
Load I ndirect Macro
Other Indirect Addressing Macros
Create Indexed Address Macro
28
28
29
29
29
30
30
30
30
31
31
31
32
32
32
32
33
33
33
33
33
34
34
34
34
35
35
35
35
35
35
CHAPTER 4
PROGRAMMING TECHNIQUES
BRANCH TABLES PSEUDO-SUBROUTINE
SUBROUTINES
Transferring Data to Subroutines
SOFTWARE MULTIPLY AND DIVIDE
MULTIBYTE ADDITION AND SUBTRACTION
DECIMAL ADDITION
DECIMAL SUBTRACTION
ALTERI NG MACRO EXPANSIONS
35
36
36
36
36
36
37
37
37
37
37
38
38
38
38
38
39
39
39
39
40
40
41
41
41
43
43
44
44
45
45
46
46
47
47
47
48
48
49
49
50
51
53
55
56
57
58
CHAPTER 5
INTERRUPTS
WRITING INTERRUPT SUBROUTINES
59
60
APPENDIX A
INSTRUCTION SUMMARY
VI
APPENDIX B
INSTRUCTION EXECUTION TIMES AND
BIT PATTERNS
XVI
APPENDIX C
ASCII TABLE
XX
APPENDIX 0
BINARY -DECIMAL-HEXADECIMAL
CONVERSION TABLES
XXII
LIST OF FIGURES
iv
"
.--/
This manual has been written to help the reader program the INTE L 8080 microcomputer in assembly language.
Accordingly, this manual assumes that the reader has a good
understanding of logic, but may be completely unfamiliar
with programming concepts.
interrupt handling
This section provides the programmer with a functional overview of the 8080. Information is presented in this
section at a level that provides a programmer with necessary
background in order to write efficient programs.
These seven working registers are numbered and referenced via the integers 0, 1,2,3,4,5, and 7; by convention,
these registers may also be accessed via the letters B, C, D,
E, H, L, and A (for the accumulator), respectively.
(1)
(2)
(3)
(4)
(5)
.__
Input/Output, which is the interface between a program and the outside world.
WORKING REGISTERS
The 8080 provides the programmer with an 8-bit accumulator and six additional 8-bit "scratchpad" registers.
Register Pair
Registers Referenced
Band C (0 and 1)
D and E (2 and 3)
Hand L (4 and 5)
See below
D
H
PSW
MEMORY
The 8080 can be used with read only memory, programmable read only memory and read/write memory. A
program can cause data to be read from any type of memory,
but can only cause data to be written into read/write
memory .
The programmer visualizes memory as a sequence of
bytes, each of which may store 8 bits (represented by two
hexadecimal digits). Up to 65,536 bytes of memory may be
Rev. B
PROGRAM COUNTER
The program counter is a 16 bit register wh ich is accessible to the programmer and whose contents indicate the
address of the next instruction to be executed as described
in this chapter under Computer Program Representation in
Memory.
STACK POINTER
A stack is an area of memory set aside by the programmer in which data or addresses are stored and retrieved
by stack operations. Stack operations are performed by
several of the 8080 instructions, and facilitate execution of
subroutines and handling of program interrupts. The programmer specifies which addresses the stack operations will
operate upon via a special accessible 16-bit register called
the stack pointer.
Memory
Address
0212
0213
0214
0215
0216
0217
0218
0219
021A
021B
021C
0210
021E
021F
0220
0221
INPUT/OUTPUT
To the 8080, the outside world consists of up to 256
input devices and 256 output devices. Each device communicates with the 8080 via data bytes sent to or received
from the accumulator, and each device is assigned a number
from 0 to 255 which is not under control of the programmer.
The instructions which perform these data transmissions are
described in Chapter 2 under Input/Output Instructions.
Instruction
Number
2
3
Program Counter
Contents
0213
0215
0216
0219
021B
021C
021F
8
9
10
0220
0221
0222
NOTE:
If a program stores data into a location, that location should not normally appear among any program instructions. This is because user programs
are (normally) executed from read-only memory,
into which data cannot be stored.
Rev. B
which will load the accumulator with the contents of memory byte 1 F2A would appear as follows:
Memory
Registers
B
Instructi 0 n
being executed
-+
7E
1------1
D
E
1F
2A
L
A
MEMORY ADDRESSING
By now it will have become apparent that addressing
specific memory bytes constitutes an important part of any
computer program; there are a number of ways in which this
can be done, as described in the following subsections.
Direct Addressing
With direct addressing, an instruction suppl ies all exact
memory address.
The instruction:
"Load the contents of memory address 1 F2A into
the accumulator"
Memory
NOTE:
'---
3A
any
-
any + 1
2A
any + 2
instruction
being executed
1F
(1)
(2)
(3)
I
I
Before Pop
SP
Memory Address
After Pop
FF
1507
FF
33
1508
33
OB
1509
OB
FF
150A
FF
I
I
Before Push
SP
B
Memory Address
After Push
FF
13A3
FF
FF
13M
30
FF
13A5
6A
FF
13A6
FF
SP
SP
The programmer loads the stack pointer with any desired value by using the LXI instruction described in Chapter
2 under Load Register Pair-Immediate. The programmer
must initialize the stack pointer before performing a stack
operation, or erroneous results will occur.
Immediate Addressing
An immediate instruction is one that contains data.
The following is an example of immediate addressing:
"Load the accumulator with the value 2AH."
The above instruction would be coded in memory as
follows:
(2)
(3)
Memory
GJ ~
~
+-
Consider a frequently used operation such as multiplication. The 8080 provides instructions to add one byte
of data to another byte of data, but what if you wish to
multiply these numbers? This will require a number of instructions to be executed in sequence. It is quite possible
that this routine may be required many times within one
program; to repeat the identical code every time it is needed
is possible, but very wasteful of memory:
Rev. B
I
I
Program
"-'
Routine
r
I
I
I
Program
Routine
I
I
I
I
Memory
Address
Instruction
OC02
OC03
OC04
OC05
OC06
CALL SUBROUTINE
02
OF
NEXT INSTRUCTION
Push address of
next instruction
(OC06H) onto
the stack and
branch to
subroutine
starting at
OF02H
Program
OFOO
OF01
OF02
Routine
I
etc
FIRST SUBROUTINE
INSTRUCTION +-
OF03
Body of subroutine
OF4E
OF4F
RETURN
Program
Subroutines may be nested up to any depth limited
only by the amount of memory available for the stack. For
example, the first subroutine could itself call some other
subroutine and so on. An examination of the sequence of
stack pushes and pops will show that the return path will
always be identical to the ;'dll path, even if the same subroutine is called at more than one level.
Program
+---+
Routine
Program
CONDITION BITS
Main Program
Call instruction ~
-;.. Subroutine
Next instruction
Carry Bit
The Carry bit is set and reset by certain data operations, and its status can be directly tested by a program.
The operations wh ich affect the Carry bit are addition, subtraction, rotate, and logical operations. For example, addition of two one-byte numbers can produce a carry out of
the high-order bit:
Bit No. 7 6
5 4
AE=
0
0
0
+ 74= 0 1 1 1 0 1 0 0
122[ 0 0 1 0 0 0 1 0
+ carry-out = 1, sets Carry Bit = 1
Addition, subtraction, rotate, and logical operations follow different rules for setting and resetting
the Carry bit. See Chapter 2 under Two's Complement Representation and the individual instruction
descriptions in Chapter 2 for details. The 8080
instructions which use the addition operation are
ADD, ADC, ADJ, ACI, and DAD. The instructions
which use the subtraction operation are SUB, SBB,
SUI, SBI, CMP, and CPI. Rotate operations are
RAL, RAR, R LC, and R RC. Logical operations
are ANA, ORA, XRA, ANI, ORI, and XRI.
Sign Bit
As described in Chapter 2 under Two's Complement
Representation, it is possible to treat a byte of data as having
the numerical range -128\0 to +127\0' In this case, by
convention, the 7 bit will always represent the sign of the
number; that is, if the 7 bit is 1, the number is in the range
-128\0 to -1. If bit 7 is 0, the number is in the range 0 to
+127\0'
At the conclusion of certain instructions (as specified
in the instruction description sections of Chapter 2). the
Sign bit will be set to the condition of the most significant
bit of the answer (bit 7).
Zero Bit
This condition bit is set if the result generated by the
execution of certain instructions is zero. The Zero bit is
reset if the result is not zero.
A result that has a carry but a zero answer byte, as
illustrated below, will also set the Zero bit:
Bit No. 7 6
I-
Bit No. 7 6 5 4
2E= 0 0
0 1
+ 74= 0 1
1 0
A2
1 0 1 0 0 0
1 0
0 0
1 0
LCarry=o
~ Auxiliary Carry=1
The Auxiliary Carry bit will be affected by all addition, subtraction, increment, decrement, and compare
instructions.
Carry ouy
of bit 7.
5 4
1 0 1 0 0 1 1 1
+ 0 1 0 1 1 0 0 1
0 0 0 0 0 0 0 0
Zero answer
Zero bit set to 1.
Parity Bit
Byte "parity" is checked after certain operations. The
number of 1 bits in a byte are counted, and if the total is
odd, "odd" parity is flagged; if the total is even, "even"
parity is flagged.
The Parity bit is set to 1 for even parity, and is reset
to 0 for odd parity.
ASSEMBLY LANGUAGE
Hexadec imal
Memory Address
1432
1433
1434
1435
1436
1437
14C3
14C4
14C5
14C6
14C7
Hexadecimal
Memory Address
1432
1433
1434
1435
1436
7E
C3
C4
14
14C3
14C4
14C5
14C6
FF
2E
36
77
Old Code
7E
C3
C4
14
~Jew
Code
tJd
New Instruction
C3
C5
14
FF
2E
36
77
FF
2E
37
77
The assembler takes care of the fact that a new instruction will shift the rest of the program in memory.
Statement Syntax
II
Assembly
language
program
written by
programmer
--J
'1
Executable
ASSEMBLERI ~ machine
code
PROGRAM I
Field 2 is the OPERAND field. It provides any address or data information needed by the CODE field.
Field 4 is the COMMENT field. It is present for the
programmer's convenience and is ignored by the assembler.
The programmer uses comment fields to describe the operation and thus make the program more readable.
-----
SOURCE
PROGRAM
OBJECT
PROGRAM
Label
Code
Operan~
HERE:
MVI
C,O
THERE:
DB
LOOP:
ADD
For example:
One Possible
Version of the
Object Progra~
NOW: MOV
CPI
JZ
LER: MOV
NOTE:
A,B
'C'
LER
M,A
is converted
by the
Assembler
to
RLC
78
FE43
CA7C3D
77
Label Field
MOV
A,B
(New instruction inserted here)
CPI
'C'
JZ
LER
MOV
coo,,,,, of E cog;""
NOTE: These examples and the ones which follow are intended to illustrate how the various fields appear
in complete assembly language statements. It is not
necessary at this point to understand the operations
wh ich the statements perform.
@HERE:
LER
; Add
to the accumulator
NOW:
M,A
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1i
7ZERO:
is an operation code
END:
is a pseudo-instruction
JMP
THERE
THERE:
MOV
C,D
THERE:
CALL
SUB
is ambiguous; the assembler cannot determine which address is to be referenced by the JMP instruction.
LOOP2:
MOV
C,D
JMP
LOOP1
Ways of specifying
(a) Register
(b) Register Pair
(c) Immediate Data
(d) 16-bit Memory Address
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Hexadecimal Data
Decimal Data
Octal Data
Binary Data
Program Counter ($)
ASCII Constant
Labels assigned values
(8) Labels of instructions
(9) Expressions
One instruction may have more than one label, however. The following sequence is valid:
LOOP1 :
Information required
(1)
; First label
; Second label
Example:
Comment
Label
JMP
LOOP2
HERE:
MVI
Code Field
This field contains a code which identifies the machine operation (add, subtract, jump, etc.) to be performed:
hence the term operation code or op code. The instructions
described later in this chapter are each identified by a
mnemonic label which must appear in the code field. For
example, since the "jump" instruction is identified by the
letters "JMP," these letters must appear in the code field to
identify the instruction as "jump."
JMP
HERE
JMPTHERE
(3)
Label
Code
Operand
ABC:
MVI
E,105
Comment
; Load register Ewith 105
THERE
is legal, but:
Comment
Label
is illegal.
LABEL:
MVI
Operand Field
This field contains information used in conjunction
with the code field to define precisely the operation to be
performed by the instruction. Depending upon the code
field, the operand field may be absent or may consist of one
item or two items separated by a comma.
(4)
A,nO
Label
Code
NOW:
JUMP:
Operand
Comment
(8)
Label
Code
Operand
A1 :
A2:
A3:
MVI
MVI
MVI
0, VALUE
2,9FH
2, VALUE
(5)
Label
Code
Operand
Comment
HERE:
JMP
THERE
; Jump to instruction
; at THERE
THERE:
MVI
D,9FH
Example:
Label
Code
GO:
JMP
(9)
(6)
An ASCII constant. This is one or more ASCII characters enclosed in single quotes. Two successive single
quotes must be used to represent one single quote
within an ASCII constant. Appendix 0 contains a list
of legal ASCII characters and their hexadecimal
representations.
Example:
Label
Code
CHAR: MVI
Operand
E:*'
Comment
The operator / produces the arithmetic integer quotient of its operands, discarding any remainder.
The operator MOD produces the integer remainder
obtained by dividing the first operand by the second.
The operator NOT complements each bit of its
operand.
(7)
"
E
H
L
M
A
" 3
"4
" 5
" 6
" 7
0
E
H
L
a memory reference
register A
Example:
Suppose VALUE has been equated to the hexadecimal number 9FH. Then the following instruc~
tions all load the 0 register with 9FH:
10
MVI, H,NOT 0
is invalid, since NOT 0 produces the 16-bit hexadecimal
number FFFF. However, the instruction:
MVI
is invalid.
(a)
Examples:
Label
Code
Operand
HERE:
MVI
C, HERE SHR 8
C, VALUE ANDOFH
Arbitrary
Memory Address
Value
2E1A
Label
Code
Operan~
NEXT:
MVI
D, 34+4 OH/2
Registe':.
1
2
3
4
5
6
C
D
E
H
L
Memory Reference
A (accumulator)
Example:
The above instruction will load the value 34+ (64/2)
= 34+32 = 66 into the D register.
Label
Code
Qeerand
INS:
DB
(ADD C)
Label
Code
Operand
INSl :
INS2:
INS3:
MVI
MVI
MVI
REG4,2EH
4H,2EH
812,2EH
(b)
1.
2.
3.
4.
Parenthesized expressions
*.IM, MOD, SHL, SHR
+, - (unary and binary)
NOT
5. AND
6. OR, XOR
Specification
B
D
H
PSW
SP
D, (34+40H)/2
11
Register Pair
Registers Band C
Registers D and E
Registers Hand L
One byte indicating the state of the
condition bits, and Register A (see
Sections 4.9.1 and 4.9.2)
The 16-bit stack pointer register
NOTE:
DATA STATEMENTS
This section describes ways in which data can be
specified in and interpreted by a program. Any 8-bit byte
contains one of the 256 possible combinations of zeros and
ones. Any particular combination may be interpreted in
various ways. For instance, the code 1FH may be interpreted
as a machine instruction (Rotate Accumulator Right
Through Carry), as a hexadecimal value 1FH=31 D, or merely
as the bit pattern 000011111.
Example:
Label
Code
Operand
Comment
PUSH
INX
SP
Arithmetic instructions assume that the data bytes upon which they operate are in a special format called "two's
complement," and the operations performed on these bytes
are called "two's complement arithmetic."
Example:
~el
L_RE:
Operan~
gode
H, DATA
MVI
Comment
; Load the H register with
; the value of DATA
take:
(d)
o = OOOOOOOOB = OH
1 = 00000001 B = 1H
Example:
~abel
i
HERE:
Qperand
JMP
JMP
Comment
-_._---
(b)
Example:
Comment Field
HERE:
(a)
Complement each
bit : 11110101 B
Add one
11110110B
12
Example:
12D = 0 0 0 0 1 1 0 0 = OCH
-15D = 1 1 1 1 000 1 = OF1 H
carry out ~ 0 1 1 1 1 1 1 0 1 = -3D
Since the carry out of bit 7 = 0, indicating that the
answer is negative and in its two's complement form, the
subtract operation will set the Carry bit indicating that a
"borrow" occurred.
86H = 1 0 0 0 0 1 1 0 B
Complement each bit : 0 1 1 1 1 00 1 B
: 0 1 11 10 10 B
Add one
Thus, the val ue of 86H is -7 AH = -122D
NOTE:
The 8080 instructions which perform the subtraction operation are SUB, SUI, SBB, SBI, CMP, and
CMI. Although the same result will be obtained by
addition of a complemented number or subtraction of an uncomplemented number, the resulting
Carry bit will be different.
EXAMPLE:
-127 D = 1 0 0 0 0 0 0 1 B = 81 H
-128D = 1 0000000 B = 80H
To perform the subtraction 1AH-OCH, the following
operations are performed:
Take the two's complement of OCH=F4H
Add the result to the minuend:
1AH = 0 0 0 1 1 0 1 0
+(-OCH) = F4H = 1 1 1 1 0 1 00
00001 1 1 0 = OEH the correct answer
When a byte is interpreted as an unsigned two's complement number, its value is considered positive and in the
range 0 to 255 10 :
+12D = 0000 1 1 00
+(-15D) = UJ...lQ.QQ.1
(j]
1 1 1 1 1 1 0 1 = -3D
causes carry to be reset
o = 0 0 0 0 0 0 0 0 B = OH
1 =00000001 B=1H
127D=01111111 B=7FH
128D = 1 0 0 0 0 0 0 0 B = 80H
oplab:
DB
occurrence of a "borrow."
Example:
(1)
(2)
13
Example:
Examples:
Instruct ion
HERE:
WORD1:
WORD2:
STR:
MINUS:
DB
DB
DB
DB
DB
A3
OA25
5A
535452494E472031
FD
HERE:
OS
OS
10
; Reserve the next 10 bytes
10H ; Reserve the next 16 bytes
Code
Operand
oplab:
OW
list
Description: The least significant 8 bits of the expression are stored in the lower address memory byte (oplab),
and the most significant 8 bits are stored in the next higher
addressed byte (oplab +1). This reverse order of the high and
low address bytes is normally the case when storing addresses in memory. This statement is usually used to create address constants for the transfer-of-control instructions; thus
LIST is usually a list of one or more statement labels appearing elsewhere in the program.
LABEL:
COMP
FILL
3C01 H, 3CAEH
not used
STCorCMC
Optional instruction label
Label
Code
oplab:
CMC
Operand
Assembled
Data (hex)
OW
OW
DW
OP
Format:
ADD1:
ADD2:
ADD3:
Operand
Examples:
Instruction
Code
1C3B
B43E
013CAE3C
Note that in each case, the data are stored with the
least significant 8 bits first.
Format:
oplab:
Code
OS
Code
oplab:
STC
biffJ
Label
Label
Operand
O l11 1
Operand
LJ
exp
14
Rev. B
illustrate:
OCR M references
registers
Format:
Label
Operan~
Code
oplab:
INR
GlJ
I;lJ
reg
Hand
reg
~
[i;]
B,C,D,E,H,L,M o,A
Memory before
Memory after
OCR M
DCRM
~.~8
1 0 0
001
010
011
100
101
110
111
indicating
memory location 3A7C
register C
register 0
register E
register H
regi ster L
memory ref. M
register A
Code
oplab:
CMA
Description: Each bit of the contents of the accumulator is complemented (producing the one's complement).
Example:
If register C contains 99H, the instruction:
INR C
will cause register C to contai n 9AH
Example:
If the accumulator contains 51 H, the instructionCMA
will cause the accumulator to contain OAEH.
= 01 01 0001 = 51 H
Accumulator = 1 0 1 0 1 1 1 0 = AEH
Accumulator
Format:
Label
Operan~
Code
oplab:
..====;
~I
~;eg
reg
Format:
B,C,D,E,H,L,M or A
for
for
for
for
for
for
for
register C
register 0
register E
register H
register L
memory ref. M
register A
oplab:
DAA
Operand
~,
.., . ,
"-'-
-----
"
_.
decimal digits
- .. ~_the followin.!Lt~o_ste.Q.p..!()cE!$~
-(1)
,._--~
-_.,
,-'
(2)
Example:
Code
Label
15
bits occurs during Step (2). the normal Carry bit is set;
otherwise, it is unaffected:
src
dst
==:===-::~==
NOTE: This instruction is used when adding decimal numbers. It is the only instruction whose operation is
affected by the Auxiliary Carry bit.
(b)
76543210
Accumulator = 1 0 0 1
+6
101 0
1 0 1 1 = 9BH
01 1 0
0001=A1H
\(2)
Since bits 0-3 are greater than 9, add 6 to the accumulator. This addition will generate a carry out of the
lower four bits, setting the Auxil iary Carry bit.
Bit No.
Auxiliary Carry = 1
Code
oplab:
Operand
MOV
Carry = 1
dst,
src
Label
oplab:
Code
Operand
OP
rp
oplab
NOP
A,B,C,D,E,H,L, or M
(dst and src not
both = M)
- or-
NOP INSTRUCTIONS
Code
1 for LDAX
When a memory reference is specified in the MOV instruction, the addressed location is specified by the Hand L
registers. The L register holds the least significant 8 bits of
the address; the H register holds the most significant 8 bits.
Accumulator = 1 0 1 00 0 0 1 = A1H
+6=0110
IJ 00000001
Label
ofor STAX
76543210
1<-.
register B
register C
register D
register E
register H
register L
memory reference M
register A
Operand
"Bor D
STAX or LDAX
MOV Instruction
Format:
Description: No operation occurs. Execution proceeds
with the next sequential instruction.
Label
Code
oplab:
M~dst,src
src
dst
Operand
16
None
Example 1:
Label
Code
Example:
If register 0 contains 93H and register E contains
8BH, the instruction:
Operand
Comment
A,E
MOV
0,0
MOV
LDAX
REGISTER OR MEMORY TO
ACCUMULATOR INSTRUCTIONS
This section describes the instructions which operate
on the accumulator using a byte fetched from another register or memory. Instructions in this class occupy one byte as
follows:
reg
M,A
Format:
..
Code
oplab:
~rp
Operand
STAX B
oplab:
Code
Operand
op
reg
'" A,B,C,D,E,H,L, or M
ADD, ADC, SUB, SBB, ANA, XRA, ORA
or CMP
Format:
Label
Code
oplab:
LDAX
Operand
.-./ rp
k'
--
register B
001 for register C
010 for register 0
011 for register E
100 for register H
101 for register L
110 for memory
reference M
111 for register A
tO~D for
Format:
Label
Code
oplab:
ADD
-I-
Operand
reg
r====
~'---L..re_gL-..J
17
y--
3DH
42H
CARRY
RESU LT
Example 1:
Assume that the D register contains 2EH and the accumulator contains 6CH. Then the instruction:
= 00 1 1 1 1 0
= 0 1 0000 1
=
= 10 0 0 0 0 0
Accumulator
Carry
Sign
Zero
Parity
Aux. Carry
ADD D
will perform the addition as follows:
2EH = 00101110
6CH = 01101100
9AH = 10011010
The Zero and Carry bits are reset; the Parity and Sign
bits are set. Since there is a carry out of bit A 3 , the Auxiliary
Carry bit is set. The accumulator now contains 9AH.
1
0
1
0 = 80H
80H
o
1
o
o
1
Example 2:
Format:
The instruction:
ADD A
will double the accumulator.
Label
Code
oplab:
SUB
~
Operand
~reg
~........L~_eg.L.1
.....J
Format:
Label
Code
oplab:
ACD
Operand
~reg
'"
~........L!r_eg.L.'
.....J
SUB A
Example:
3EH = 0 0 1 1 1 1 1 0
+(-3EH) = 1 1 000001 negate and add one
+
1 to produce two's
_ _ _ _ _ _ complement
carry -+ j] 00000000 Result = 0
ADC C
will perform the addition as follows:
3DH = 00 1 1 1 1 0 1
42H = 0 1 0 0 0 0 1 0
CARRY =
0
RESULT=01111111=7FH
7FH
o
o
o
o
o
The Parity and Zero bits will also be set, and the Sign
bit will be reset.
Thus the SUB A instruction can be used to reset the
Carry bit (and zero the accumulator).
18
Example:
Format:
Label
Code
oplab:
SBB
-}
Operand
~reg
r==
~'-..J~,-e_gL.'
ANA C
will act as follows:
-J
Accumulator = 1 1 1 1 1 1 0 0 = OFCH
C Register
=0 0 0 0 1 1 1 1 = OFH
Result in
Accumulator =0 0 0 0 1 1 0 0 = OCH
Format:
Example:
Assume that register L contains 2, the accumulator
contains 4, and the Carry bit = 1. Then the instruction SBB
L will act as follows:
Label
Code
Operand
oplab:
XRA
reg
~'-_'L.re_gL.1
JC
The final result stored in the accumulator is one, causing the Zero bit to be reset. The. Carry bit is reset since this
is a subtract operation and there was a carry out of the high
order bit position. The Auxiliary Carry bit is set since there
was a carry out of bit A 3 . The Parity and the Sign bits are
reset.
Since any bit EXCLUSIVE-ORed with itself produces zero, the EXCLUSIVE-OR can be used to zero the
accumulator.
Label
Format:
Label
Code
Operand
oplab:
ANA
reg
~
+ ;:=:::.=,
Code
Operand
XRA
MOV
MOV
A
B,A
C,A
XRA B
will produce the one's complement of the B register in the
accumulator.
19
Rev. B
Example 3:
Testing for change of status.
Many times a byte is used to hold the status of several
(up to eight) conditions within a program, each bit signifying whether a condition is true or false, enabled or disabled,
etc.
Label
Code
Operand
LA:
LB:
CHNG:
MOV
INX
MOV
XRA
A,M
H
B,M
B
STAT:
ANA
STAT2:
STAT1 :
OS
OS
; STAT2 to accumulator
; Address next location
; STAT1 to B register
; EXCLUSIVE-OR
; STAT1 and STAT2
; AND result with STAT1
ORA C
acts as follows:
Accumulator = 0 0 1 1 00 1 1 = 33H
C Register
= 0 0 0 0 1 1 1 1 = OFH
Accumulator = 00 111111 =3FH
Result =
Format:
Label
Code
oplab:
CMP
t
76543210
STAT1 = 5CH =
STAT2 = 78H =
EXCLUSIVE-OR'
o 1 0 1 1 100
01111000
00100100
00100100
01011100
00000100
NOTE:
Example 1:
Format:
Label
reg
I
reg
~
WliliJ
For example:
Bit Number
Operand
Operand
oplab:
Accumulator
+ (-E Register)
OAH
-5H
- - - - - IJ
0000 10 10
111110 11
00000 1 0 1 = result
20
Description: The Carry bit is set equal to the highorder bit of the accumulator. The contents of the accumulator are rotated one bit position to the left, with the highorder bit being transferred to the low-order bit position of
the accumulator.
Example 2:
If the accumulator had contained the number 2H, the
internal subtraction would have produced the following:
a a aa a a a
a
Accumulator
02H
1
+ (-E Register) = -5H = 1 1 1 1 1 1 1
OJ 1 1 1 1 1 1 a 1 = result
The Zero bit would be reset and the Carry bit set,
indicating E greater than A.
acts as follows:
Before R LC is executed: Carry
Example 3:
Assume that the accumulator contains -1 BH. The internal subtraction now produces the following:
Accumulator
-lBH
o1EEEIiliJiliEJ]
After R LC is executed:
11100101
= 1111 1 1 1
~~
---IJ
Accumulator
11100000
Carry = 1
A = OE5H
Label
Code
oplab:
RRC
..,
10
0 0
1 1
[;]iliJiJ
t
00 for R LC
01 for RRC
10 for RAL
11 for RAR
Code
Example:
Operand
op
~
+-
not used
RRC
acts as follows:
Before R RC is executed:
oplab:
RLC
Carry
rEEEIiliJiliEJ r0
Format:
Label
Accumulator
Operand
After R RC is executed:
>l-
A = 79H
21
Carry=O
Format:
Label
Code
oplab:
RAL
Accumulator
Carry
rillillEE-Eb
Operand
-j.-
~
A = OB5H
Carry=O
Description: The contents of the accumulator are rotated one bit position to the left.
Label
Code
Operand
oplab:
PUSH
rp
RAL
acts as follows:
Before RAL is executed: Carry
Accumulator
GJ
Carry=1
A=6AH
The contents of the first register are saved at the memory address one less than the address indicated by the stack
pointer; the contents of the second register are saved at the
address two less than the address indicated by the stack
pointer. If register pair PSW is specified, the first byte of information saved holds the contents of the A register; the
second byte holds the settings of the five condition bits,
i.e., Carry, Zero, Sign, Parity, and Auxiliary Carry. The format of this byte is:
Code
oplab:
RAR
Operand
7 6 543 2 1 0
Description: The contents of the accumulator are rotated one bit position to the right.
JJ
State of auxiliary
Carry bit
Example:
Assume that the accumulator contains 6AH. Then the
instruction:
\ iL\
' - - - - - - - always 0
In any case, after the data has been saved, the stack
pointer is decremented by two.
RAR
acts as follows:
Example 1:
22
Rev. B
Assume that register D contains 8FH, register E contains 9DH, and the stack pointer contains 3A2CH. Then the
instruction:
PUSH D
stores the D register at memory address 3A2BH, stores the
E register at memory address 3A2AH, and then decrements
the stack pointer by two, leaving the stack pointer equal to
3A2AH.
[
Before PUSH
In any case, after the data has been restored, the stack
pointer is incremented by two.
After PUSH
HEX
MEMORY ADDRESS MEMORY
SP
-+
FF
3A29
FF
FF
3A3A
9D
FF
3A2B
8F
FF
3A2C
FF
SP
Example 1:
Assume that memory locations 1239H and 123AH
contain 3DH and 93H, respectively, and that the stack
poi nter conta ins 1239 H. Then the instructi on:
POP H
Example 2:
Assume that the accumulator contains 1 FH, the stack
pointer contains 502AH, the Carry, Zero and Parity bits all
equal 1, and the Sign and Auxiliary Carry bits all equal O.
Then the instruction:
Before POP
MEMORY
PUSH PSW
stores the accumulator (1FH) at location 5029H, stores the
value 47H, corresponding to the flag settings, at location
5028H, and decrements the stack pointer to the value
5028H.
SP
Code
Operand
oplab:
POP
rp
~'B'D'H'
DC
PSW
for
for
for
for
--+
1238
1239
123A
123B
3D
93
FF
3D
93
FF
+- SP
ffiJ
ITQ]
[]I]
[]Q]
Example 2:
Assume that memory locations 2COOH and 2C01 H
contain C3H and FFH respectively, and that the stack
pointer contains 2COOH. Then the instruction:
~
" ' - - - - 00
01
10
11
After POP
HEX
ADDRESS MEMORY
POP PSW
registers Band C
registers D and E
registers Hand L
flags and register A
will load the accumulator with FFH and set the condition
bits as follows:
C3H= 1 1 0 0 0 0 1 1
23
II I
~) Carry
bit = 1
Parity bit = 0
Rev. B
Format:
Label
Code
Operand
oplab:
DAD
...!:....
~ ~ 8,D,H, or SP
INX D
will cause register D to contain 39H and register E to contain OOH.
the
INX SP
will cause register SP to contain OOOOH.
Description: The 16-bit number in the specified register pair is added to the 16-bit number held in the Hand L
registers using two's complement arithmetic. The result replaces the contents of the Hand L registers.
Label
Code
Operan<!
Example 1:
oplab:
DCX
rp
Assume that register 8 contains 33H, register C contains 9FH, register H contains A1 H, and register L contains
78H. Then the instruction:
'B,D,H, or SP
DAD 8
Register H now contains D5H and register L now contains 1AH. Since no carry out was produced, the Carry bit
is reset = O.
Example 2:
Example:
The instruction:
DAD H
will double the 16-bit number in the Hand L registers
(which is equivalent to shifting the 16 bits one position to
the left).
DCX H
Format:
Format:
Label
Code
Operand
oplab:
INX
...!:....
/
Label
Code
oplab:
XCHG
Operand
~B,D,H,orSP
24
Example:
Format:
After XCHG
Before XCHG
[ill
WJ
[QQ]
[]
[QQ]
[]
[]LJ
[]
Label
Code
oplab:
SPHL
Operand
Format:
Label
Code
oplab:
XTHL
Operand
IMMEDIATE INSTRUCTIONS
This section describes instructions which perform operations using a byte or bytes of data which are part of the
instruction itself.
Description: The contents of the L register are exchanged with the contents of the memory byte whose address is held in the stack pointer SP. The contents of the H
register are exchanged with the contents of the memory
byte whose address is one greater than that held in the stack
pointer.
Example:
~ ,I~~,d,a~a, I,hi~h,~a,t~ I
If register SP contains 10ADH, registers Hand L contain OBH and 3CH respectively, and memory locations
1OADH and 1OAEH contain FOH and ODH respectively, the
instruction XTH L will perform the following operation:
Before XTHL
After XTHL
MEMORY
~.
HEX
ADDRESS
[Q[]
[K]
[Q]
[ill
FO
OD
FF
10AC
lOAD
10AE
lOAF
tf]::=,=re::g==~L-L.-L.~d_a.L.t_a
-L.--L.-...L..-
m
3C
08
FF
registers Band C
registers D and E
registers Hand L
register SP
MEMORY
SP
""----00 for
01 for
10 for
11 for
SP
25
register B
register C
register D
register E
register H
register L
memory ref. M
register A
Rev. B
Format:
~,::::=O:::P~~L..-,--,--,-d_aL.ta-,--,--,-_
Label
oplab:
LXI
Operand
rp, data
LXI H,103H
LXI H,259
LXI H,STRT
B,D,H,orSP
Example 2:
The following instruction loads the stack pointer with
the value 3ABCH:
LXI SP,3ABCH
-orLabel
oplab:
Code
MV I
\"
Operand
reg, data
----
8-b;1 d'"
Format:
q,,",;,y
Label
oplab:
A,B,C,D,E,H,L, or M
g , r e g,
Label
oplab:
Code
OP
None
oplab:
,,''
Code
Operand
Label
Code
~ rP..:--da~a \.
Code
.. MVI
Operand
reg , dtta
J
A
data
Operand
data
Example
LI--
1_.
ADI,ACI,SUI,SBI,ANI,XRI,ORI,
or CPI
26
Label
Code
Operand
Assembled Data
M1:
M2:
M3:
MVI
MVI
MVI
H,3CH
L,OF4H
M,OFFH
26EC
2EF4
36FF
Format:
Label
Code
oplab:
ACI
Operan~
i/data
I<"
"-
NOTE: The instructions at Ml and M2 above could be replaced by the single instruction:
data
,J
LXI H, 3CF4H
Example:
Format:
Label
oplab:
Code
~ADI
Operand
l<!
data
~===~::=:::::
~1-~~~d_a
....t_a.L-""""...a..-
Label
Code
Operand
C1:
C2:
C3:
MVI
ACI
ACI
A,56H
-66
66
Assembled Data
3E56
CEBE
CE42
Assuming that the Carry bit = 0 just before the instruction at C2 is executed, this instruction will produce the
same result as instruction AD3 in the example of Section
3.10.3.
That is:
Accumulator = 14H
Carry
= 1
Example:
Code
Operand
AD1:
AD2:
AD3:
MVI
ADI
ADI
A,20
66
-66
Assem bl ed Data
3E14
C642
C6BE
Format:
Label
oplab:
Code
k'
SUI
27
Example:
This instruction can be used as the equivalent of the
OCR instruction.
Label
Code
Sl:
MVI
SUI
Operand
Assembled Data
A,O
1
3EOO
0601
Accumulator = OH = 00000000
-Sl Immediate Data = -1 H = 11111111 two's complement
Result
= 11111111 = -1 H
Since there was no carry, and this is a subtract operation, the Carry bit is set, indicating a borrow.
Ar.cumulator = OH = 00000000
11111111
---11111110 = -2H = Resu It
carry out = 0 causing the Carry bit to be set
This time the Carry and sign bits are set, while the
zero, parity, and auxi Iiary Carry bits are reset.
Format:
Label
oplab:
Code
J!'SBI
Operand
Format:
""data
A
Label
~---'---'--L_d..l-at_a..L1
oplab:
- -'-.-L--J
.,...
Code
Operan<:!
ANI
,/ data
~
Description: The Carry bit is internally added to the
byte of immediate data. This value is then subtracted from
the accumulator using two's complement arithmetic.
data
This instruction and the SBB instruction are most useful when performing multibyte subtractions. For an example of th is, see the section on Multibyte Addition and
Subtraction in Chapter 4.
Label
Code
Operand
Al:
MOV
ANI
A,C
OFH
Assembled Data
79
E60F
Example:
Label
Code
Assembled Data
XRA
SBI
AF
DEOl
The contents of the C register are moved to the accumulator. The AN I instruction then zeroes the high-order
four bits, leaving the low-order four bits unchanged. The
Zero bit will be set if and only if the low-order four bits
were originally zero.
If the C register contained 3AH, the ANI would perform the following:
Accumulator = 3AH = 00111010
AND (Al Immediate Data) = OFH = 00001111
Result =
00001010 = OAH
28
If the C register contained OB5H, the ORI would perform the following:
Format:
Label
Code
____ XRI
Accumulator=OB5H = 10110101
OR (ORl Immediate data) = OFH = 00001111
Result = 10111111 =OBFH
~---l---lL....-L..d_aL..ta....L.--L-'J
oplab:
data
.... j
Description: The byte of immediate data is EXCLUSIV E-ORed with the contents of the accumulator. The carry
bit is set to zero.
Label
Code
oplab:
CPI
data
;/
.A
any bit EXCLUSIVEORed with a one is comand any bit EXCLUSIVE-ORed with a zero is
th is instruction can be used to complement spethe accumulator. For instance, the instruction:
XRI 81 H
will complement the least and most significant bits of the
accumulator, leaving the rest unchanged. If the accumulator
contained 3BH, the process would work as follows:
Format:
Label
Code
oplab:
ORt
Qperan~
,data
~l-..J......J........L.d_a.L.t_a.L.-.L.I.J
Example:
-~---l
Label
OR1:
Assembled Data
MVl
A,4AH
40H
3E4A
FE40
Example:
MOV
ORt
Operand
Code
Code
CP~
Label
Operand
A,C
OFH
Ass~mbly
Data
79
F60F
The contents of the C register are moved to the accumulator. The ORI instruction then sets the low-order four
bits to one, leaving the high-order four bits unchanged.
29
Rev. B
Code
oplab:
LDA
Operand
Jt' adr ""
most significant 8
bits of a memory
address
Label
STA
LOA
SHLD
LHLD
The following instructions will each replace the accumulator contents with the data held at location 300H:
LOAD:
GET:
LOA
LOA
LOA
300H
3*(16*16)
200H+256
first.
The general assembly language format is:
Label
Code
label:
l
STA
Operand
"-Linst~uction
op
exp
Format:
Label
oplab:
Optional
Code
Operand
SHLD
b~ilil~1'~'Y~'1~', I,h;9,h:',d~~ I
label
Code
Operand
SHLD
10AH
Memory
Before SHLD
Example:
The following instructions will each store the contents
of the accumulator at memory address 5B3H:
SAC:
LAB:
STA 5B3H
STA 1459
STA 010110110011 B
0
00
00
00
HEX
ADDRESS
109
lOA
lOB
10C
I
I
30
Memory
After SHLD
00
29
AE
00
The three-byte instructions in this class cause a transfer of program control depending upon certain specified conditions. If the specified condition is true, program execution
will continue at the memory address formed by concatenating the 8 bits of HI ADD (the third byte of the instruction)
with the 8 bits of LOW ADD (the second byte of the instruction). If the specified condition is false, program execution
will continue with the next sequential instruction.
Format:
Label
Code
Operand
oplab:
LHLD
Label
Code
Example:
oplab:
PCHL
"-'not used
25BH
Operand
will load the L register with F FH, and will load the H register with 03H.
-orLabel
JUMP INSTRUCTIONS
Code
label:
This section describes instructions which alter the normal execution sequence of instructions. Instructions in this
class occupy one or three bytes as follows:
op
Operand
EXP
"-
~ A 16-bit address
I
I
PCHL
Operand
000 for
001 for
010 for
all for
100 for
101 for
110 for
111 for
Code
oplab:
most significant 8
bits of a memory
address
Label
JMP or JNZ
JZ
JNC
JC
JPO
JPE
JP
JM
will cause program execution to continue with the instruction at memory address 413EH.
31
Example 2:
Arbitrary
Memory
Address
----
Label
Code
Operand
40CO
ADR:
DW
LOC
4100
STRT:
LHLD ADR
PCHL
2AC040
E9
4200
LOC:
NOP
00
Assembled
Data
0042
JC Jump If Carry
Format:
Label
Code
oplab:
JC
Operand
adr
j,!'
Program execution begins at STRT. The LH LD instruction loads registers Hand L from locations 40C1 H
and 40COH; that is, with 42H and OOH, respectively. The
PCHL instruction then loads the program counter with
4200H, causing program execution to continue at location
LOC.
"'"
Description: If the Carry bit is one, program execution conti nues at the memory address adr.
Condition bits affected: None
For a programming example, see the section on JPO
later in th is chapter.
JMP JUMP
JNC Jump If No Carry
Format:
Format:
Arbitrary
Memory
Address
Label
Code
Operand
Assembled
Data
3COO
3C03
AD:
JMP
ADI
CLR
2
C3003E
C602
LOAD: MVI
JMP
A,3
3C03H
3E03
C3033C
CLR:
A
$-101 H
AF
C3003D
3EOO
3E01
JNC
i/
adr
..".
Example:
3D02
oplab:
Operand
~DOO
Code
Description: If the Carry bit is zero, program execution continues at the memory address adr.
Label
XRA
JMP
JZ Jump If Zero
Format:
Label
Code
oplab:
JZ
Operan~
i/
adr
""
32
Format:
-....-.
Label
Code
oplab:
JNZ
Format:
Operand
adr
0/
"'It
Label
Code
oplab:
JPO
Operand
adr
0/
Description: If the Zero bit is zero, program execution continues at the memory address adr.
Description: If the Parity bit is zero (indicating a result with odd parity), program execution conti nues at the
memory address adr.
JM Jump If Minus
Format:
Label
Code
oplab:
JM
Description: If the Sign bit is one (indicating a negative result), program execution continues at the memory
address adr.
Label
Code
Operand
Assembled
Data
ONE:
MOV
ANI
JZ
JNZ
A,C
80H
PLUS
MINUS
79
E680
CAXXXX
C2XXXX
TWO:
MOV
RLC
JNC
JMP
A,C
79
07
D2XXXX
C3XXXX
JP Jump If Positive
Format:
Label
Code
oplab:
JP
Operand
THREE:
adr
"
'Ii
PLUS:
MINUS:
Description: If the sign bit is zero, (indicating a positive result), program execution continues at the memory
address adr.
JPE
adr
'Ii
iL'
~.
I I
I" I
hi add
MOV
ADI
JM
PLUS
MINUS
A,C
0
MINUS
SIGN BIT
RESET
79
C600
FAXXXX
JPE
'Ii
, I I I I I ,
33
CALL Call
Format:
Label
Code
Operand
oplab:
CALL
sub
t
most significant 8
bits of a memory
address
CC Call If Carry
Format:
Label
Code
oplab:
CC
CNZ
CZ or CALL
CNC
CC
CPO
CPE
CP
CM
Code
Operand
i label:
op
sub
Format:
Label
Code
Qperand
oplab:
CNC
sub
34
Rev. B
CP Call If Plus
Format:
Label
Code
Operand
oplab:
CP
sub
CZ Call If Zero
Format:
Label
Code
Operand
oplab:
CZ
sub
Description: If the Sign bit is zero (indicating a positive result), a call operation is performed to subroutine sub.
~ 111"11
lowadd I hiadd I
1""11
Format:
Label
Code
Operand
oplab:
CPE
sub
Code
Operand
oplab:
CNZ
sub
It'
'\I
~~'
~1111111
'I
.. I I I I I I I .
Label
Code
Operand
oplab:
CPO
sub
CM Call If Minus
Format:
Label
Code
oplab:
CM
~'111'1QOI'
1"
"
"
hi
'
~dd
I
'.
35
xxx
I
~I
L.L...L.J
~ 1 for RET,
o otherwise
Code
oplab:
oplab:
RNC
Operand
Operand
op
Code
Label
ET,RC,RNC,RZ,RNZ,RM,RP,RPE,RPO
RZ Return If Zero
Format:
Label
Code
oplab:
RZ
Operand
RET Return
Format:
Label
Code
oplab:
RET
Operand
Description: If the Zero bit is one, a return operation
is performed.
Format:
Thus, execution proceeds with the instruction immediately following the last call instruction.
RC Return If Carry
oplab:
RC
oplab:
RNZ
Operand
Format:
Code
Code
Label
Label
Operand
36
Rev. B
RM Return If Minus
Format:
Label
Code
oplab:
RM
Operand
RST INSTRUCTION
This section describes the RST (restart) instruction,
which is a special purpose subroutine jump. This instruction
occupies one byte.
Format:
Label
Code
oplab:
RST
RP Return If Plus
30/
Code
oplab:
RP
/t
@_....L~_xP.L,_biliJ
Format:
Label
/ e xp
Operand
Description: If the Sign bit is zero (indicating a positive result). a return operation is performed.
OOOOOOOOOOEXPOOOB
Normally, this instruction is used in conjunction with
up to eight eight-byte routines in the lower 64 words of
memory in order to service interrupts to the processor. The
interrupting device causes a particular RST instruction to be
executed, transferring control to a subroutine which deals
with the situation as described in Section 6.
Code
oplab:
RPE
Opera~~
Example:
Description: If the Parity bit is one (indicating even
parity), a return operation is performed.
Label Code
Operand
RST
10 - 7
RST
E SHL 1
RST
RST
Code
oplab:
RPO
\.
L-
3
~
... _. -
Comment
; Call the subrouti ne at
; address 24 (011000B)
; Call the subroutine at
; address 48 (11 OOOOB). E
; is equated to 11B.
; Invalid instruction
; Call the subroutine at
; address 24 (011000B)
--'
37
t\
device no.
~
'"
'-------1o
1 for IN
o for OUT
for EI
for 01
Code
label:
Operand
op
The general assembly language format is:
"---- 00'
Label
u"d
Code
label:
Operand
exp
op
EI or 01
IN or OUT
EI Enable Interrupts
Format:
Label
Code
oplab:
EI
Operand
IN Input
Format:
Description: This instruction sets the I NTE flip-flop,
enabling the CPU to recognize and respond to interrupts.
Label
Code
Operand
oplab:
IN
exp
01 Disable Interrupts
Format:
Label
Code
oplab:
01
Operand
Label Code
INPUT/OUTPUT INSTRUCTIONS
This section describes the instructions which cause
data to be input to or output from the 8080. Instructions in
this class occupy two bytes as follows:
38
Operand
IN
IN
10/2
Comment
; Read one byte from input
; device # 0 into the
; accumulator
; Read one byte from input
; device # 5 into the
; accumulator
OUT Output
Format:
Label
Code
oplab:
OUT
Code
Operand
op
opnd
Comment
Example:
Label Code
Comment
Operand
OUT
10
OUT
1FH
ORG Origin
Format:
Label
Code
Operand
oplab:
ORG
exp
Format:
A 16-bit address
Label
Code
oplab:
HLT
not used
If no GRG appears before the first machine instruction or data byte in the program, assembly will begin
at location O.
Example 1:
Description: The program counter is incremented to
the address of the next sequential instruction. The CPU then
enters the STOPPED state and no further activity takes
place until an interrupt occurs.
Hex Memory
Address
Label
1000
1001
1003
PSEUDO - INSTRUCTIONS
This section describes pseudo-instructions recognized
by the assembler. A pseudo-instruction is written in the same
fashion as the machine instructions described earlier in this
chapter, but does not cause any object code to be generated.
1050
39
Code
ORG
MOV
ADI
JMP
HERE: ORG
NEXT: XRA
Operand
1000H
A,C
2
NEXT
1050H
A
Assembled
Data
79
C602
C35010
AF
The first ORG pseudo-instruction informs the assembler that the object program will begin at memory address
1000H. The second ORG tells the assembler to set its location counter to 1050H and continue assembling machine instructions or data bytes from that point. The label HERE
refers to memory location 1006H, since this is the address
immediately following the jump instruction. Note that the
range of memory from 1006H to 104FH is still included in
the object program, but does not contain assembled data. In
particular, the programmer should not assume that these
locations will contain zero, or any other value.
SET
Example 2:
Format:
Memory
Address Label
2COO
2COt
2C04
2Cl0
--
MOV
JMP
OS
NEXT: XRA
Code Operand
-- -----
A,C
MOV
A,C
NEXT
JMP NEXT
12
ORG
$+t2
A
NEXT: XRA
A
Label
Code
Opera l1E
name
SET
exp
Assbl.
Data
--
An expression
Required name
79
'C3102C
AF
EQU Equate
Format:
Label
Code
Qperand
name
EQU
exp
Label
Code
Qperand
IMMED
SET
ADI
SET
ADI
5
IMMED
10H-6
IMMED
IMMED
t
An expression
Assembled Data
C605
C60A
Required name
Example 2:
Before every assembly, the assembler performs the following SET statements:
Label
B
C
0
E
H
L
M
A
Label
Code
Operand
PTO
EQU
Assembled Data
Code
Qperand
SET
SET
SET
SET
SET
SET
SET
SET
0
1
2
3
4
5
6
7
OUT
PTO
0308
MOV 2,7
40
Example:
-..-'
Label
Code
oplab:
END
Operand
Label
Code
COND
SET
IF
MOV
ENDIF
SET
IF
MOV
ENDIF
XRA
COND
Description: The END statement signifies to the assembler that the physical end of the program has been
reached, and that generation of the object program and (possibly) listing of the source program should now begin,
One and only one END statement must appear in
every assembly, and it must be the (physically) last statement of the assembly.
Operand
Assembled Data
OFFH
COND
A,C
79
0
COND
A,C
A9
Code
name
MACRO
Qpera~~
list
Format:
Label
oplab:
A Iist of expressions,
normally ASCII constants
Code
Required name
IF
statements
oplab:
ENDM
an expression
Description: For a detailed explanation of the definition and use of macros, together with programming
examples, see Chapter 3.
statements
oplab:
The assembler accepts the statements between MACRO and ENDM as the definition of the macro named
"name." Upon encountering "name" in the code field of an
instruction, the assembler substitutes the parameters specified in the operand field of the instruction for the occurrences of "list" in the macro definition, and assemblies the
statements.
ENDIF
Description: The assembler evaluates expo If exp evaluates to zero, the statements between IF and ENDIF are ignored. Otherwise the intervening statements are assembled
as if the IF and EN D IF were not present.
NOTE:
41
Macros (or macro instructions) are an extremely important tool provided by the assembler. Properly utilized,
they will increase the efficiency of programming and the
readability of programs. It is strongly suggested that the user
become familiar with the use of macros and utilize them to
tailor programming to suit his specific needs.
Code
SHRT
MACRO
RRC
ANI
7FH
ENDM
Operand
Label
Code
SHRT
MACRO
RRC
RRC
ANI
Operand
ANI
ENOM
7FH
Label
; Rotate accumulator
; right
; Clear high-order bit
Code
Operand
LOA
SHRT
TEMP
Label
; Load accumulator
Code
Operand
LDA
RRC
ANI
TEMP
Code
Operand
LOA
SHRT
STA
TEMP
; Macro reference
TEMP
We can now reference the macro by placing the following instructions later in the same program:
Label
7FH
Code
Operand
LOA
RRC
ANI
STA
TEMP
;I
Macro reference
7FH
TEMP
; Load accumulator
7FH
43
Code
Label
Operand
MACRO
RRC
7FH
ANI
D
DCR
JNZ
LOOP
ENDM
LOOP:
; Rotate right once
; Clear the high-order bit
; Decrement shift counter
; Return for another shift
Code
Operand
LDA
MVI
SHV
STA
TEMP
D,3
Label
LDA
MVI
LOOP: RRC
ANI
DCR
JNZ
STA
C,5
SHV
Code
Operand
MVI
RRC
ANI
DCR
JNZ
E,2
Label
TEMP
TEMP
D,3
7FH
D
LOOP
TEMP
Macro Definition
Format:
Label
Code
Operand
name
MACRO
plist
mac r
Code
SHV
MACRO REG,AMT
MVI
REG,AMT
Operand
7FH
REG
Operand
LDA
TEMP
"plist" is a list of expressions (usually unquoted character strings) which indicate parameters specified by the
macro reference that are to be substituted into the macro
body. These expressions, which serve only to mark the positions where macro parameters are to be inserted into the
macro body, are called dummy parameters.
bod Y
Description: The macro definition produces no assembled data in the object program. It merely indicates to the
assembler that the symbol "name" is to be considered equivalent to the group of statements appearing between the
pseudo instructions MACRO and ENDM (see Chapter 2 MACRO and ENDM Macro Definition). This group of statements, called the macro body, may consist of assembly language instructions, pseudo-instructions (except MACRO or
ENDM), comments, or references to other ma,cros.
LOOP
Code
ENDM
7FH
E
LOOP
Operand
Label
JNZ
ENDM
E,2
RRC
ANI
DCR
Operand
Note that the D register contents will change whenever the SHV macro is referenced, since it is used to specify
shift count.
LOOP:
7FH
C
LOOP
MVI
RRC
ANI
DCR
JNZ
Code
LOOP:
Label
Operand
Code
C,5
Example:
44
label specified by the macro reference, loads the most significant 8 bits of the address into the C register, and loads the
least significant 8 bits of the address into the B register. (This
is the opposite of what the instruction LXI B,ADDR would
do).
Label
Code
Operand
Label
Code
Operand
LOAD
MACRO
MVI
MVI
ENDM
ADDR
C, ADDR SHR 8
B, ADDR AND OFFH
MACl
MACRO
XRA
OCR
ENDM
Code
Operand
MACl
C,D, ; DECREMENT
;REG C'
LABEL:
The reference:
INST:
The reference:
Code
Operand
LOAD
LABEL
Operand
MVI
MVI
C, LABEL SHR 8
B, LABEL AND OFFH
Operand
LOAD
INST
Operand
MVI
MVI
C,INST SHR 8
B, INST AND OFFH
C ; DECREMENT REG C
Code
Operand
MACl
E.B
Code
Operand
XRA
OCR
B
E
Macro Expansion
The result obtained by substituting the macro parameters into the macro body is called the macro expansion.
The assembler assembles the statements of the expansion
exactly as it assembles any other statements. In particular.
every statement produced by expanding the macro must be
a legal assembler statement.
The MACRO and ENDM statements inform the assembler that when the symbol LOAD appears in the code field
of a statement, the characters appearing in the operand field
of the statement are to be substituted everywhere the symbol
ADD R appears in the macro body, and the two MVI instructions are to be inserted into the statements at that point of
the program and assembled.
Example:
Given the macro definition:
XRA
OCR
Operand
The reference:
The reference:
Code
Code
Code
Operand
name
plist
Label
Code
MAC
MACRO
PUSH
ENDM
Pl
Pl
MAC
Operand
the reference:
MAC
PUSH
which will be flagged as an error.
45
Code
TMAC
MACRO
Code
EQMAC
VAL
MACRO
EQU
DB
ENDM
8
VAL
Operand
Label
Operand
Label
Code
Operand
VAL
DB1:
EQU
DB
EQMAC
EQU
DB
DB
VAL
DB2:
Assembled Data
06
VAL
8
08
06
VAL
VAL
LOOP:
JMP
EN OM
VAL is first defined globally with a value of 6. Therefore the reference to VAL at DB 1 produces a byte equal to
6. The macro reference EQMAC generates a symbol VAL
defined only within the macro expansion with a value of 8;
therefore the reference to VAL by the second statement of
the macro produces a byte equal to 8. Since th is statement
ends the macro expansion, the reference to VAL at DB2 refers to the global definition of VAL. The statement at DB2
therefore produces a byte equal to 6.
LOOP
Program
"Set" Names: Suppose that a "set" statement is generated by a macro. If its name has already been defined globally by another set statement, the generated statement will
change the global value of the name for all subsequent references. Otherwise, the name is defined locally, applying
only within the current macro expansion. These cases are
illustrated as follows:
TMAC
LOOP:
JMP
TMAC
LOOP:
JMP
Label
Code
STMAC
SYM
MACRO
SET
DB
ENDM
Operand
5
SYM
46
Code
SYM
DBl :
SET
DB
STMAC
SET
DB
DB
SYM
DB2:
Operand
Assembled Data
MAC4
0
SYM
00
ABC
5
SYM
SYM
05
05
MAC4
Operand
STMAC
SET
DB
DB
SYM
DB3:
14
3
'ABC'
the assembler would evaluate the expression 'ABC: producing the characters ABC as the value of parameter Pl. Then
the expansion is produced, and, since ABC is altered by the
first statement of the expansion, Pl will now produce the
value 14.
Expansion produced:
Using the same macro definition as above, the following program section is invalid:
Code
SET
DB
SYM is first defined globally with a value of zero, causing the reference at DBl to produce a byte of O. The macro
reference STMAC resets this global value to 5, causing the
second statement of the macro to produce a value of 5. Although this ends the macro expansion, the value of SYM remains equal to 5, as shown by the reference at DB2.
Label
ABC
ABC
SET
DB
14
ABC ; Assembles as 14
Assembled Data
5
SYM
SYM
05
The use of macros is an important programming technique that can substantially ease the user's task in the following ways:
**ERROR**
Since in this case SYM is first defined in a macro expansion, its value is defined locally. Therefore the second
(and final) statement of the macro expansion produces a
byte equal to 5. The statement at DB3 is invalid, however,
since SYM is unknown globally.
(a)
(b)
If an error in a macro definition is discovered, the program can be corrected by changing the definition and
reassembling. If the same routine had been repeated
many times throughout the program without using
macros, each occurrence would have to be located and
changed. Thus debugging time is decreased.
(c)
Duplication of effort between programmers can be reduced. Once the most efficient coding of a particular
function is discovered, the macro definition can be
made available to all other programmers.
(d)
Example:
Suppose that the following macro MAC4 is defined at
the beginning of the program:
Label
Code
Operand
MAC4
ABC
MACRO
SET
DB
ENDM
Pl
14
Pl
USEFUL MACROS
SET
47
Rev. B
Example:
Indicates address
of data
RI
Hex
Memory Address
134C
50
134D
13
134E
134F
1350
FF
------7)~
Label
Code
LIND
Comment
Code
Code
Operand
IXAD
MACRO
LXI
DAD
RP, BSADD
H, BSADD ; Load the base address
RP
; Add index to base
; address
Macro reference:
Label
Operand
Label
Code
Operand
LHLD
MOV
LABEL
C,M
Operand
MVI
MVI
IXAD
D,1
E,2EH
D,LABEL
Code
Operand
MVI
MVI
LXI
DAD
D,1
E,2EH
H, BSADD
D
Macro expansion:
C, LABEL
Macro expansion:
Label
Code
Comment
ENDM
Macro reference:
Label
Label
48
Jump to routine 1
2
3
4
5
6
7
8
CONDITION = CONDITION 1?
IF YES BRANCH TO ROUTINE 1
CONDITION = CONDITION 2?
IF YES BRANCH TO ROUTINE 2
BRANCH TO ROUTINE N
Main Program
Branch Table
Program
Jump
Routines
1
normal subroutine return
sequence not followed by
branch table program
49
Rev. B
Label
Code
Operand
START:
LXI
GTBIT:
RAR
JC
INX
INX
GETAD
H
H
JMP
MOV
INX
GTBIT
E,M
H
MOV
XCHG
D,M
GETAD:
; (H,L)=(H,L)+2 to
; point to next address
; in branch table.
Label
Code
Qperand
MINC:
INR
RNZ
INX
INR
RET
H
M
; Exchange D and E
; with Hand L.
; Jump to routine
; address.
PCHL
Comme~
DW
DW
ROUTl
ROUT2
DW
DW
DW
DW
DW
DW
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
Arbitrary
Memory Address
Arbitrary
Memory Address
2COO
The control routine at START uses the Hand L registers as a pointer into the branch table (BTB L) corresponding
to the bit of the accumulator that is set. The routine at
GETAD then transfers the address held in the corresponding
branch table entry to the Hand L registers via the D and E
registers, and then uses a PCH L instruction, thus transferring
control to the selected routine.
2EFO
CO 0
.::.3.::c:::.:'-*', MINe
CALL MINC
SUBROUTINES
Frequently, a group of instructions must be repeated
many times in a program. As we have seen in Chapter 3, it is
sometimes helpful to define a macro to produce these
groups. If a macro becomes too lengthy or must be repeated
many times, however, better economy can be obtained by
using subroutines.
A subroutine is coded like any other group of assembly
language statements, and is referred to by its name, which is
the label of the first instruction. The programmer references
a subroutine by writing its name in the operand field of a
CALL instruction. When the CALL is executed, the address
of the next sequential instruction after the CALL is pushed
onto the stack (see the section on the Stack Pointer in
Chapter 1), and program execution proceeds with the first
instruction of the subroutine. When the subroutine has completed its work, a RETURN instructiofl is executed;.. which
FF
FF
FF
2C
2C
00
00
FF
FF
FF
FF
50
~Stack
FF
~Stack
Pointer
Pointer
~Stack
Pointer
ADSUBD
Code
Operand
LXI
CALL
06
PLiST
08
PUSHI
OEH
PLlSH2
The second time ADSUB is called, the Hand L registers point to the parameter list L1ST2. The A and B registers
are loaded with 10 and 35 respectively, and the sum is stored
at L1ST2 + 2. Return is then made to the instruction at
RET2.
Comment-
ADSUBD CJ
H
CJ
RET1:
PLlST: DB
DB
DS
LXI
CALL
OA
L1ST2
23
L1ST2+1
20
L1ST2+2
RET2:
L1ST2: DB
DB
DS
ADSUB:
'--""
10
35
1
MOV
INX
A,M
H
MOV
ADD
INX
B, M
B
H
MOV
M,A
RET
This can be done by passing the subroutine a parameter list wh ich is a Iist of addresses of parameters, rather
than the parameters themselves, and signifying the end of
the parameter list by a number whose first byte is FFH
(assuming that no parameters will be stored above address
FFOOH).
51
Call to GENAO:
GENAO:
DOD
DR1
AOR2
f~
AOR3
AOR4
FFFF
Label
PLfST:
PARMl
PARM4
PARM3
[J PARM2
Code
Operand
LXI
CALL
H, PLiST
GENAO
; Calling program
OW
OW
PARMl
PARM2
PARM3
PARM4
OFFFFH
OW
OW
OW
PARM1:
08
DB
PARM4~
PABM3:
DB
13
PARM2:
DB
82
GENAO:
LOOP:
XRA
MOV
MOV
A
C,A
E, M
tNX
MOV
H
A,M
CPI
JZ
MOV
LDAX
ADD
INX
OFFH
BACK
O,A
0
C
H
JMP
MOV
RET
LOOP
A,C
BACK:
Comment
; Terminator
16
; Clear accumulator
; Save current total in C
; Get low order address byte
; of first parameter
; Get high order address byte
; of first parameter
; Compare to FFH
; If equal, routine is complete
; 0 and E now address parameter
; Load accumulator with parameter
; Add previous total
; Increment Hand L to point
; to next parameter address
; Get next parameter
; Routine done-restore total
; Return to calling routine
52
The sequence:
PLlST:
LXI
CALL
H, PLIST
GENAD
DW
DW
DW
PARM4
PARM1
OFFFFH
(a)
(b)
(c)
HIGH-ORDER BYTE
MULTIPLIER
MULTIPLICAND
OF RESULT
Start
00111100
00101010
00000000
Step 1 a --------------------------------------b
00000000
Step 2 a -------------------------------------b
00000000
S~p3a--------------------------------------00101010
b
00010101
Step 4 a --------------------------------------- 00111111
b
00011111
S~p5a---------------------------------~----01001001
b
00100100
Step 6 a --------------------------------------- 01001110
b
00100111
Srep7a--------------------------------------b
00010011
Srep8a--------------------------------------b
00001001
",-,,'
53
LOW-ORDER BYTE
OF RESULT
00000000
00000000
00000000
00000000
00000000
00000000
10000000
10000000
11000000
11000000
01100000
10110000
11011000
The program uses the B register to hold the most significant byte of the result, and the C register to hold the
least significant byte of the result.
Step 3: Test multiplier 2bit; it is 1, so add 2AH to highorder byte of result and shift 16-bit result right one
bit.
Step 4: Test multiplier 3-bit; it is 1, so add 2AH to highorder byte of result and shift 16-bit result right one
bit.
o
C
Step 5: Test multiplier 4-bit; it is 1, so add 2AH to highorder byte of result and shift 16-bit resu It right one
bit.
Step 6: Test multipl ier 5-bit; it is 1, so add 2 AH to highorder byte of result and sh ift 16-bit resu It right one
bit.
Register D holds the multiplicand, and register C originally holds the multiplier.
MULT:
For example:
MULTIPLICAND
00001010
MULT1: RAR
2- 1
MOV
JMP
2- 1 + (BITl MCND 2 8 ))
MVI
MVI
MULTO: MOV
RAR
MOV
DCR
JZ
MOV
JNC
ADD
MULTIPLIER
00000101
(BITO' MCND 2 8 )
DONE:
2- 1
54
DIV:
DIVa:
DIV1:
DIV2:
MVI
MOV
MOV
MOV
MOV
DCR
JZ
MOV
RAL
JNC
SUB
JMP
SUB
JNC
ADD
JMP
RAL
MOV
MVI
XRA
MOV
MOV
RAR
E,9
A,B
B,A
A,C
The result will be stored from low-order byte to highorder byte beginning at memory location FIRST, replacing
the original contents of these locations.
; Bit counter
C,A
E
DIV2
A,B
Memory
Location before
DIVl
D
DIVa
D
; Subtract divisor. If
; less than high-order
; quotient, loop.
; Otherwise, add it back
DiVa
D
DIVa
E,A
A,OFFH
C
C,A
A,E
lA
) carry
-+~
6A
) carry
FIRST+l
AF
FIRST+2
32
SECND
90
SECND+l
BA
BA
SECND+2
84
84
+..::.+ B7
...
90
Label
Code
MADD:
LXI
LXI
XRA
LDAX
ADC
LOOP:
32AF8A
+ 84BA90
B76A1A
This addition may be performed on the 8080 by adding the two low-order bytes of the numbers, then adding
the resulting carry to the two next-higher-order bytes, and
so on:
32
84
AF
BA
B7
6A
8A
The carry bit and the ADC (add with carry) instructions may be used to add unsigned data quantities of arbitrary length. Consider the following addition of two threebyte unsigned hexadecimal numbers:
carry = 1
-++
FIRST
DONE:
'-~
after
Comment
DONE:
FiRST:
DB
DB
DB
SECND: DB
DB
DB
8A
90
lA
ca"y
Operand
90H
OBAH
84H
8AH
OAFH
32H
The following routine will perform this multibyte addition, making these assumptions:
55
Rev. 8
The carry (or borrow) bit and the SBB (subtract with
borrow) instruction may be used to subtract unsigned data
quantities of arbitrary length. Consider the following subtraction of two two-byte unsigned hexadecimal numbers:
1301
- 0503
ODFE
Carry = 0 /
00000001 = 01 H
11.111101 = -(03H+carry)
11111110= OF EH, the low-order result
carry out = 0, setting the Carry bit = 1, indicating a borrow
High-order subtraction:
00010011 = 13H
11111010= -(05H+carry)
00001101
carry out = 1, resetting the Carry bit indicating no borrow
"carry bit = 1
DeCIMAL ADDITION
"-
Carry = 0 /
_---.J!11QB
a 01111001B
'"\
carry bit = 0
Since the leftmost 4 bits are <10 and the Carry bit is
reset, no further action occurs.
Thus, the correct decimal result 7921 is generated in
two bytes.
A routine which adds decimal numbers, then, is exactly analogous to the multibyte addition routine MADD of the
last section, and may be produced by inserting the instruction DAA after the ADC M instruction of that example.
56
Rev. B
Accumulator = 10011001 B
o = OOOOOOOOB
Carry
1
10011010B = 9AH
(5)
The process consists of generating the hundred's complement of the subtrahend digit (the difference between the
subtrahend digit and 100 decimal), and adding the result to
the minuend digit. For instance, to subtract 340 from 560,
the hundred's complement of 340 (1000-340=660) is
added to 560, producing 1220, which when truncated to 8
bits gives 220, the correct result. If a borrow was generated
by the previous subtraction, the 99's complement of the
subtrahend digit is produced to compensate for the borrow.
:a
Carry = 0
/71
Auxiliary Carry = 1
(6)
(7)
(8)
(9)
(2)
(3)
(4)
(5)
(6)
Accumulator = 10011001B
13H = 11101101B
IJ 1000011 DB
(10)
Accumulator = 1000011 DB
43H = 01000011B
OJ 11001 001 B = C9H
Carry = 0 /
Auxiliary Carry = 0
Otherwise, stop.
(11) OAA converts accumulator to 29H and sets the carry
bit = 1, indicating no borrow occurred.
Example:
The following subroutine will subtract one 16digit decimal number from another using the following
assumptions:
The minuend is stored least significant (2) digits first
beginning at location MINU.
{1)
Set ca rry = 1.
(2)
(3)
51
Label
Code
Operand
DSUB:
LXI
LXI
MVI
STC
LOOP:
MVI
ACI
SUB
XCHG
ADD
DAA
MOV
XCHG
DCR
JZ
INX
INX
JMP
DONE: NOP
Comment
Label
Code
Operand
FIRST
SET
OFFH
SBMAC
MACRO
FIRST
CALL
SUBR
IF
SET
JMP
FIRST
0
OUT
SUBR::
OUT:
RET
NOP
ENDIF
ENDM
FIRS-T
CALL
SUBA
IF
SET
JMP
FIRST
OUT
SUBR:
RET
OUT:
NOP
Since FIRST is non-zero when encountered during
this expansion, the statements between the IF and END IF
are assembled into the program. The first statement thus
assembled sets the value of FI RST to 0, while the remaining
statements are the necessary subrouti ne SUB R and a jump
around the subroutine. When this portion of the program is
executed, the subroutine SUB R will be called, but program
execution will not flow into the subroutine's definition.
On any subsequent reference to SBMAC i:l the program, however, the following expansion will be produced:
Label
Code
Operand
SBMAC
CALL
SUBR
IF
FIRST
Since FIRST is now equal to zero, the IF ~tatement
ends the macro expansion and does not calise the subroutine
to be generated again. The label SUBR !~ k'lOwn during this
expansion because it was defined globally (followed by two
colons in the definition).
58
The interrupting device supplies, via hardware, one instruction which the CPU executes. This instruction
does not appear anywhere in memory, and the programmer has no control over it, since it is a function
of the interrupting device's controller design. The
program counter is not incremented before this
instruction.
The instruction supplied by the interrupting device is
normally an RST instruction (see Chapter 2), since this is an
efficient one byte call to one of 8 eight-byte subroutines located in the first 64 words of memory. For instance, the
teletype may supply the instruction:
(a)
(2)
(3)
(1)
RST OH
INTERRUPT
Normal
Program
Execution
-----f----------=--=------,--+
Transfers
Device "a"
control to
Supplies RST OH
Interrupt Service
Routine
-......./
) 0000
0007
Device "b"
Supplies RST 1H
Transfers
control to
) 0008
oooF
59
I
I
Subroutine for
device "a"
Subroutine for
device "b"
Device "x"
Transfers
control to
Supplies RST 7H
JC LOC
and the carry bit equals 1. If the interrupt subroutine happens to zero the carry bit just before returning to the interrupted program, the jump to LOC which should have occurred will not, causing the interrupted program to produce
erroneous results.
ARBITRARY
MEMORY ADDRESS
3COB
3COC
INSTRUCTION
MOV
MOV
C,B
+----------1'
E,A~
Device 1 supplies
RST OH
Program Counter =
3COC pushed onto
the stack.
0000
I
B
Control transferred
to 0000
Instruction 1
Instruction 2
RET
t
Stack popped into
program counter
Like any other subroutine then, any interrupt subroutine should save at least the condition bits and restore them
before performing a RETURN operation. (The obvious and
most convenient way to do this is to save the data in the
stack, using PUSH and POP operations.)
60
'--~
Code
Operand
PUSH
PSW
EI
Comment
-----
POP
RET
PSW
61
This appendix provides a summary of 8080 assembly language instructions. Abbreviations used are as follows:
'--"""
ADDR
Aux. carry
Carry
CODE
An operation code
DATA
DATA16
DST
EXP
INTE
lABEL:
A memory byte
Parity
PC
Program Counter
PCH
PCl
REGM
vi
RP
RP1
RP2
Sign
SP
SRC
Zero
XY
CODE
DESCRIPTION
STC
(Carry) +-1
Set carry
CMC
(Carry) +-(Carry)
Complement carry
INR
-orDCR
-orCMA
-orDAA
REGM
REGM
vii
CODE
DESCRIPTION
INR
(REGM) +- (REGM)+l
DCR
(REGM) +- (REGM)-l
CMA
(A)
DAA
If (A o-A 3 )
+-
+-
(A)
(1\)
Complement accumulator
> 9 or(Aux.Carry)=l,
Convert accumulator
(A)+6
contents to form
Then if (A 4 -A 7 )
> 9 or (Carry)=
(A) = (A) + 6 2
two decimal
digits
INR,DCR
CMA
DAA
NOP INSTRUCTION
Format:
[LABEL:]
NOP
,-------I
CODE
DESCRIPTION
NOP
- - - - - - - No operation
MOV
-orCODE
[LABEL:]
DST,SRC
RP
DESCRIPTION
MOV
(DST)
+-
(SRC)
STAX
((RP))
+-
(A)
LDAX
(A)
+-
((RP))
viii
CODE
REGM
CODE
DESCRIPTION
ADD
(A)
+-
(A)+(REGM)
ADC
(A)
+-
(A)+(R EGM)+(Carry)
SUB
(A)
+-
(AHREGM)
SBB
(A)
+-
(A)-( REGM)-(Carry)
ANA
(A)
+-
XRA
(A)
+-
ORA
(A)
+-
(A) OR (REGM)
CMP
CODE
CODE
DESCRIPTION
RLC
(Carry) +- A 7 , A n+ 1, +- An' A o +- A 7
RRC
(Carry) +- A o, An +- A n+ 1 , A 7 +- A o
RAL
RAR
An +- A n+ 1 , (Carry) +- A o , A 7
+-
ix
Rev. B
CODE1
-orCODE2
[LABEL:)
RP
I
CODE1
DESCRIPTION
PUSH
(SP) +- (SP)-2
(SP) +- (SP)+2
DAD
INX
(RP) +-(RP)+1
Increment RP by 1
DCX
(RP) +- (RP)-1
Decrement RP by 1
CODE2
DESCRIPTION
XCHG
(H)
(D), (L)
XTHL
(L)
((SP)). (H)
SPHL
(SP) +- (H):(L)
POP
(E)
((SP)+1)
IMMEDIATE INSTRUCTIONS
Format:
[LABEL:)
[LABEL:)
RP,DATA16
LXI
-orMVI
REGM, DATA
-ar[LABEL:)
REGM
CODE
CODE
DESCRIPTION
LXI
(RP) +-DATA 16
MVI
(REGM) +-DATA
ADI
ACI
SUI
SBt
ANI
XRI
ORI
CPt
Format:
[LABEL:]
CODE
ADDR
CODE
DESCRIPTION
STA
(ADDR) +- (A)
LOA
(A) +- (ADDR)
SHLD
LHLD
JUMP INSTRUCTIONS
Format:
[LABEL:]
[LABEL:]
PCHL
-orCODE
ADDR
xi
Rev. 8
CODE
DESCRIPTION
PCHL
(PC) +-(HL)
JMP
(PC) +-ADDR
JC
If (Carry)
If (Carry)
= 1, (PC) +- ADDR
If (Carry)
If (Carry)
= 0, (PC) +- ADDR
= 1, (PC) +- (PC)+3
If (Zero)
If (Zero)
= 0, (PC) +- (PC)+3
If (Zero)
=
=
0, (PC) +- ADDR
1, (PC) +- (PC)+3
If (Zero)
If (Zero)
=
=
0, (PC) +- ADDR
1, (PC) +- (PC)+3
If (Sign)
If (Sign)
1, (PC) +- ADDR
= 0, (PC) +- (PC)+3
If (Parity)
If (Parity)
0, (PC) +- (PC)+3
If (Parity)
If (Parity)
0, (PCI +- ADDR
= 1, (PC) +- (PC)+3
JNC
JZ
JNZ
JP
JM
JPE
JPO
0, (PC) +- (PC)+3
If (Zero)
1, (PC) +- ADDR
= 1, (PC) +- ADDR
Jump to ADDR if parity even
CALL INSTRUCTIONS
Format:
CODE
[LABEL: ]
CODE
DESCRIPTION
ADDR
CALL
CC
If (Carry)
If (Carry)
CNC
If (Carry)
If (Carry)
= 1,
= 0,
= 0,
= 1, (PC) +- (PC)+3
CZ
If (Zero)
If (Zero)
= 1,
= 0,
CNZ
If (Zero)
If (Zero)
CP
If (Sign)
If (Sign)
= 1, (PC) +- (PC)+3
CM
CPE
= 0,
= 0, (PCl +- (PC)+3
Call subroutine if Parity even
If (Parity) = 0, ((SP)-1) +-(PCH), ((SPI-2) +-(PCL), (SP) +-(SP)+2, (PC) +-ADDR
Call subroutine if Parity odd
If (Parity) = 1, (PC) +- (PC)+3
If (Parity)
CPO
xii
RETURN INSTRUCTIONS
Format:
[lABEL:]
CODE
CODE
DESCRIPTION
RET
RC
RNC
RZ
RNZ
RM
RP
RPE
RPO
RST INSTRUCTION
Format:
[lABEL:]
NOTE: OooB
EXP
RST
EXP
111B
CODE
DESCRIPTION
RST
CODE
CODE
DESCRIPTION
EI
(INTE) +-1
DI
(lNTE) +-0
xiii
Rev. B
INPUT/OUTPUT INSTRUCTIONS
Format:
[LABEL:]
EXP
CODE
CODE
DESCRIPTION
IN
OUT
HLT INSTRUCTION
Format:
[LABEL:]
HLT
CODE
DESCRIPTION
HLT
-------------
PSEUDO - INSTRUCTIONS
ORG PSEUDO - INSTRUCTION
Format:
ORG
EXP
CODE
DESCRIPTION
ORG
EQU
CODE
DESCRIPTION
EQU
NAME +- EXP
EXP
EXP
SET
CODE
DESCRIPTION
SET
NAME +- EXP
--
xiv
DESCRIPTION
END
IF
-andENDIF
CODE
DESCRIPTION
IF
ENDIF
MACRO
LIST
-andENDM
CODE
DESCRIPTION
MACRO
ENDM
xv
This appendix summarizes the bit patterns and number of time states associated with every 8080 CPU instruction.
When using this summary, note the following symbology:
1)
DDD represents a destination register. SSS represents a source register. Both DDD and SSS are interpreted as follows:
Interpretation
DDD or SSS
Register B
Register C
Register D
Register E
Register H
Register L
A memory register
The accumulator
000
001
010
011
100
101
110
111
2)
Instruction execution time equals number of time periods multiplied by the duration of a time period.
A time period may vary from 480 nanosecs to 2 jJ.sec.
Where two numbers of time periods are shown (eq. 5/11), it means that the smaller number of time periods will be
required if a condition is not met, and the larger number of time periods will be required if the condition is met.
MNEMONIC
CALL
CC
CNC
CZ
CNZ
CP
CM
CPE
CPO
RET
RC
RNC
RZ
RNZ
RP
RM
RPE
RPO
D7
D6
Ds
D4
D3
D2
D1
Do
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
xvi
MNEMONIC
D7
RST
IN
OUT
LXI B
LXID
LXIH
LXISP
PUSH B
PUSH D
PUSH H
PUSH PSW
POP B
POP D
POP H
POP PSW
STA
LDA
XCHG
XTHL
SPHL
PCHL
DAD B
DAD D
DAD H
DAD SP
STAX B
STAX D
LDAX B
LDAX D
INX B
INXD
INX H
INX SP
MOVrl,r2
MOV M, r
MOV r, M
HLT
MVI r
MVI M
INR
DCR
INR A
DCR A
INR M
DCR M
ADDr
ADCr
SUB r
SBB r
AND r
XRAr
ORAr
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
eMP,
ADD M
i~
1
0
ADC M
_ _ _ _ _ _ _ _ _ L-_
D6
Ds
D4
D3
D2
D1
Do
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
D
1
D
1
D
1
D
D
1
1
1
1
0
0
0
0
1
1
1
1
0
0
A
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
D
1
D
1
D
1
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
A
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
D
0
D
0
D
0
D
D
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S
S
1
1
1
1
0
0
0
0
0
0
S
S
S
S
S
S
S
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
S
S
0
0
0
0
0
1
0
1
0
1
S
S
S
S
S
S
S
S
0
0
S
S
1
1
1
1
1
1
1
1
1
1
S
S
S
S
S
S
S
S
1
1
xvii
4
18
5
5
10
10
10
10
7
7
7
7
5
5
5
5
5
7
7
7
7
10
5
5
5
5
10
10
4
4
4
4
4
4
4
4
7
7
Rev. B
MNEMONIC
07
06
05
04
03
O2
01
SUB M
SBB M
ANOM
XRAM
ORAM
CMPM
AOI
ACI
SUI
SBI
ANI
XRI
ORI
CPI
RlC
RRC
RAl
RAR
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
OCXB
OCXO
DCXH
OCXSP
CMA
STC
CMC
DAA
SHlO
lHlO
EI
DI
NOP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
xviii
7
7
7
7
7
7
7
7
7
7
7
7
7
7
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
4
4
4
4
10
10
10
10
10
10
10
10
10
5
5
5
5
4
4
4
4
16
16
4
4
4
The 8080 uses a seven-bit ASCII code, which is the normal 8 bit ASCII code with the parity (high-order) bit always
reset.
GRAPHIC OR CONTROL
ASCII (HEXADECIMAL)
NULL
SOM
EOA
EOM
EOT
WRU
RU
8ELL
FE
H. Tab
Line Feed
V. Tab
Form
Return
00
01
02
03
04
05
06
07
SO
SI
OCO
X-On
Tape Aux. On
X-Off
Tape Aux. Off
Error
Sync
LEM
SO
S1
S2
S3
S4
S5
S6
57
GRAPHIC OR CONTROL
ACK
Alt. Mode
Rubout
!
,.,.
$
%
&
08
09
OA
08
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C
<
>
?
[
\
]
t
+--
10
1E
1F
blank
0
xx
ASCII (HEXADECIMAL)
7C
70
7F
21
22
23
24
25
26
27
28
29
2A
28
2C
20
2E
2F
3A
38
3C
3D
3E
3F
58
5C
50
5E
5F
40
20
30
GRAPHIC OR CONTROL
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
P
Q
R
S
T
U
V
W
X
y
ASCII (HEXADECIMAL)
31
32
33
34
35
36
37
38
39
41
42
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
I
I
I
~
xxi
xxii
POWERS OF TWO
2
2
4
8
16
32
64
128
-n
1.0
1 0.5
2 0.25
3 0.125
4
5
6
7
0.062
0.031
0.015
0.007
256 8 0.003
512 9 0.001
1 024 10 0.000
2 048 11 0.000
906
953
976
488
25
125
562 5
281 25
4
8
16
32
096
192
384
768
12
13
14
15
0.000
0.000
0.000
0.000
244
122
061
030
140
070
035
517
625
312 5
156 25
578 125
65
131
262
524
536
072
144
288
16
17
18
19
0.000
0.000
0.000
0.000
015
007
003
001
258
629
814
907
789
394
697
348
062
531
265
632
5
25
625
812 5
1
2
4
8
048
097
194
388
576
152
304
608
20
21
22
23
0.000
0.000
0.000
0.000
000
000
000
000
953
476
238
119
674
837
418
209
316
158
579
289
406
203
101
550
25
125
562 5
781 25
16
33
67
134
777
554
108
217
435
870
741
483
216
432
864
728
456
912
824
648
24
25
26
27
28
29
30
31
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
059
029
014
007
003
001
000
000
604
802
901
450
725
862
931
465
644
322
161
580
290
645
322
661
775
387
193
596
298
149
574
287
390
695
847
923
461
230
615
307
625
312
656
828
914
957
478
739
5
25
125
062
031
515
257
5
25
625
812 5
268
536
1 073
2 147
1
2
4
9
5
25
625
812 5
---
4
8
17
34
294
589
179
359
967
934
869
738
296
592
184
368
32
33
34
35
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
232
116
058
029
830
415
207
103
643
321
660
830
653
826
913
456
869
934
467
733
628
814
407
703
906
453
226
613
25
125
562 5
281 25
68
137
274
549
719
438
877
755
476
953
906
813
736
472
944
888
36
37
38
39
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
014
007
003
001
551
275
637
818
915
957
978
989
228
614
807
403
366
183
091
545
851
425
712
856
806
903
951
475
640
320
660
830
625
312 5
156 25
078 125
1
2
4
8
099
199
398
796
511
023
046
093
627
255
511
022
776 40
55241
104 42
208 43
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
909
454
227
113
494
747
373
686
701
350
675
837
772
886
443
721
928
464
232
616
237
118
059
029
915
957
478
739
039
519
759
379
062
531
765
882
5
25
625
812 5
17
35
70
140
592
184
368
737
186
372
744
488
044
088
177
355
416
832
664
328
44
45
46
47
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
056
028
014
007
843
421
210
105
418
709
854
427
860
430
715
357
808
404
202
601
014
007
003
001
869
434
717
858
689
844
422
711
941
970
485
242
406
703
351
675
25
125
562 5
781 25
281
562
1 125
2 251
474
949
899
799
976
953
906
813
710
421
842
685
656
312
624
248
48
49
50
51
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
003
001
000
000
552
776
888
444
713
356
178
089
678
839
419
209
800
400
700
850
500
250
125
062
929
464
232
616
355
677
338
169
621
810
905
452
337
668
334
667
890
945
472
236
625
312 5
656 25
328 125
4
9
18
36
503
007
014
028
599
199
398
797
627
254
509
018
370
740
481
963
496
992
984
968
52
53
54
55
0.000
0.000
0.000
0000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
222
111
055
027
044
022
511
755
604
302
151
575
925
462
231
615
031
515
257
628
308
654
827
913
084
042
021
510
726
363
181
590
333
166
583
791
618
809
404
702
164
082
541
270
062
031
015
507
5
25
625
812 5
72
144
288
576
057
115
230
460
594
188
376
752
037
075
151
303
927
855
711
423
936
872
744
488
56
57
58
59
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
013
006
003
001
877
938
469
734
787
893
446
723
807
903
951
475
814
907
953
976
456
228
614
807
755
377
188
094
295
647
823
411
395
697
848
924
851
925
962
481
135
567
783
391
253
676
813
906
906
950
476
738
25
125
562 5
281 25
152
305
611
223
921
843
686
372
504
009
018
036
606
213
427
854
846
693
387
775
976
952
904
808
60
61
62
63
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
867
433
216
108
361
680
840
420
737
868
434
217
988
994
497
248
403
201
100
550
547
773
886
443
205
602
801
400
962
981
490
745
240
120
560
280
695
347
173
086
953
976
988
994
369
684
342
171
140
570
285
142
xxiii
625
312 5
156 25
578 125
1
17
281
4 503
72 057
152 921
4
68
099
592
474
599
594
504
1
16
268
294
719
511
186
976
627
037
606
4
65
048
777
435
967
476
627
044
710
370
927
846
1
16
256
096
536
576
216
456
296
736
776
416
656
496
936
976
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0.10000
0.62500
0.39062
0.24414
0.15258
0.95367
0.59604
0.37252
0.23283
0.14551
0.90949
0.56843
0.35527
0.22204
0.13877
0.86736
00000 00000
00000 00000
50000 00000
06250 00000
78906 25000
43164 06250
64477 53906
90298 46191
06436 53869
91522 83668
47017 72928
41886 08080
13678 80050
46049 25031
78780 78144
17379 88403
00000
00000
00000
00000
00000
00000
25000
40625
62891
51807
23792
14870
09294
30808
56755
54721
x 10
X
X
X
x
x
x
x
x
x
x
x
x
x
x
x
TABLE OF POWERS OF 10 16
10
3
23
163
OEO
8AC7
2
17
E8
918
5AF3
807E
8652
4578
B683
2304
1
F
98
5F5
389A
5408
4876
04A5
4E72
107A
MC6
6FC1
508A
A764
89E8
1
A
64
3E8
2710
86AO
4240
9680
E100
CAOO
E400
E800
1000
AOOO
4000
8000
0000
0000
0000
0000
10- n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1.0000
0.1999
0.28F5
0.4189
0.6808
0.A7C5
0.10C6
0.1 A07
0.2AF3
0.44B8
0.60F3
0.AFE8
0.1197
0.1 C25
0.2009
0.480E
0.734A
0.B877
0.1272
0.1083
xxiv
0000
9999
C28F
3748
8BAC
AC47
F7AO
F29A
lOC4
2FAO
7F67
FFOB
9981
C268
3700
BE7B
CA5F
AA32
5001
C94F
0000
9999
5C28
C6A7
710C
1B47
85EO
BCAF
6118
9B5A
SEF6
CB24
20EA
4976
4257
9058
6226
36M
0243
8602
0000
999A
F5C3
EF9E
8296
8423
8037
4858
73BF
52CC
EAOF
AAFF
1119
81C2
3604
5660
FOAE
B449
A8A1
AC35
x 16- 1
x 16- 2
x 16- 3
x 16-4
x 16-4
x 16 -5
x 16-6
x 16 -7
x 16-8
x
x
x
x
x
16-9
16-9
16 -10
16- 11
16 -12
x 16- 13
x 16- 14
x 16 -14
x 16- 15
10- 1
10- 2
10- 3
10-4
10-6
10-7
10-8
10-9
10- 10
10- 12
10- 13
10- 14
10- 15
10- 16
10- 18
Decimal
Hexadecimal
01000
02000
03000
04000
05000
06000
07000
08000
09 000
OAOOO
DB 000
DC 000
00000
OE 000
OF 000
10 000
11000
12000
13000
14000
15000
16000
17000
18000
19000
lA 000
1BODO
lC 000
10000
1E 000
1F 000
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
65536
69632
73728
77 824
81 920
86016
90112
94208
98304
102400
106496
110592
114688
118 784
122880
126976
20000
30000
40000
50000
60000
70000
80000
90000
AO 000
BO 000
CO 000
DO 000
EO 000
FO 000
100000
200000
300000
400000
500000
600000
700000
800000
900000
ADO 000
BOO 000
COO 000
000000
EOO 000
FOO 000
1 000000
2000000
Decimal
131 072
196608
262144
327680
393216
458752
524288
589824
655360
720896
786432
851 968
917504
983040
1 048576
2097 152
3 145728
4 194304
5242880
6291 456
7340032
8388608
9437 184
10485760
11 534336
12582912
13631 488
14680064
15728640
16777216
33554432
000
010
020
030
0000
0016
0032
0048
0001
0017
0033
0049
0002
0018
0034
0050
0003
0019
0035
0051
0004
0020
0036
0052
0005
0021
0037
0053
0006
0022
0038
0054
0007
0023
0039
0055
0008
0024
0040
0056
0009
0025
0041
0057
0010
0026
0042
0058
0011
0027
0043
0059
0012
0028
0044
0060
0013
0029
0045
0061
0014
0030
0046
0062
0015
0031
0047
0063
040
050
060
070
0064
0080
0096
0112
0065
0081
0097
0113
0066
0082
0098
0114
0067
0083
0099
0115
0068
0084
0100
0116
0069
0085
0101
0117
0070
0086
0102
0118
0071
0087
0103
0119
0072
0088
0104
0120
0073
0089
0105
0121
0074
0090
0106
0122
0075
0091
0107
0123
0076
0092
0108
0124
0077
0093
0109
0125
0078
0094
0110
0126
0079
0095
0111
0127
080
090
OAO
OBO
0128
0144
0160
0176
0129
0145
0161
0177
0130
0146
0162
0178
0131
0147
0163
0179
0132
0148
0164
0180
0133
0149
0165
0181
0134
0150
0166
0182
0135
0151
0167
0183
0136
0152
0168
0184
0137
0153
0169
0185
0138
0154
0170
0186
0139
0155
0171
0187
0140
0156
0172
0188
0141
0157
0173
0189
0142
0158
0174
0190
0143
0159
0175
0191
OCO
000
OEO
OFO
0192
0208
0224
0240
0193
0209
0225
0241
0194
0210
0226
0242
0195
0211
0227
0243
0196
0212
0228
0244
0197
0213
0229
0245
0198
0214
0230
0246
0199
0215
0231
0247
0200
0216
0232
0248
0201
0217
0233
0249
0202
0218
0234
0250
0203
0219
0235
0251
0204
0220
0236
0252
0205
0221
0237
0253
0206
0222
0238
0254
0207
0223
0239
0255
xxv
1
0257
0273
0289
0305
2
0258
0274
0290
0306
3
0259
0275
0291
0307
4
0260
0276
0292
0308
5
0261
0277
0293
0309
6
0262
0278
0294
0310
7
0263
0279
0295
0311
8
0264
0280
0296
0312
9
0265
0281
0297
0313
A
0266
0282
0298
0314
100
110
120
130
0
0256
0272
0288
0304
0267
0283
0299
0315
0268
0284
0300
0316
0269
0285
0301
0317
0270
0286
0302
0318
0271
0287
0303
0319
140
150
160
170
0320
0336
0352
0368
0321
0337
0353
0369
0322
0338
0354
0370
0323
0339
0355
0371
0324
0340
0356
0372
0325
0341
0357
0373
0326
0342
0358
0374
0327
0343
0359
0375
0328
0344
0360
0376
0329
0345
0361
0377
0330
0346
0362
0378
0331
0347
0363
0379
0331
0348
0364
0380
0333
0349
0365
0381
0334
0350
0366
0382
0335
0351
0367
0383
180
190
1AO
1BO
0384
0400
0416
0432
0385
0401
0417
0433
0386
0402
0418
0434
0387
0403
0419
0435
0388
0404
0420
0436
0389
0405
0421
0437
0390
0406
0422
0438
0391
0407
0423
0439
0392
0408
0424
0440
0393
0409
0425
0441
0394
0410
0426
0442
0395
0411
0427
0443
0396
0412
0428
0444
0397
0429
0445
0398 0399
(\11111
0415
0430 0431
0446 0447
1CO
100
1EO
1FO
0448
0464
0480
0496
0449
0465
0481
0497
0450
0466
0482
0498
0451
0467
0483
0499
0452
0468
0484
0500
0453
0469
0485
0501
0454
0470
0486
0502
0455
0471
0487
0503
0456
0472
0488
0504
0457
0473
0489
0505
0458
0474
0490
0506
0459
0475
0491
0507
0460
0476
0492
0508
0461
0477
0493
0509
0462
0478
0494
0510
0463
0479
0495
0511
200
210
220
230
0512
0528
0544
0560
0513
0529
0545
0561
0514
0530
0546
0562
0515
0531
0547
0563
0516
0532
0548
0564
0517
0533
0549
0565
0518
0534
0550
0566
0519
0535
0551
0567
0520
0536
0552
0568
0521
0537
0553
0569
0522
0538
0554
0570
0523
0539
0555
0571
0524
0540
0556
0572
0525
0541
0557
0573
0526
0542
0558
0574
0527
0543
0559
0575
240
250
260
270
0576
0592
0608
0624
0577
0593
0609
0625
0578
0594
0610
0626
0579
0595
0611
0627
0580
0596
0612
0628
0581
0597
0613
0629
0582
0598
0614
0630
0583
0599
0615
0631
0584
0600
0616
0632
0585
0601
0617
0633
0586
0602
0618
0634
0587
0603
0619
0635
0588
0604
0620
0636
0589
0605
0621
0637
0590
0606
0622
0638
0591
0607
0623
0639
280
290
2AO
2BO
0640
0656
0672
0688
0641
0657
0673
0689
0642
0658
0674
0690
0643
0659
0675
0691
0644
0660
0676
0692
0645
0661
0677
0693
0646
0662
0678
0694
0647
0663
0679
0695
0648
0664
0680
0696
0649
0665
0681
0697
0650
0666
0682
0698
0651
0667
0683
0699
0652
0668
0684
0700
0653
0669
0685
0701
0654
0670
0686
0702
0655
0671
0687
0703
2CO
200
2EO
2FO
0704
0720
0736
0752
0705
0721
0737
0753
0706
0722
0738
0754
0707
0723
0739
0755
0708
0724
0740
0756
0709
0725
0741
0757
0710
0726
0742
0758
0711
0727
0743
0759
0712
0728
0744
0760
0713
0729
0745
0761
0714
0730
0746
0762
0715
0731
0747
0763
0716
0732
0748
0764
0717
0733
0749
0765
0718
0734
0750
0766
0719
0735
0751
0767
300
310
320
330
0768
0784
0800
0816
0769
0785
0301
0817
0770
0786
0802
0818
0771
0787
0803
0819
0772
0788
0804
0820
0773
0789
0805
0821
0774
0790
0806
0822
0775
0791
0807
0823
0776
0792
0808
0824
0777
0793
0809
0825
0778
0794
0810
0826
0779
0795
0811
0827
0780
0796
0812
0828
0781
0797
0813
0829
0782
0798
0814
0830
0783
0799
0815
0831,
340
350
360
370
0832
0848
0864
0880
0833
0849
0865
0881
0834
0850
0866
0882
0835
0851
0867
0883
0836
0852
0868
0884
0837
0853
0869
0885
0838
0854
0870
0886
0839
0855
0871
0887
0840
0856
0872
0888
0841
0857
0873
0889
0842
0858
0874
0890
0843
0859
0875
0891
0844
0860
0876
0892
0845
0861
0877
0893
0846
0862
0878
0894
0847
0863
0879
0895
380
390
3AO
3BO
0896
0212
0928
0944
0897
0913
0929
0945
0898
0914
0930
0946
0899
0915
0931
0947
0900
0916
0932
0948
0901
0917
0933
0949
0902
0918
0934
0950
0903
0919
0935
0951
0904
0920
0936
0952
0905
0921
0937
0953
0906
0922
0938
0954
0907
0923
0939
0955
0908
0924
0940
0956
0909
0925
0941
0957
0910
0926
0942
0958
0911
0927
0943
0959
3CO
300
3EO
3FO
0960
0976
0992
1008
0961
0977
0993
1009
0962
0978
0994
1010
0963
0979
0995
1011
0964
0980
0996
1012
0965
0981
0997
1013
0966
0982
0998
1014
0967
0983
0999
1015
0968
0984
1000
1016
0969
0985
1001
1017
0970
0986
1002
1018
0971
0987
1003
1019
0972
0988
1004
1020
0973
0989
1005
1021
0974
0990
1006
1022
0975
0991
1007
1023
xxvi
0413
U"'TI""
1
1025
1041
1057
1073
2
1026
1042
1058
1074
3
1027
1043
1059
1075
4
1028
1044
1060
1076
5
1029
1045
1061
1077
6
1030
1046
1062
1078
7
1031
1047
1063
1079
8
1032
1048
1064
1080
9
1033
1049
1065
1081
A
1034
1050
1066
1082
8
1035
1051
1067
1083
C
1036
1052
1068
1084
0
1037
1053
1069
1085
400
410
420
430
0
1024
1040
1056
1072
1038
1054
1070
1086
1039
1055
1071
1087
440
450
460
470
1088
1104
1120
1136
1089
1105
1121
1137
1090
1106
1122
1138
1091
1107
1123
1139
1092
1108
1124
1140
1093
1109
1125
1141
1094
1110
1126
1142
1095
1111
1127
1143
1096
1112
1128
1144
1097
1113
1129
1145
1098
1114
1130
1146
1099
1115
1131
1147
1100
1116
1132
1148
1101
1117
1133
1149
1102
1118
1134
1150
1103
1119
1135
1151
480
490
4AO
480
1152
1168
1184
1200
1153
1169
1185
1201
1154
1170
1186
1202
1155
1171
1187
1203
1156
1172
1188
1204
1157
1173
1189
1205
1158
1174
1190
1206
1159
1175
1191
1207
1160
1176
1192
1208
1161
1177
1193
1209
1162
1178
1194
1210
1163
1179
1195
1211
1164
1180
1196
1212
1165
1181
1197
1213
1166
1182
1198
1214
1167
1183
1199
1215
4CO
400
4EO
4FO
1216
1232
1248
1264
1217
1233
1249
1265
1218
1234
1250
1266
1219
1235
1251
1267
1220
1236
1252
1268
1221
1237
1253
1269
1222
1238
1254
1270
1223
1239
1255
1271
1224
1240
1256
1272
1225
1241
1257
1273
1226
1242
1258
1274
1227
1243
1259
1275
1228
1244
1260
1276
1229
1245
1261
1277
1230
1246
1262
1278
1231
1247
1263
1279
500
510
520
530
1280
1296
1312
1328
1281
1297
1313
1329
1282
1298
1314
1330
1283
1299
1315
1331
1284
1300
1316
1332
1285
1301
1317
1333
1286
1302
1318
1334
1287
1303
1319
1335
1288
1304
1320
1336
1289
1305
1321
1337
1290
1306
1322
1338
1291
1307
1323
1339
1292
1308
1324
1340
1293
1309
1325
1341
1294
1310
1326
1342
1295
1311
1327
1343
540
550
560
570
1344
1360
1376
1392
1345
1361
1377
1393
1346
1362
1378
1394
1347
1363
1379
1395
1348
1364
1380
1396
1349
1365
1381
1397
1350
1366
1382
1398
1351
1367
1383
1399
1352
1368
1384
1400
1353
1369
1385
1401
1354
1370
1386
1402
1355
1371
1387
1403
1356
1372
1388
1404
1357
1373
1389
1405
1358
1374
1390
1406
1359
1375
1391
1407
580
590
5AO
580
1408
1424
1440
1456
1409
1425
1441
1457
1410
1426
1442
1458
1411
1427
1443
1459
1412
1428
1444
1460
1413
1429
1445
1461
1414
1430
1446
1462
1415
1431
1447
1463
1416
1432
1448
1464
1417
1433
1449
1465
1418
1434
1450
1466
1419
1435
1451
1467
1420
1436
1452
1468
1421
1437
1453
1469
1422
1438
1454
1470
1423
1439
1455
1471
5CO
500
5EO
5FO
1472
1488
1504
1520
1473
1489
1505
1521
1474
1490
1506
1522
1475
1491
1507
1523
1476
1492
1508
1524
1477
1493
1509
1525
1478
1494
1510
1526
1479
1495
1511
1527
1480
1496
1512
1528
1481
1497
1513
1529
1482
1498
1514
1530
1483
1499
1515
1531
1484
1500
1516
1532
1485
1501
1517
1533
1486
1502
1518
1534
1487
1503
1519
1535
600
610
620
630
1536
1552
1568
1584
1537
1553
1569
1585
1538
1554
1570
1586
1539
1555
1571
1587
1540
1556
1572
1588
1541
1557
1573
1589
1542
1558
1574
1590
1543
1559
1575
1591
1544
1560
1576
1592
1545
1561
1577
1593
1546
1562
1578
1594
1547
1563
1579
1595
1548
1564
1580
1596
1549
1565
1581
1597
1550
1566
1582
1598
1551
1567
1583
1599
640
650
660
670
1600
1616
1632
1648
1601
1617
1633
1649
1602
1618
1634
1650
1603
1619
1635
1651
1604
1620
1636
1652
1605
1621
1637
1653
1606
1622
1638
1654
1607
1623
1639
1655
1608
1624
1640
1656
1609
1625
1641
1657
1610
1626
1642
1658
1611
1627
1643
1659
1612
1628
1644
1660
1613
1629
1645
1661
1614
1630
1646
1662
1615
1631
1647
1663
680
690
6AO
680
1664
1680
1696
1712
1665
1681
1697
1713
1666
1682
1698
1714
1667
1683
1699
1715
1668
1684
1700
1716
1669
1685
1701
1717
1670
1686
1702
1718
1671
1687
1703
1719
1672
1688
1704
1720
1673
1689
1705
1721
1674
1690
1706
1722
1675
1691
1707
1723
1676
1692
1708
1724
1677
1693
1709
1725
1678
1694
1710
1726
1679
1695
1711
1727
6CO
600
6EO
6FO
1728
1744
1760
1776
1729
1745
1761
1777
1730
1746
1762
1778
1731
1747
1763
1779
1732
1748
1764
1780
1733
1749
1765
1781
1734
1750
1766
1782
1735
1751
1767
1783
1736
1752
1768
1784
1737
1753
1769
1785
1738
1754
1770
1786
1739
1755
1771
1787
1740
1756
1772
1788
1741
1757
1773
1789
1742
1758
1774
1790
1743
1759
1775
1791
xxvii
Rev. B
700
710
720
730
1792
1808
1824
1840
1793
1809
1825
1841
1794
1810
1826
1842
1795
1811
1827
1843
740
750
760
770
1856
1872
1888
1904
1857
1873
1889
1905
1858
1874
1890
1906
780
790
7AO
780
1920
1936
1952
1968
1921
1937
1953
1969
7CO
700
7EO
7FO
1984
2000
2016
2032
800
810
820
830
6
1798
1814
1830
1846
7
1799
1815
1831
1847
8
1800
1816
1832
1848
9
1801
1817
1833
1849
A
1802
1818
1834
1850
8
1803
1819
1835
1851
C
1804
1820
1836
1852
1796
1812
1828
1844
5
1797
1813
1829
1845
1805
1821
1837
1853
1806
1822
1838
1854
1807
1823
1839
1855
1859
1875
1891
1907
1860
1876
1892
1908
1861
1877
1893
1909
1862
1878
1894
1910
1863
1879
1895
1911
1864
1880
1896
1912
1865
1881
1897
1913
1866
1882
1898
1914
1867
1883
1899
1915
1868
1884
1900
1916
1869
1885
1901
1917
1870
1886
1902
1918
1871
1887
1903
1919
1922
1938
1954
1970
1923
1939
1955
1971
1924
1940
1956
1972
1925
1941
1957
1973
1926
1942
1958
1974
1927
1943
1959
1975
1928
1944
1960
1976
1929
1945
1961
1977
1930
1946
1962
1978
1931
1947
1963
1979
1932
1948
1964
1980
1933
1949
1965
1981
1934
1950
1966
1982
1935
1951
1967
1983
1985
2001
2017
2033
1986
2002
2018
2034
1987
2003
2019
2035
1988
2004
2020
2036
1989
2005
2021
2037
1990
2006
2022
2038
1991
2007
2023
2039
1992
2008
2024
2040
1993
2009
2025
2041
1994
2010
2026
2042
1995
2011
2027
2043
1996
2012
2028
2044
1997
2013
2029
2045
1998
2014
2030
2046
1999
2015
2031
2047
2048
2064
2080
2096
2049
2065
2081
2097
2050
2066
2082
2098
2051
2067
2083
2099
2052
2068
2084
2100
2053
2069
2085
2101
2054
2070
2086
2102
2055
2071
2087
2103
2056
2072
2088
2104
2057
2073
2089
2105
2058
2074
2090
2106
2059
2075
2091
2107
2060
2076
2092
2108
2061
2077
2093
2109
2062
2078
2094
2110
2063
2079
2095
2111
840
850
860
870
2112
2128
2144
2160
2113
2129
2145
2161
2114
2130
2146
2162
2115
2131
2147
2163
2116
2132
2148
2164
2117
2133
2149
2165
2118
2134
2150
2166
2119
2135
2151
2167
2120
2136
2152
2168
2121
2137
2153
2169
2122
2138
2154
2170
2123
2139
2155
2171
2124
2140
2156
2172
2125
2141
2157
2173
2126
2142
2158
2174
2127
2143
2159
2175
880
890
8AO
880
2176
2192
2208
2224
2177
2193
2209
2225
2178
2194
2210
2226
2179
2195
2211
2227
2180
2196
2212
2228
2181
2197
2213
2229
2182
2198
2214
2230
2183
2199
2215
2231
2184
2200
2216
2232
2185
2201
2217
2233
2186
2202
2218
2234
2187
2203
2219
2235
2188
2204
2220
2236
2189
2205
2221
2237
2190
2206
2222
2238
2191
2207
2223
2239
8CO
800
8EO
8FO
2240
2256
2272
2288
2241
2257
2273
2289
2242
2258
2274
2290
2243
2259
2275
2291
2244
2260
2276
2292
2245
2261
2277
2293
2246
2262
2278
2294
2247
2263
2279
2295
2248
2264
2280
2296
2249
2265
2281
2297
2250
2266
2282
2298
2251
2267
2283
2299
2252
2268
2284
2300
2253
2269
2285
2301
2254
2270
2286
2302
2255
2271
2287
2303
900
910
920
930
2304
2320
2336
2352
2305
2321
2337
2353
2306
2322
2338
2354
2307
2323
2339
2355
2308
2324
2340
2356
2309
2325
2341
2357
2310
2326
2342
2358
2311
2327
2343
2359
2312
2328
2344
2360
2313
2329
2345
2361
2314
2330
2346
2362
2315
2331
2347
2363
2316
2332
2348
2364
2317
2333
2349
2365
2318
2334
2350
2366
2319
2335
2351
2367
940
950
960
970
2368
2384
2400
2416
2369
2385
2401
2417
2370
2386
2402
2418
2371
2387
2403
2419
2372
2388
2404
2420
2373
2389
2405
2421
2374
2390
2406
2422
2375
2391
2407
2423
2376
2392
2408
2424
2377
2393
2409
2425
2378
2394
2410
2426
2379
2395
2411
2427
2380
2396
2412
2428
2381
2397
2413
2429
2382
2398
2414
2430
2383
2399
2415
2431
980
990
9AO
980
2432
2448
2464
2480
2433
2449
2465
2481
2434
2450
2466
2482
2435
2451
2467
2483
2436
2452
2468
2484
2437
2453
2469
2485
2438
2454
2470
2486
2439
2455
2471
2487
2440
2456
2472
2488
2441
2457
2473
2489
2442
2458
2474
2490
2443
2459
2475
2491
2444
2460
2476
2492
2445
2461
2477
2493
2446
2462
2478
2494
2447
2463
2479
2495
9CO
900
9EO
9FO
2496
2512
2528
2544
2497
2513
2529
2545
2498
2514
2530
2546
2499
2515
2531
2547
2500
2516
2532
2548
2501
2517
2533
2549
2502
2518
2534
2550
2503
2519
2535
2551
2504
2520
2536
2552
2505
2521
2537
2553
2506
2522
2538
2554
2507
2523
2539
2555
2508
2524
2540
2556
2509
2525
2541
2557
2510
2526
2542
2558
2511
2527
2543
2559
xxviii
1
2561
2577
2593
2609
2
2562
2578
2594
2610
3
2563
2579
2595
2611
4
2564
2580
2596
2612
5
2565
2581
2597
2613
6
2566
2582
2598
2614
7
2567
2583
2599
2615
8
2568
2584
2600
2616
A
2569 2570
2585 2586
2601 2602
2617 2618
AOO
Al0
A20
A30
0
2560
2576
2592
2608
2571
2587
2603
2619
2572
2588
2604
2620
2573
2589
2605
2621
2574
2590
2606
2622
2575
2591
2607
2623
A40
A50
A60
A70
2624
2640
2656
2672
2625
2641
2657
2673
2626
2642
2658
2674
2627
2643
2659
2675
2628
2644
2660
2676
2629
2645
2661
2677
2630
2646
2662
2678
2631
2647
2663
2679
2632
2648
2664
2680
2633
2649
2665
2681
2634
2650
2666
2682
2635
2651
2667
2683
2636
2652
2668
2684
2637
2653
2669
2685
2638
2654
2670
2686
2639
2655
2671
2687
A80
A90
AAO
ABO
2688
2704
2720
2736
2689
2705
2721
2737
2690
2706
2722
2738
2691
2707
2723
2739
2692
2708
2724
2740
2693
2709
2725
2741
2694
2710
2726
2742
2695
2711
2727
2743
2696
2712
2728
2744
2697
2713
2729
2745
2698
2714
2730
2746
2699
2715
2731
2747
2700
2716
2732
2748
2701
2717
2733
2749
2702
2718
2734
2750
2703
2719
2735
2751
ACO
ADO
AEO
AFO
2752
2768
2784
2800
2753
2769
2785
2801
2754
2770
2786
2802
2755
2771
2787
2803
2756
2772
2788
2804
2757
2773
2789
2805
2758
2774
2790
2806
2759
2775
2791
2807
2760
2776
2792
2808
4761
2777
2793
2809
2762
2778
2794
2810
2763
2779
2795
2811
2764
2780
2796
2812
2765
2781
2797
2813
2766
2782
2798
2814
2767
2783
2799
2815
BOO
B10
B20
B30
2816
2832
2848
2864
2817
2833
2849
2865
2818
2834
2850
2866
2819
2835
3851
2867
2820
2836
2852
2868
2821
2837
2853
2869
2822
2838
2854
2870
2823
2839
2855
2871
2824
2840
2856
2872
2825
2841
2857
2873
2826
2842
2858
2874
2827
2843
2859
2875
2828
2844
2860
2876
2829
2845
2861
2877
2830
2846
2862
2878
2831
2847
2863
2879
B40
B50
B60
B70
2880
2896
2912
2928
2881
2897
2913
2929
2882
2898
2914
2930
2883
2899
2915
2931
2884
2900
2916
2932
2885
2901
2917
2933
2866
2902
2918
2934
2887
2903
2919
2935
2888
2904
2920
2936
2889
2905
2921
2937
2890
2906
2922
2938
2891
2907
2923
2939
2892
2908
2924
2940
2893
2909
2925
2941
2894
2910
2926
2942
2895
2911
2927
2943
B80
B90
BAO
BBO
2944
2960
2976
2992
2945
2961
2977
2993
2946
2962
2978
2994
2947
2963
2979
2995
2948
2964
2980
2996
2949
2965
2981
2997
2950
2966
2982
2998
2951
2967
2983
2999
2952
2968
2984
3000
2953
2969
2985
3001
2954
2970
2986
3002
2955
2971
2987
3003
2956
2972
2988
3004
2957
2973
2989
3005
2958
2974
2990
3006
2959
2975
2991
3007
BCO
BOO
BEO
BFO
3011
3027
3043
3059
3012
3028
3044
3060
3013
3029
3045
3061
3014
3030
3046
3062
3015
3031
3047
3063
3016
3032
3048
3064
3017
3033
3049
3065
3018
3034
3050
3066
3019
3035
3051
3067
3020
3036
3052
3068
3021
3037
3053
3069
3022
3038
3054
3070
3023
3039
3055
3071
COO
Cl0
C20
C30
3072
3088
3104
3120
3073
3089
3105
3121
3074
3090
3106
3122
3075
3091
3107
3123
3076
3092
3108
3124
3077
3093
3109
3125
3078
3094
3110
3126
3079
3095
3111
3127
3080
3096
3112
3128
3081
3097
3113
3129
3082
3098
3114
3130
3083
3099
3115
3131
3084
3100
3116
3132
3085
3101
3117
3133
3086
3102
3118
3134
3087
3103
3119
3135
C40
C50
C60
C70
3136
3152
3168
3184
3137
3153
3169
3185
3138
3154
3170
3186
3139
3155
3171
3187
3140
3156
3172
3188
3141
3157
3173
3189
3142
3158
3174
3190
3143
3159
3175
3191
3144
3160
3176
3192
3145
3161
3177
3193
3146
3162
3178
3194
3147
3163
3179
3195
3148
3164
3180
3196
3149
3165
3181
3197
3150
3166
3182
3198
3151
3167
3183
3199
C80
C90
CAO
CBO
3203
3219
3235
3251
3204
3220
3236
3252
3205
3221
3237
3253
3206
3222
3238
3254
3207
3223
3239
3255
3208
3224
3240
3256
3209
3225
3241
3257
3210
3226
3242
3258
3211
3227
3243
3259
3212
3228
3244
3260
3213
3229
3245
3261
3214
3230
3246
3262
3215
3231
3247
3263
CCO
CDO
CEO
CFO
3264
3280
3296
3312
3267
3283
3299
3315
3268
3284
3300
3316
3269
3285
3301
3317
3270
3286
3302
3318
3271
3287
3303
3319
3272
3288
3304
3320
3273
3289
3305
3321
3274
3290
3306
3322
3275
3291
3307
3323
3276
3292
3308
3324
3277
3293
3309
3325
3278
3294
3310
3326
3279
3295
3311
3327
3265
3281
3297
3313
3266
3282
3298
3314
xxix
Rev. B
,----"
--
3339
3355
3371
3387
3340
3356
3372
3388
3341
3357
3373
3389
3342
3358
3374
3390
3343
3359
3375
3391
3400 3401
3416 3417
3432 3433
3448 3449
3402 3403
3418 3419
3434 3435
3450 3451
3404
3420
3436
3452
3405
3421
3437
3453
3406
3422
3438
3454
3407
3423
3439
3455
3463
3479
3495
3511
3464
3480
3496
3512
3466
3482
3498
3514
3467
3483
3499
3515
3468
3484
3500
3516
3469
3485
3501
3517
3470
3486
3502
3518
3471
3487
3503
3519
3526
3542
3558
3574
3527
3543
3559
3575
3532
3548
3564
3580
3533
3549
3565
3581
3534
3550
3566
3582
3535
3551
3567
3583
3589
3605
3621
3637
3590
3606
3622
3638
3591
3607
3623
3639
3595
3611
3627
3643
3596
3612
3628
3644
3597
3613
3629
3645
3598
3614
3630
3646
3599
3615
3631
3647
3652
3668
3684
3700
3653
3669
3685
3701
3654
3670
3686
3702
3655
3671
3687
3703
3656
3672
3688
3704
3657
3673
3689
3705
3658
3674
3690
3706
3659
3675
3691
3707
3660
3676
3692
3708
3661
3677
3693
3709
3662
3678
3694
3710
3663
3679
3695
3711
3715
3731
3747
3763
3716
3732
3748
3764
3717
3733
3749
3765
3718
3734
3750
3766
3719
3735
3751
3767
3720 3721
3736 3737
3752 3753
3768 3769
3722
3738
3754
3770
3723
3739
3755
3771
3724
3740
3756
3772
3725
3741
3757
3773
3726
3742
3758
3774
3727
3743
3"159
3775
3779
3795
3811
3827
3780
3796
3812
3828
3781
3797
3813
3829
3782
3798
3814
3830
3783
3799
3815
3831
3784
3800
3816
3832
3785
3801
3817
3833
3786
3802
3818
3834
3787
3803
3819
3835
3788
3804
3820
3836
3789
3805
3821
3837
3790
3806
3822
3838
3791
3807
3823
3839
FOO
FlO
F20
F30
3844
3860
3876
3892
3845
3861
3877
3893
3846
3862
3878
3894
3847
3863
3879
3895
3848
3864
3880
3896
3849
3865
3881
3897
3850
3866
3882
3898
3851
3867
3883
3899
3852
3868
3884
3900
3853
3869
3885
3901
3854
3870
3886
3902
3855
3871
3887
3903
F40
F50
F60
F70
3907
3923
3939
3955
3908
3924
3940
3956
3909
3925
3941
3957
3910
3926
3942
3958
3911
3927
3943
3959
3912
3928
3944
3960
3913
3929
3945
3961
3914
3930
3946
3962
3915
3931
3947
3963
3916
3932
3948
3964
3917
3933
3949
3965
3918
3934
3950
3966
3919
3935
3951
3967
F80
F90
FAO
FBO
3968
3984
4000
4016
3969
3985
4001
4017
3970
3986
4002
4018
3971
3987
4003
4019
3972
3988
4004
4020
3973
3989
4005
4021
3974
3990
4006
4022
3975
3991
4007
4023
3976
3992
4008
4024
3977
3993
4009
4025
3978
3994
4010
4026
3979
3995
4011
4027
3980
3996
4012
4028
3981
3997
4013
4029
3982
3998
4014
4030
3983
3999
4015
4031
FCO
FDO
FEO
FFO
4032
4048
4064
4080
4033
4049
4065
4081
4034
4050
4066
4082
4035
4051
4067
4083
4036
4052
4068
4084
4037
4053
4069
4085
4038
4054
4070
4086
4039
4055
4071
4087
4040
4056
4072
4088
4041
4057
4073
4089
4042
4058
4074
4090
4043
4059
4075
4091
4044
4060
4076
4092
4045
4061
4077
4093
4046
4062
4078
4094
4047
4063
4079
4095
3332
3348
3364
3380
7
5
6
3333 3334 3335
3349 3350 3351
3365 3366 3367
3381 3382 3383
3395
3411
3427
3443
3396
3412
3428
3444
3458
3474
3490
3506
3459
3475
3491
3507
3460
3476
3492
3508
3461
3477
3493
3509
3462
3478
3494
3510
3521
3537
3553
3569
3522
3538
3554
3570
3523
3539
3555
3571
3524
3540
3556
3572
3525
3541
3557
3573
3584
3600
3616
3632
3585
3601
3617
3633
3586 3587
3602 3603
3618 3619
3634 3635
3588
3604
3620
3636
E40
E50
E60
E70
3648
3664
3680
3696
3649
3665
3681
3697
3650 3651
3666 3667
3682 3683
3698 3699
E80
E90
EAO
EBO
3712
3728
3744
3760
3713
3729
3745
3761
3714
3730
3746
3762
ECO
EDO
EEO
EFO
3776
3792
3808
3824
3777
3793
3809
3825
3778
3794
3810
3826
DOO
Dl0
D20
D30
1
3
2
0
3328 3329 3330 3331
3344 3345 3346 3347
3360 3361 3362 3363
3376 3377 3378 3379
D40
D50
D60
D70
3392
3408
3424
3440
3393
3409
3425
3441
3394
3410
3426
3442
D80
D90
DAO
DBO
3456
3472
3488
3504
3457
3473
3489
3505
DCO
DDO
DEO
DFO
3520
3536
3552
3568
Eoo
E10
E20
E30
xxx
3465
3481
3497
3513
Rev. B
INTEL CORPORATION, 3065 Bowers Avenue, Santa Clara, CA 95051 (408) 246-7501
...
",._, "../
.-:< -