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Reading Assignment
Reading Assignment
3 Implementation Technology
Reading Assignment
Reading Assignment
Roth
Digital IC Definitions
Amplitude and
Voltage Transfer
Characteristics
Digital IC Definitions
Noise Margins
Sources of noise
Definition of noise
margins
Propagation Delay
1 t PHL
2 t PLH
Propagation Delay
tPHL
tPLH
10
Propagation Delay
11
Propagation Delay
12
Propagation Delay
20 ns + 20 ns = 40 ns
13
Propagation Delay
14
Alternate
symbol and
more details
Current
flows only
when output
switching
Power is
frequency
dependent
15
Output switching
requires charging (or
discharging) parasitic
and gate capacitance
through a resistor(s)
Transistor on
resistance
Wire capacitance and
resistance
Gate capacitance
16
17
18
0 70 C
-55 125 C
19
54/74XX
54/74SXX
54/74LSXX
54/74ALSXX
54/74ACTXX
20
multiple emitter
input stage
21
22
23
24
Binary Numbers
Sign magnitude
Ones complement
Twos complement
25
Binary to Decimal
Decimal to Binary
26
Binary
Hexadecimal (24)
27
Half Adder
2 input bits
x
y
2 output bits
s (sum)
c (carry)
28
TTL Implementation
29
TTL Implementation
30
TTL Implementation
SN7400
tPLH (max) = 22 ns
tPHL (max) = 15 ns
31
TTL Implementation
Two possibilities
22 ns + 15 ns + 22 ns = 59 ns
32
33
34
Functional Simulation
0+0=00
0+1=01
1+0=01
1+1=10
35
36
Timing Simulation
37
tPLH
6ns
tPHL
6ns
38
I/O Delays
39
I/O Delays
Timing Simulation
tPLH 6ns
tPHL 6ns
January 25, 2012
40
VLSI Circuits
Intel 8080
Timing and Control
Instruction
Decode
Ground Pad
Arithmetic Logic Unit
41
VLSI Circuits
Intel
Pentium
42
Full Adder
Full Adder
By adding a carry in
input, multiple-bit
numbers can be added
by cascading full adder
stages
43
Full Adder
Generic Circuit
Implementation
44
Schematic
Capture
45
Timing Simulation
46
47
48
CPLD Implementation
Timing Simulation
3.5ns
9.5ns
49
CPLD Implementation
Timing Simulation
50
Addendum:
Power Dissipation in CMOS Circuits
Constant current
52
Static dissipation
53
Dynamic dissipation
54
55
56
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