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Masahiro Fujita

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'90
'80

2015

[j73]

Masahiro Fujita, Osamu Koike, Yukio Yamaguchi:


Direct simulation of drying colloidal suspension on
substrate using immersed free surface model. J.
Comput. Physics 281: 421-448 (2015)

[j72]

Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita,


Zainalabedin Navabi:
Automatic High-Level Data-Flow Synthesis and
Optimization of Polynomial Datapaths Using
Functional Decomposition. IEEE Trans. Computers 64(6):
1579-1593 (2015)

[j71]

Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Masataka Ikeda,


Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa,
Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu
Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
A Boosting Pass Gate With Improved Switching
Characteristics and No Overdriving for
Programmable Routing Switch Based on Crystalline
In-Ga-Zn-O Technology. IEEE Trans. VLSI Syst. 23(3): 422-434
(2015)

[c234]

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Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro


Fujita:

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

Temperature-aware software-based self-testing for


delay faults. DATE 2015: 423-428

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[c233]

Masahiro Fujita:
On Implementation of LUT with Large Numbers of
Inputs (Abstract Only). FPGA 2015: 277

[c232]

Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan


Mishchenko:
Incremental ATPG methods for multiple faults under
multiple fault models. ISQED 2015: 177-180

[c231]

Takanori Matsuzaki, Tatsuya Onuki, Shuhei Nagatsuka, Hiroki


Inoue, Takahiko Ishizu, Yoshinori Ieda, Naoto Yamade, Hidekazu
Miyairi, Masayuki Sakakura, Tomoaki Atsumi, Yutaka Shionoiri,
Kiyoshi Kato, Takashi Okuda, Yoshitaka Yamamoto, Masahiro
Fujita, Jun Koyama, Shunpei Yamazaki:
16.9 A 128kb 4b/cell nonvolatile memory with
crystalline In-Ga-Zn oxide FET using Vt, cancel write
method. ISSCC 2015: 1-3

[c230]

Reza Sharanejad, Bijan Alizadeh, Masahiro Fujita:


UPF-based formal verication of low power
techniques in modern processors. VTS 2015: 1-6

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2014

2 of 36

[j70]

Amir Masoud Gharehbaghi, Masahiro Fujita:


Automatic Rectication of Processor Design Bugs
Using a Scalable and General Correction Model. IEICE
Transactions 97-D(4): 852-863 (2014)

[j69]

Hiroaki Yoshida, Masayuki Wakizaka, Shigeru Yamashita,


Masahiro Fujita:
An Energy-Ecient Patchable Accelerator and Its
Design Methods. IEICE Transactions 97-A(12): 2507-2517
(2014)

[j68]

Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita:


SAT-based Automatic Rectication and Debugging of
Combinational Circuits with LUT Insertions. IPSJ T. on
System LSI Design Methodology 7: 46-55 (2014)

[j67]

Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Wataru Uesugi,


Atsuo Isobe, Naoaki Tsutsui, Yasutaka Suzuki, Yutaka Okazaki,
Yukio Maehashi, Jun Koyama, Yoshitaka Yamamoto, Shunpei

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

Yamazaki, Masahiro Fujita, James Myers, Pekka Korpinen:


Embedded SRAM and Cortex-M0 Core Using a 60-nm
Crystalline Oxide Semiconductor. IEEE Micro 34(6): 42-53
(2014)

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[j66]

Tetsuya Tsujikawa, Sami S. Zoghbi, Jinsoo Hong, Sean R.


Donohue, Kimberly J. Jenko, Robert L. Gladding, Christer Halldin,
Victor W. Pike, Robert B. Innis, Masahiro Fujita:
In vitro and in vivo evaluation of 11C-SD5024, a
novel PET radioligand for human brain imaging of
cannabinoid CB1 receptors. NeuroImage 84: 733-741
(2014)

[j65]

Talakad G. Lohith, Sami S. Zoghbi, Cheryl L. Morse, Maria D.


Ferraris Araneta, Vanessa N. Barth, Nancy A. Goebl, Johannes T.
Tauscher, Victor W. Pike, Robert B. Innis, Masahiro Fujita:
Retest imaging of [11C]NOP-1A binding to
nociceptin/orphanin FQ peptide (NOP) receptors in
the brain of healthy humans. NeuroImage 87: 89-95
(2014)

3 of 36

[c229]

Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh,


Masahiro Fujita, Zainalabedin Navabi:
Improving polynomial datapath debugging with
HEDs. ETS 2014: 1-6

[c228]

Yuki Ikeya, Masahiro Fujita, Junya Kani, Yuta Yoneyama,


Masakatsu Nishigaki:
An Image-Based CAPTCHA Using Sophisticated
Mental Rotation. HCI (24) 2014: 57-68

[c227]

Jorji Nonaka, Kenji Ono, Masahiro Fujita:


Multi-step image compositing for massively parallel
rendering. HPCS 2014: 627-634

[c226]

Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita,


Zainalabedin Navabi:
RTL datapath optimization using system-level
transformations. ISQED 2014: 309-316

[c225]

Amir Masoud Gharehbaghi, Masahiro Fujita:


Specication and formal verication of power
gating in processors. ISQED 2014: 604-610

[c224]

Masahiro Fujita:

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

Variation-Aware Analysis and Test Pattern


Generation Based on Functional Faults. ISVLSI 2014:
273-277

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[c223]

Masahiro Fujita, Alan Mishchenko:


Ecient SAT-based ATPG techniques for all multiple
stuck-at faults. ITC 2014: 1-10

[c222]

Shiori Arimura, Masahiro Fujita, Shinya Kobayashi, Junya Kani,


Masakatsu Nishigaki, Akira Shiba:
i/k-Contact: A context-aware user authentication
using physical social trust. PST 2014: 407-413

[c221]

Sriram Karunagaran, Karuna P. Sahoo, Jayaraj Poroor, Masahiro


Fujita:
MAESTRO: A time-driven embedded testbed
Architecture with Event-driven Synchronization.
RTAS 2014: 237-248

[c220]

Masahiro Fujita, Alan Mishchenko:


Logic synthesis and verication on xed topology.
VLSI-SoC 2014: 1-6

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2013

4 of 36

[j64]

Giuseppe Di Guglielmo, Luigi Di Guglielmo, Andreas Foltinek,


Masahiro Fujita, Franco Fummi, Cristina Marconcini, Graziano
Pravadelli:
On the integration of model-driven design and
dynamic assertion-based verication for embedded
software. Journal of Systems and Software 86(8): 2013-2033
(2013)

[c219]

Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto,


Masahiro Fujita:
Rectication of advanced microprocessors without
changing routing on FPGAs (abstract only). FPGA
2013: 279

[c218]

Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto,


Masahiro Fujita:
Debugging processors with advanced features by
reprogramming LUTs on FPGA. FPT 2013: 50-57

[c217]

Will X. Y. Li, Shridhar Chaudhary, Ray C. C. Cheung, Takeshi


Matsumoto, Masahiro Fujita:

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

Fast simulation of Digital Spiking Silicon Neuron


model employing recongurable dataow
computing. FPT 2013: 478-479

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[c216]

Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:


Hardware implementation of BLTL property
checkers for acceleration of statistical model
checking. ICCAD 2013: 670-676

[c215]

Masahiro Fujita, Satoshi Jo, Shohei Ono, Takeshi Matsumoto:


Partial synthesis through sampling with and
without specication. ICCAD 2013: 787-794

[c214]

Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:


A debugging method for gate level circuit designs
by introducing programmability. VLSI-SoC 2013: 78-83

[c213]

Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo:


FOF: Functionally Observable Fault and its ATPG
techniques. VLSI-SoC 2013: 108-111

[c212]

Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh


Tamarapalli, Sharad Kumar, Rajesh Mittal:
Tutorial T10: Post - Silicon Validation, Debug and
Diagnosis. VLSI Design 2013

[c211]

Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita,


Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos,
Antonis M. Paschalis, Adit D. Singh, Tian Xia:
Special session 4B: Elevator talks. VTS 2013: 1

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2012

5 of 36

[j63]

Viacheslav Izosimov, Giuseppe Di Guglielmo, Michele Lora,


Graziano Pravadelli, Franco Fummi, Zebo Peng, Masahiro Fujita:
Time-Constraint-Aware Optimization of Assertions in
Embedded Software. J. Electronic Testing 28(4): 469-486
(2012)

[j62]

Amir Masoud Gharehbaghi, Masahiro Fujita:


Transaction Ordering in Network-on-Chips for
Post-Silicon Validation. IEICE Transactions 95-A(12):
2309-2318 (2012)

[j61]

Yasuyuki Kimura, Fabrice G. Simon, Sami S. Zoghbi, Yi Zhang,


Jun Hatazawa, Victor W. Pike, Robert B. Innis, Masahiro Fujita:
Quantication of metabotropic glutamate subtype 5
Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

receptors in the brain by an equilibrium method


using

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[j60]

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18F-SP203.

NeuroImage 59(3): 2124-2130 (2012)

Paolo Zanotti-Fregonara, Christina S. Hines, Sami S. Zoghbi,


Jeih-San Liow, Yi Zhang, Victor W. Pike, Wayne C. Drevets, Alan G.
Mallinger, Carlos A. Zarate Jr., Masahiro Fujita, Robert B. Innis:
Population-based input function and image-derived
input function for [11C](R)-rolipram PET imaging:
Methodology, validation and application to the
study of major depressive disorder. NeuroImage 63(3):
1532-1541 (2012)

6 of 36

[c210]

Masahiro Fujita, Hiroaki Yoshida:


Post-silicon patching for verication/debugging
with high-level models and programmable logic.
ASP-DAC 2012: 232-237

[c209]

Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro


Fujita:
Automated data analysis techniques for a modern
silicon debug environment. ASP-DAC 2012: 298-303

[c208]

Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris,


Shigeru Yamashita, Masahiro Fujita:
On error tolerance and Engineering Change with
Partially Programmable Circuits. ASP-DAC 2012: 695-700

[c207]

Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita:


SAT-Based Automatic Rectication and Debugging
of Combinational Circuits with LUT Insertions. Asian
Test Symposium 2012: 19-24

[c206]

Amir Masoud Gharehbaghi, Masahiro Fujita:


Error Model Free Automatic Design Error Correction
of Complex Processors Using Formal Methods. Asian
Test Symposium 2012: 143-148

[c205]

Marco Bonato, Giuseppe Di Guglielmo, Masahiro Fujita, Franco


Fummi, Graziano Pravadelli:
Dynamic property mining for embedded software.
CODES+ISSS 2012: 187-196

[c204]

Masahiro Fujita:
Simulation-Based Analysis of Cyberphysical
Systems. DSD 2012: 485-492

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

[c203]

Masahiro Fujita, Hiroaki Yoshida:


Post-silicon debugging targeting electrical errors
with patchable controllers (abstract only). FPGA 2012:
271

[c202]

Amir Masoud Gharehbaghi, Masahiro Fujita:


Automatic rectication of design errors in complex
processors with programmable hardware. FPT 2012:
141-146

[c201]

Bijan Alizadeh, Masahiro Fujita:


A functional test generation technique for RTL
datapaths. HLDVT 2012: 64-70

[c200]

Masahiro Fujita:
Post-silicon verication and debugging with control
ow traces and patchable hardware. HLDVT 2012:
100-107

[c199]

Shohei Ono, Takeshi Matsumoto, Masahiro Fujita:


Automatic assertion extraction in gate-level
simulation using GPGPUs. ICCD 2012: 522-523

[c198]

Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro


Fujita:
SEU tolerant robust memory cell design. IOLTS 2012:
13-18

[c197]

Amir Masoud Gharehbaghi, Masahiro Fujita:


Transaction-based post-silicon debug of many-core
System-on-Chips. ISQED 2012: 702-708

[c196]

Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi,


Masahiro Fujita:
Polynomial datapath synthesis and optimization

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based on vanishing polynomial over Z2m and


algebraic techniques. MEMOCODE 2012: 65-74

7 of 36

[c195]

Masahiro Fujita:
Future direction of digital content: 20th
anniversary keynote talk. ACM Multimedia 2012: 1-2

[c194]

Koji Nakamaru, Toru Matsuoka, Masahiro Fujita:


Distance aware ray tracing for curves. SIGGRAPH
Posters 2012: 103

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

[c193]

Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro


Fujita:
SEU Tolerant Robust Latch Design. VDAT 2012: 223-232

[c192]

Takeshi Matsumoto, Shohei Ono, Masahiro Fujita:


An ecient method to localize and correct bugs in
high-level designs using counterexamples and
potential dependence. VLSI-SoC 2012: 291-294

[i2]

Grschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik


Roy, Matteo Sonza Reorda:
Verifying Reliability (Dagstuhl Seminar 12341).
Dagstuhl Reports 2(8): 57-73 (2012)

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2011

[j59]

Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:


Multi-Level Bounded Model Checking with Symbolic
Counterexamples. IEICE Transactions 94-A(2): 696-705 (2011)

[j58]

Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:


An Automatic Method of Mapping I/O Sequences of
Chip Execution onto High-level Design for
Post-Silicon Debugging. IEICE Transactions 94-A(7):
1519-1529 (2011)

[j57]

Hiroaki Yoshida, Masahiro Fujita:


Exact Minimum Factoring of Incompletely Specied
Logic Functions via Quantied Boolean Satisability.
IPSJ T. on System LSI Design Methodology 4: 70-79 (2011)

[j56]

Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan,


Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani
Narayan:
Data Flow Graph Partitioning Algorithms and Their
Evaluations for Optimal Spatio-temporal
Computation on a Coarse Grain Recongurable
Architecture. IPSJ T. on System LSI Design Methodology 4:
193-209 (2011)

[j55]

Paolo Zanotti-Fregonara, Sami S. Zoghbi, Jeih-San Liow, Elise


Luong, Ronald Boellaard, Robert L. Gladding, Victor W. Pike,
Robert B. Innis, Masahiro Fujita:
Kinetic analysis in human brain of [11C](R)-rolipram,
a positron emission tomographic radioligand to

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image phosphodiesterase 4: A retest study and use


of an image-derived input function. NeuroImage 54(3):
1903-1909 (2011)

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[c191]

Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita,


Mythri Alle, S. K. Nandy, Ranjani Narayan:
Dataow Graph Partitioning for Optimal SpatioTemporal Computation on a Coarse Grain
Recongurable Architecture. ARC 2011: 125-132

[c190]

Masahiro Fujita:
Utilizing high level design information to speed up
post-silicon debugging. ASP-DAC 2011: 301-305

[c189]

Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:


On-chip dynamic signal sequence slicing for
ecient post-silicon debugging. ASP-DAC 2011: 719-724

[c188]

Masahiro Fujita:
High Level Verication and Its Use at Pos-Silicon
Debugging and Patching. Asian Test Symposium 2011:
464-469

[c187]

Masahiro Fujita:
Synthesizing, Verifying, and Debugging SoC with
FSM-Based Specication of On-Chip Communication
Protocols. ATVA 2011: 43-50

[c186]

Hiroaki Yoshida, Masahiro Fujita:


An energy-ecient patchable accelerator for
post-silicon engineering changes. CODES+ISSS 2011:
13-20

[c185]

Viacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco


Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita:
Optimization of Assertion Placement in
Time-Constrained Embedded Systems. European Test
Symposium 2011: 171-176

[c184]

Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan,


S. K. Nandy:
Interconnect-topology independent mapping
algorithm for a Coarse Grained Recongurable
Architecture. FPT 2011: 1-5

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dblp: Masahiro Fujita

[c183]

Bijan Alizadeh, Masahiro Fujita:


Modular equivalence verication of polynomial
datapaths with multiple word-length operands.
HLDVT 2011: 9-16

[c182]

Amir Masoud Gharehbaghi, Masahiro Fujita:


Formal verication guided automatic design error
diagnosis and correction of complex processors.
HLDVT 2011: 121-127

[c181]

Giuseppe Di Guglielmo, Masahiro Fujita, Luigi Di Guglielmo,


Franco Fummi, Graziano Pravadelli, Cristina Marconcini,
Andreas Foltinek:
Model-driven design and validation of embedded
software. AST 2011: 98-104

[c180]

Hideo Tanida, Masahiro Fujita, Mukul R. Prasad, Sreeranga P.


Rajan:
Client-tier Validation of Dynamic Web Applications.
ICSOFT (2) 2011: 86-95

[c179]

Hideo Tanida, Mukul R. Prasad, Sreeranga P. Rajan, Masahiro


Fujita:
Automated System Testing of Dynamic Web
Applications. ICSOFT (Selected Papers) 2011: 181-196

[c178]

Bijan Alizadeh, Masahiro Fujita:


Early case splitting and false path detection to
improve high level ATPG techniques. ISCAS 2011:
1463-1466

[c177]

Amir Masoud Gharehbaghi, Masahiro Fujita:


Global transaction ordering in Network-on-Chips for
post-silicon validation. ISQED 2011: 284-289

[c176]

Bijan Alizadeh, Masahiro Fujita:


Debugging and optimizing high performance
superscalar out-of-order processors using formal
verication techniques. ISQED 2011: 297-302

[c175]

Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja,


Masahiro Fujita:
SEU tolerant SRAM cell. ISQED 2011: 597-602

[c174]

Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi,


Graziano Pravadelli, Stefano Soa:

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Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

EFSM-based model-driven approach to concolic


testing of system-level design. MEMOCODE 2011:
201-209

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[c173]

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Virendra Singh, Masahiro Fujita:


Tutorial: "Post silicon debug of SOC designs". SoCC
2011: 18

2010

[j54]

Kenshu Seto, Masahiro Fujita:


Custom Instruction Generation for Congurable
Processors with Limited Numbers of Operands. IPSJ T.
on System LSI Design Methodology 3: 57-68 (2010)

[j53]

Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita:


Performance Estimation with Automatic False-Path
Detection for System-Level Designs. IPSJ T. on System
LSI Design Methodology 3: 69-80 (2010)

[j52]

Hiroaki Yoshida, Masahiro Fujita:


Performance-Constrained Transistor Sizing for
Dierent Cell Count Minimization. JIP 18: 252-262 (2010)

[j51]

William C. Kreisl, Masahiro Fujita, Yota Fujimura, Nobuyo


Kimura, Kimberly J. Jenko, Pavitra Kannan, Jinsoo Hong, Cheryl L.
Morse, Sami S. Zoghbi, Robert L. Gladding, Steven Jacobson,
Unsong Oh, Victor W. Pike, Robert B. Innis:
Comparison of [11C]-(R)-PK 11195 and [11C]PBR28,
two radioligands for translocator protein (18 kDa) in
human and monkey: Implications for positron
emission tomographic imaging of this inammation
biomarker. NeuroImage 49(4): 2924-2932 (2010)

[j50]

Paolo Zanotti-Fregonara, Sami S. Zoghbi, Jeih-San Liow, Jinsoo


Hong, Ronald Boellaard, Victor W. Pike, Robert B. Innis, Masahiro
Fujita:
Category: Methodology: Quantication and
test-retest study of 11C-(R)-rolipram, a PET tracer of
the cAMP cascade, using an arterial input function
and an image-derived input function. NeuroImage
52(Supplement-1): S161 (2010)

[j49]

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Paolo Zanotti-Fregonara, Jeih-San Liow, Masahiro Fujita, Sami S.


Zoghbi, Claude Comtat, Elise Luong, Ronald Boellaard, Victor W.

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

Pike, Robert B. Innis:


Image-derived input function for brain imaging
using the high-resolution research tomograph.
NeuroImage 52(Supplement-1): S222 (2010)

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[j48]

Masahiro Fujita, Alan G. Mallinger, Carlos A. Zarate Jr., Leah P.


Dickstein, Sami S. Zoghbi, Victor W. Pike, Yi Zhang, Robert B.
Innis, Wayne C. Drevets:
Changes of brain phosphodiesterase 4 in major
depression. NeuroImage 52(Supplement-1): S51 (2010)

[j47]

Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita:


Coverage Driven High-Level Test Generation Using a
Polynomial Model of Sequential Circuits. IEEE Trans. on
CAD of Integrated Circuits and Systems 29(5): 737-748 (2010)

[j46]

Bijan Alizadeh, Masahiro Fujita:


Modular Datapath Optimization and Verication
Based on Modular-HED. IEEE Trans. on CAD of Integrated
Circuits and Systems 29(9): 1422-1435 (2010)

[c172]

Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita:


Pipelined Microprocessors Optimization and
Debugging. ARC 2010: 435-444

[c171]

Bijan Alizadeh, Masahiro Fujita:


Guided gate-level ATPG for sequential circuits using
a high-level test generation approach. ASP-DAC 2010:
425-430

[c170]

Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga,


Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita:
Towards minimizing execution delays on
dynamically recongurable processors: a case
study on REDEFINE. CASES 2010: 77-86

[c169]

Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita:


Aggressive overclocking support using a novel
timing error recovery technique on FPGAs (abstract
only). FPGA 2010: 288

[c168]

Bijan Alizadeh, Masahiro Fujita:


A debugging method for repairing post-silicon bugs
of high performance processors in the elds. FPT
2010: 328-331

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

[c167]

Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja,


Masahiro Fujita:
SEU tolerant SRAM for FPGA applications. FPT 2010:
491-494

[c166]

Finn Haedicke, Bijan Alizadeh, Grschwin Fey, Masahiro Fujita,


Rolf Drechsler:
Polynomial datapath optimization using constraint
solving and formal modelling. ICCAD 2010: 756-761

[c165]

Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:


Generation of I/O sequences for a high-level design
from those in post-silicon for ecient post-silicon
debugging. ICCD 2010: 402-408

[c164]

Masahiro Fujita, Hideo Tanida, Fei Gao, Tasuku Nishihara,


Takeshi Matsumoto:
Synthesis and formal verication of on-chip
protocol transducers through decomposed
specication. ISQED 2010: 515-523

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2009

13 of 36

[j45]

Masahiro Fujita:
Intelligence Dynamics: a concept and preliminary
experiments for open-ended learning agents.
Autonomous Agents and Multi-Agent Systems 19(3): 248-271
(2009)

[j44]

Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal


Urard:
Functional Equivalence Verication Tools in
High-Level Synthesis Flows. IEEE Design & Test of
Computers 26(4): 88-95 (2009)

[j43]

Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:


Word-Level Equivalence Checking in Bit-Level
Accuracy by Synthesizing Designs onto Identical
Datapath. IEICE Transactions 92-D(5): 972-984 (2009)

[j42]

Bijan Alizadeh, Masahiro Fujita:


A Unied Framework for Equivalence Verication of

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

Datapath Oriented Applications. IEICE Transactions


92-D(5): 985-994 (2009)

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[j41]

Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu,


Masahiro Fujita:
Interconnect-Aware Pipeline Synthesis for
Array-Based Architectures. IEICE Transactions 92-A(6):
1464-1475 (2009)

[j40]

Masahiro Fujita:
Trends in Formal Verication Techniques for C-based
Hardware Designs. IPSJ T. on System LSI Design
Methodology 2: 2-17 (2009)

[j39]

O. Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro


Fujita:
A Formal Approach for Debugging Arithmetic
Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems
28(5): 742-754 (2009)

[c163]

Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro


Fujita:
A Post-Silicon Debug Support Using High-Level
Design Description. Asian Test Symposium 2009: 137-142

[c162]

Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi:


Debugging from high level down to gate level. DAC
2009: 627-630

[c161]

O. Sarbishei, Bijan Alizadeh, Masahiro Fujita:


Polynomial datapath optimization using
partitioning and compensation heuristics. DAC 2009:
931-936

[c160]

Bijan Alizadeh, Masahiro Fujita:


Modular arithmetic decision procedure with
auto-correction mechanism. HLDVT 2009: 138-145

[c159]

Bijan Alizadeh, Masahiro Fujita:


Improved heuristics for nite word-length
polynomial datapath optimization. ICCAD 2009: 739-744

[c158]

Amir Masoud Gharehbaghi, Masahiro Fujita:


Transaction-based debugging of system-on-chips
with patterns. ICCD 2009: 186-192

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http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

[c157]

Hiroaki Yoshida, Masahiro Fujita:


Improving the accuracy of rule-based equivalence
checking of system-level design descriptions by
identifying potential internal equivalences. ISQED
2009: 366-370

[c156]

O. Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro


Fujita:
High-level optimization of integer multipliers over a
nite bit-width with verication capabilities.
MEMOCODE 2009: 56-65

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[e1]

Bernd Becker, V. Bertacoo, Rolf Drechsler, Masahiro Fujita:


Algorithms and Applications for Next Generation
SAT Solvers, 08.11. - 13.11.2009. Dagstuhl Seminar
Proceedings 09461, Schloss Dagstuhl - Leibniz-Zentrum fr
Informatik, Germany 2009 [contents]

[i1]

Bernd Becker, Valeria Bertacco, Rolf Drechsler, Masahiro Fujita:


09461 Abstracts Collection - Algorithms and
Applications for Next Generation SAT Solvers.
Algorithms and Applications for Next Generation SAT Solvers
2009

2008

15 of 36

[b1]

Masahiro Fujita, Indradeep Ghosh, Mukul R. Prasad:


Verication Techniques for System-Level Design. The
Morgan Kaufmann series in systems on silicon, Morgan
Kaufmann 2008, ISBN 978-0-12-370616-4, pp. I-VIII, 1-240

[j38]

Jens-Steen Gutmann, Masaki Fukuchi, Masahiro Fujita:


3D Perception and Environment Map Generation for
Humanoid Robot Navigation. I. J. Robotic Res. 27(10):
1117-1134 (2008)

[j37]

Masahiro Fujita, Kenshu Seto, Thanyapat Sakunkonchak:


Dependence Graph Based Verication and Synthesis
of Hardware/Software Co-Designs with SAT Related
Formulation. JSAT 5(1-4): 57-82 (2008)

[j36]

Masao Imaizumi, Emmanuelle Briard, Sami S. Zoghbi, Jonathan


P. Gourley, Jinsoo Hong, Yota Fujimura, Victor W. Pike, Robert B.
Innis, Masahiro Fujita:
Brain and whole-body imaging in nonhuman

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

primates of [11C]PBR28, a promising PET radioligand


for peripheral benzodiazepine receptors. NeuroImage
39(3): 1289-1298 (2008)

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Masahiro Fujita, Masao Imaizumi, Sami S. Zoghbi, Yota Fujimura,


Amanda G. Farris, Tetsuya Suhara, Jinsoo Hong, Victor W. Pike,
Robert B. Innis:
Kinetic analysis in healthy humans of a novel
positron emission tomography radioligand to image
the peripheral benzodiazepine receptor, a potential
biomarker for inammation. NeuroImage 40(1): 43-52
(2008)

[c155]

Hiroaki Yoshida, Masahiro Fujita:


Performance-Constrained Dierent Cell Count
Minimization for Continuously-Sized Circuits. DATE
2008: 1099-1102

[c154]

Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:


Multi-level Bounded Model Checking to detect bugs
beyond the bound. HLDVT 2008: 49-55

[c153]

Taro Takahashi, Toshimitsu Tsuboi, Takeo Kishida, Yasunori


Kawanami, Satoru Shimizu, Masatsugu Iribe, Tetsuharu
Fukushima, Masahiro Fujita:
Adaptive grasping by multi ngered hand with
tactile sensor based on robust force and position
control. ICRA 2008: 264-271

[c152]

Masahiro Fujita, Takeshi Matsumoto, Hiroaki Yoshida:


A HW/SW Co-Reuse Methodology Based on Design
Renement Templates in UML Diagrams. ICSOFT
(SE/MUSE/GSDCA) 2008: 240-245

[c151]

Ken'ichiro Nagasaka, Atsushi Miyamoto, Masakuni Nagano,


Hirokazu Shirado, Tetsuharu Fukushima, Masahiro Fujita:
Motion control of a virtual humanoid that can
perform real physical interactions with a human.
IROS 2008: 2303-2310

[c150]

O. Sarbishei, Bijan Alizadeh, Masahiro Fujita:


Arithmetic Circuits Verication without Looking for
Internal Equivalences. MEMOCODE 2008: 7-16

[c149]

Subash Shankar, Masahiro Fujita:

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

Rule-Based Approaches for Equivalence Checking of


SpecC Programs. MEMOCODE 2008: 39-48

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[c148]

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Kenshu Seto, Masahiro Fujita:


Custom Instruction Generation with High-Level
Synthesis. SASP 2008: 14-19

2007

17 of 36

[j34]

Masahiro Fujita, Yukio Yamaguchi:


Multiscale simulation method for self-organization
of nanoparticles in dense suspension. J. Comput.
Physics 223(1): 108-120 (2007)

[j33]

Shunsuke Sasaki, Tasuku Nishihara, Daisuke Ando, Masahiro


Fujita:
Hardware/Software Co-design and Verication
Methodology from System Level Based on System
Dependence Graph. J. UCS 13(13): 1972-2001 (2007)

[c147]

Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi


Komatsu, Masahiro Fujita:
Protocol Transducer Synthesis using Divide and
Conquer approach. ASP-DAC 2007: 280-285

[c146]

Bijan Alizadeh, Masahiro Fujita:


Automatic Merge-Point Detection for Sequential
Equivalence Checking of System-Level and RTL
Descriptions. ATVA 2007: 129-144

[c145]

Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:


Using Counterexample Analysis to Minimize the
Number of Predicates for Predicate Abstraction.
ATVA 2007: 553-563

[c144]

Takeshi Matsumoto, Daisuke Ando, Tasuku Nishihara, Masahiro


Fujita:
Development and Verication of a Collaborative
Printing Environment. C5 2007: 99-108

[c143]

Bijan Alizadeh, Masahiro Fujita:


A novel formal approach to generate high-level test
vectors without ILP and SAT solvers. HLDVT 2007:
97-104

[c142]

Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:


Interconnect-aware Pipeline Synthesis for Array
Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

based Recongurable Architectures. IESS 2007:


121-134

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[c141]

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Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro


Asada:
VLSI CAD Education and Exercise Course with Public
Domain Tools. MSE 2007: 111-112

2006

18 of 36

[j32]

Shunsuke Sasaki, Tasuku Nishihara, Masahiro Fujita:


Slicing-based Hardware/Software Co-design
Methodology From Functional Specications. Electr.
Notes Theor. Comput. Sci. 159: 265-280 (2006)

[j31]

Yu Liu, Satoshi Komatsu, Masahiro Fujita:


Synchronization Mechanism for Timed/Untimed
Mixed-Signal System Level Design Environment. IEICE
Transactions 89-A(4): 1018-1026 (2006)

[j30]

Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:


Synchronization Verication in System-Level Design
with ILP Solvers. IEICE Transactions 89-A(12): 3387-3396
(2006)

[j29]

Yu Liu, Satoshi Komatsu, Masahiro Fujita:


The AMS Extension to System Level Design
Language - SpecC. IEICE Transactions 89-A(12): 3397-3407
(2006)

[j28]

David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark


Kwan, Sreeranga P. Rajan:
Embedded Software Verication Using Symbolic
Execution and Uninterpreted Functions. International
Journal of Parallel Programming 34(1): 61-91 (2006)

[c140]

Ken Matsui, Masahiro Fujita:


Object-oriented analysis and specication for
HW/SW co-design with UML diagrams. ACST 2006:
38-43

[c139]

Masahiro Fujita, Tasuku Nishihara, Daisuke Ando:


System LSI distributed collaborative design
environment for both designers and CAD
developers/engineers. C5 2006: 175-183

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

[c138]

Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu,


Masahiro Fujita:
Dynamically recongurable protocol transducer. FPT
2006: 341-344

[c137]

Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:


Equivalence Checking with Rule-Based Equivalence
Propagation and High-Level Synthesis. HLDVT 2006:
162-169

[c136]

Satoshi Komatsu, Masahiro Fujita:


An optimization of bus interconnects pitch for
low-power and reliable bus encoding scheme. ISCAS
2006

[c135]

Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita:


Equivalence Checking of C Programs by Locally
Performing Symbolic Simulation on Dependence
Graphs. ISQED 2006: 370-375

[c134]

Masahiro Fujita, Subash Shankar, S. Shunsuke:


Equivalence checking: a rule-based approach.
MEMOCODE 2006: 197

[c133]

Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra:


Sequential Equivalence Checking. VLSI Design 2006:
18-19

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2005

19 of 36

[j27]

Satoshi Komatsu, Masahiro Fujita:


Low Power and Fault Tolerant Encoding Methods for
On-Chip Data Transfer in Practical Applications. IEICE
Transactions 88-A(12): 3282-3289 (2005)

[j26]

Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita:


An Equivalence Checking Method for C Descriptions
Based on Symbolic Simulation with Textual
Dierences. IEICE Transactions 88-A(12): 3315-3323 (2005)

[j25]

Masahiro Fujita:
Equivalence checking between behavioral and RTL
descriptions with virtual controllers and datapaths.
ACM Trans. Design Autom. Electr. Syst. 10(4): 610-626 (2005)

[j24]

Gregory S. Hornby, Seiichi Takamura, Takashi Yamamoto,

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

Masahiro Fujita:
Autonomous evolution of dynamic gaits with two
quadruped robots. IEEE Transactions on Robotics 21(3):
402-410 (2005)

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[c132]

Masahiro Fujita:
Behavior-RTL Equivalence Checking Based on Data
Transfer Analysis with Virtual Controllers and
Datapaths. CHARME 2005: 340-344

[c131]

Yosuke Bando, Takahiro Saito, Masahiro Fujita:


Hexagonal storage scheme for interleaved frame
buers and textures. Graphics Hardware 2005: 33-40

[c130]

Yu Liu, Satoshi Komatsu, Masahiro Fujita:


AMS Extensions for Timed/Untimed System-Level
Design Language. FDL 2005: 77-81

[c129]

Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:


Pipeline Scheduling for Array Based Recongurable
Architectures Considering Interconnect Delays. FPT
2005: 137-144

[c128]

Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro


Fujita:
System level design language extensions for
timed/untimed digital-analog combined system
design. ACM Great Lakes Symposium on VLSI 2005: 130-133

[c127]

Jens-Steen Gutmann, Masaki Fukuchi, Masahiro Fujita:


A modular architecture for humanoid robot
navigation. Humanoids 2005: 26-31

[c126]

Jens-Steen Gutmann, Masaki Fukuchi, Masahiro Fujita:


A Floor and Obstacle Height Map for 3D Navigation
of a Humanoid Robot. ICRA 2005: 1066-1071

[c125]

Jens-Steen Gutmann, Masaki Fukuchi, Masahiro Fujita:


Real-Time Path Planning for Humanoid Robot
Navigation. IJCAI 2005: 1232-1237

[c124]

Masahiro Fujita, Shunsuke Sasaki, Ken Matsui:


Object-oriented analysis and design of
hardware/software co-designs with dependence
analysis for design reuse. IRI 2005: 318-325

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

[c123]

Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:


Synchronization verication in system-level design
with ILP solvers. MEMOCODE 2005: 121-130

[c122]

Masahiro Fujita:
Extended abstract: a formal design approach from
software oriented UML descriptions to hardware
oriented RTL. MEMOCODE 2005: 241-242

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2004

21 of 36

[c121]

Masahiro Fujita, Takashi Kanai:


Precomputed Radiance Transfer with SpatiallyVarying Lighting Eects. CGIV 2004: 101-108

[c120]

Masahiro Fujita:
On equivalence checking between behavioral and
RTL descriptions. HLDVT 2004: 179-184

[c119]

Tsutomu Sawada, Tsuyoshi Takagi, Yukiko Hoshino, Masahiro


Fujita:
Learning behavior selection through interaction
based on emotionally grounded symbol concept.
Humanoids 2004: 450-469

[c118]

Yukiko Hoshino, Tsuyoshi Takagi, Ugo Di Proo, Masahiro Fujita:


Behavior Description and Control using Behavior
Module for Personal Robot. ICRA 2004: 4165-4171

[c117]

Jens-Steen Gutmann, Masaki Fukuchi, Masahiro Fujita:


Stair climbing for humanoid robots using stereo
vision. IROS 2004: 1407-1413

[c116]

Tsutomu Sawada, Tsuyoshi Takagi, Masahiro Fujita:


Behavior selection and motion modulation in
emotionally grounded architecture for QRIO
SDR-4XII. IROS 2004: 2514-2519

[c115]

Fumihide Tanaka, Kuniaki Noda, Tsutomu Sawada, Masahiro


Fujita:
Associated Emotion and Its Expression in an
Entertainment Robot QRIO. ICEC 2004: 499-504

[c114]

Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad,


Masahiro Fujita:
High Level Design Validation: Current Practices and

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

Future Directions. VLSI Design 2004: 9-11


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Masahiro Fujita:
Formal Verication of C Language Based VLSI
Designs. VLSI Design 2004: 93-

2003

[j23]

Minoru Asada, Oliver Obst, Daniel Polani, Brett Browning,


Andrea Bonarini, Masahiro Fujita, Thomas Christaller, Tomoichi
Takahashi, Satoshi Tadokoro, Elizabeth Sklar, Gal A. Kaminka:
An Overview of RoboCup-2002 Fukuoka/Busan. AI
Magazine 24(2): 21-40 (2003)

[j22]

Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika


Hasegawa:
An ethological and emotional basis for human-robot
interaction. Robotics and Autonomous Systems 42(3-4):
191-201 (2003)

[c112]

Satoshi Komatsu, Masahiro Fujita:


Irredundant address bus encoding techniques
based on adaptive codebooks for low power. ASP-DAC
2003: 9-14

[c111]

Farzan Fallah, Indradeep Ghosh, Masahiro Fujita:


Event-driven observability enhanced coverage
analysis of C programs for functional validation.
ASP-DAC 2003: 123-128

[c110]

Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi


Nanya:
Logic optimization for asynchronous speed
independent controllers using transduction
method. ASP-DAC 2003: 197-202

[c109]

Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian


Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John
O'Leary, Fabio Somenzi:
Formal verication - prove it or pitch it. DAC 2003:
710-711

[c108]

Edmund M. Clarke, Masahiro Fujita, David P. Gluch:


Model Checking for Dependable Software-Intensive
Systems. DSN 2003: 764

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

[c107]

Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto,


Thanyapat Sakunkonchak, Yoshihisa Kojima:
Field Modiable Architecture with FPGAs and its
Design/Verication/Debugging Methodologies. HICSS
2003: 279

[c106]

Yoshihiro Kuroki, Masahiro Fujita, Tatsuzo Ishida, Ken'ichiro


Nagasaka, Jin'ichi Yamaguchi:
A small biped entertainment robot exploring
attractive applications. ICRA 2003: 471-476

[c105]

Masahiro Fujita, Yoshihiro Kuroki, Tatsuzo Ishida, Toshi T. Doi:


Autonomous behavior control architecture of
entertainment humanoid robot SDR-4X. IROS 2003:
960-967

[c104]

Masahiro Fujita, Kohtaro Sabe, Yoshihiro Kuroki, Tatsuzo Ishida,


Toshi T. Doi:
SDR-4X II: A Small Humanoid as an Entertainer in
Home Environment. ISRR 2003: 355-364

[c103]

Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu,


Masahiro Fujita:
Engineering Changes in Field Modiable
Architectures. MEMOCODE 2003: 87-94

[c102]

Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro


Fujita, Kunihiro Asada:
Comparative Study On Verilog-Based And C-Based
Hardware Design Education. MSE 2003: 41-42

[c101]

Tetsuro Ogi, Toshio Yamada, Michitaka Hirose, Masahiro Fujita,


Kazuto Kuzuu:
High Presence Remote Presentation in the Shared
Immersive Virtual World. VR 2003: 289-290

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2002

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[j21]

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A.


Abraham, Donald S. Fussell, Masahiro Fujita:
Ecient Combinational Verication Using
Overlapping Local BDDs and a Hash Table. Formal
Methods in System Design 21(1): 95-101 (2002)

[j20]

Pedro U. Lima, Tucker R. Balch, Masahiro Fujita, Ral Rojas,


Manuela M. Veloso, Holly A. Yanco:

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

RoboCup 2001. IEEE Robot. Automat. Mag. 9(2): 20-30 (2002)


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[j19]

Hans-Dieter Burkhard, Dominique Duhaut, Masahiro Fujita,


Pedro U. Lima, Robin R. Murphy, Ral Rojas:
The road to RoboCup 2050. IEEE Robot. Automat. Mag.
9(2): 31-38 (2002)

[j18]

Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas


W. Reps, Subash Shankar, Tim Teitelbaum:
Program slicing for VHDL. STTT 4(1): 125-137 (2002)

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Thanyapat Sakunkonchak, Masahiro Fujita:


Verication of Event-Based Synchronization of
SpecC Description Using Dierence Decision
Diagrams. FORTE 2002: 369

[c99]

Masao Kubo, Masahiro Fujita:


Debug methodology for arithmetic circuits on
FPGAs. FPT 2002: 236-242

[c98]

Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto,


Masahiro Fujita:
Field modiable architecture with FPGAs and its
design methodology. FPT 2002: 382-385

[c97]

Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak,


Masahiro Fujita, Takashi Nanya:
An equivalence checking methodology for hardware
oriented C-based specications. HLDVT 2002: 139-144

[c96]

Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu,


Masahiro Fujita:
Field Modiable Architecture and its Design
Methodology: System Design Without Logic
Synthesis. IWLS 2002: 103-108

[c95]

Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi


Nanya:
Logic Optimization for Asynchronous SI Controllers
using Transduction Method. IWLS 2002: 245-250

[c94]

Hiroshi Nakamura, Takanori Arai, Masahiro Fujita:


Formal Verication of a Pipelined Processor with
New Memory. PRDC 2002: 321-324

[c93]

Masahiro Fujita:

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

Sony Four Legged Robot League at RoboCup 2002.


RoboCup 2002: 469-476

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[c92]

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Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita:


Simultaneous Circuit Transformation and Routing.
VLSI Design 2002: 479-483

2001

25 of 36

[j17]

Masahiro Fujita:
AIBO: Toward the Era of Digital Creatures. I. J. Robotic
Res. 20(10): 781-794 (2001)

[j16]

Jawahar Jain, Ingo Wegener, Masahiro Fujita:


A Note on Complexity of OBDD Composition and
Eciency of Partitioned-OBDDs over OBDDs. IEEE
Trans. Computers 50(11): 1289-1290 (2001)

[j15]

Indradeep Ghosh, Masahiro Fujita:


Automatic test pattern generation for functional
register-transferlevel circuits using assignment
decision diagrams. IEEE Trans. on CAD of Integrated Circuits
and Systems 20(3): 402-415 (2001)

[c91]

Masahiro Fujita, Gabriel Costa, Rika Hasegawa, Tsuyoshi Takagi,


Jun Yokono, Hideki Shimomura:
Architecture and preliminary experimental results
for emotionally grounded symbol acquisition. Agents
2001: 35-36

[c90]

Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika


Hasegawa:
Ethological Modeling and Architecture for an
Entertainment Robot. ICRA 2001: 453-458

[c89]

Tatsuzo Ishida, Yoshihiro Kuroki, Jin'ichi Yamaguchi, Masahiro


Fujita, Toshi T. Doi:
Motion entertainment by a small humanoid robot
based on OPEN-R. IROS 2001: 1079-1086

[c88]

Masahiro Fujita, Hiroshi Nakamura:


The standard SpecC language. ISSS 2001: 81-86

[c87]

Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R.


Gao, Rajesh K. Gupta, Preeti Ranjan Panda:
New Design Paradigms: What Needs to be
Standardized?. ISSS 2001: 94
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[c86]
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Takashi Michikawa, Takashi Kanai, Masahiro Fujita, Hiroaki


Chiyokura:
Multiresolution Interpolation Meshes. Pacic
Conference on Computer Graphics and Applications 2001: 60-69

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[j14]

Masahiro Fujita, Manuela M. Veloso, William T. B. Uther, Minoru


Asada, Hiroaki Kitano, Vincent Hugel, Patrick Bonnin,
Jean-Christophe Bouramou, Pierre Blazevic:
Vision, Strategy, and Localization Using the Sony
Robots at RoboCup-98. AI Magazine 21(1): 47-56 (2000)

[c85]

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro


Fujita:
Automatic partitioning for ecient combinatorial
verication. ASP-DAC 2000: 67-72

[c84]

Indradeep Ghosh, Masahiro Fujita:


Automatic test pattern generation for functional RTL
circuits using assignment decision diagrams. DAC
2000: 43-48

[c83]

Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita:


Ecient variable ordering using aBDD based
sampling. DAC 2000: 687-692

[c82]

Gregory Hornby, Seiichi Takamura, Osamu Hanagata, Masahiro


Fujita, Jordan B. Pollack:
Evolution of Controllers from a High-Level Simulator
to a High DOF Robot. ICES 2000: 80-89

[c81]

Masahiro Fujita:
Digital Creatures for Future Entertainment Robotics.
ICRA 2000: 801-806

[c80]

Gregory Hornby, Seiichi Takamura, Jun Yokono, Osamu


Hanagata, Takashi Yamamoto, Masahiro Fujita:
Evolving Robust Gaits with AIBO. ICRA 2000: 3040-3045

[c79]

Takashi Yamamoto, Masahiro Fujita:


A quadruped robot platform with basic software for
RoboCup-99 legged robot league. IROS 2000: 1026-1031

[c78]

Minoru Asada, Andreas Birk, Enrico Pagello, Masahiro Fujita,


Itsuki Noda, Satoshi Tadokoro, Dominique Duhaut, Peter Stone,

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dblp: Masahiro Fujita

Manuela M. Veloso, Tucker R. Balch, Hiroaki Kitano, Brian


Thomas:
Progress in RoboCup Soccer Research in 2000. ISER
2000: 363-372

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[c77]

Peter Stone, Minoru Asada, Tucker R. Balch, Masahiro Fujita,


Gerhard K. Kraetzschmar, Henrik Hautop Lund, Paul Scerri,
Satoshi Tadokoro, Gordon Wyeth:
Overview of RoboCup-2000. RoboCup 2000: 1-28

[c76]

Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar


Jain, Masahiro Fujita:
Hierarchical Error Diagnosis Targeting RTL Circuits.
VLSI Design 2000: 436-441

[c75]

Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain,


Masahiro Fujita, Michael S. Hsiao:
Testing, Verication, and Diagnosis in the Presence
of Unknowns. VTS 2000: 263-270

[] 1990 1999
1999

27 of 36

[j13]

Ashok Sudarsanam, Sharad Malik, Masahiro Fujita:


A Retargetable Compilation Methodology for
Embedded Digital Signal Processors Using a
Machine-Dependent Code Optimization Library.
Design Autom. for Emb. Sys. 4(2-3): 187-206 (1999)

[j12]

Masahiro Fujita, Hiroaki Kitano, Koji Kageyama:


A recongurable robot platform. Robotics and
Autonomous Systems 29(2-3): 119-132 (1999)

[j11]

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro


Fujita, Jacob A. Abraham, Donald S. Fussell:
An ecient lter-based approach for combinational
verication. IEEE Trans. on CAD of Integrated Circuits and
Systems 18(11): 1542-1557 (1999)

[c74]

Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama,


Masahiro Fujita:
Model Checking Based on Sequential ATPG. CAV 1999:
418-430

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dblp: Masahiro Fujita

[c73]

Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas


W. Reps, Subash Shankar, Tim Teitelbaum:
Program Slicing of Hardware Description
Languages. CHARME 1999: 298-312

[c72]

Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad


Malik:
Development of an optimizing compiler for a Fujitsu
xed-point digital signal processor. CODES 1999: 2-6

[c71]

Armin Biere, Alessandro Cimatti, Edmund M. Clarke, Masahiro


Fujita, Yunshan Zhu:
Symbolic Model Checking Using SAT Procedures
instead of BDDs. DAC 1999: 317-320

[c70]

Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro


Fujita, Pradeep Bollineni:
Multiple Error Diagnosis Based on Xlists. DAC 1999:
660-665

[c69]

Rajeev Murgai, Masahiro Fujita:


On Reducing Transitions Through Data
Modications. DATE 1999: 82-

[c68]

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro


Fujita, Jacob A. Abraham, Donald S. Fussell:
An Ecient Filter-Based Approach for Combinational
Verication. DATE 1999: 132-137

[c67]

Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita:


Speeding Up Look-up-Table Driven Logic Simulation.
VLSI 1999: 385-397

[c66]

Masahiro Fujita, Hiroaki Kitano, Toshitada Doi:


Syntactic-semantic analysis of recongurable robot.
IROS 1999: 1567-1572

[c65]

Manuela M. Veloso, Hiroaki Kitano, Enrico Pagello, Gerhard K.


Kraetzschmar, Peter Stone, Tucker R. Balch, Minoru Asada, Silvia
Coradeschi, Lars Karlsson, Masahiro Fujita:
Overview of RoboCup-99. RoboCup 1999: 1-34

[c64]

Rajeev Murgai, Jawahar Jain, Masahiro Fujita:


Ecient Scheduling Techniques for ROBDD
Construction. VLSI Design 1999: 394-401

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dblp: Masahiro Fujita

[c63]
'10
'00

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita:


On the Evaluation of Arbitrary Defect Coverage of
Test Sets. VTS 1999: 426-432

'90 1998
'80

29 of 36

[j10]

Masahiro Fujita, Hiroaki Kitano:


Development of an Autonomous Quadruped Robot
for Robot Entertainment. Auton. Robots 5(1): 7-18 (1998)

[j9]

Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien


Lee:
ATM switch design by high-level modeling, formal
verication and high-level synthesi. ACM Trans. Design
Autom. Electr. Syst. 3(4): 554-562 (1998)

[c62]

Masahiro Fujita, Hiroaki Kitano, Koji Kageyama:


Recongurable Physical Agents. Agents 1998: 54-61

[c61]

Juan D. Velsquez, Masahiro Fujita, Hiroaki Kitano:


An Open Architecture of Remotion and Behavior
Control of Autonomous Agents. Agents 1998: 473-474

[c60]

Masahiro Fujita:
Model Checking: Its Basics and Reality (Embedded
Tutorial). ASP-DAC 1998: 217-222

[c59]

Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira:


Using Complementation and Resequencing to
Minimize Transitions. DAC 1998: 694-697

[c58]

Masahiro Fujita, Sreeranga P. Rajan, Alan J. Hu:


Two Real Formal Verication Experiences: ATM
Switch Chip and Parallel Cache Protocol. FM-Trends
1998: 281-295

[c57]

Jawahar Jain, William Adams, Masahiro Fujita:


Sampling schemes for computing OBDD variable
orderings. ICCAD 1998: 631-638

[c56]

Hiroaki Kitano, Masahiro Fujita, Stphane Zrehen, Koji


Kageyama:
Sony Legged Robot for RoboCup Challenge. ICRA 1998:
2605-2612

[c55]

Manuela M. Veloso, William T. B. Uther, Masahiro Fujita, Minoru


Asada, Hiroaki Kitano:

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

Playing soccer with legged robots. IROS 1998: 437-442


'10

[c54]

Vamsi Boppana, Masahiro Fujita:


Modeling the unknown! Towards model-independent
fault and error diagnosis. ITC 1998: 1094-1101

[c53]

Masahiro Fujita, Stphane Zrehen, Hiroaki Kitano:


A Quadruped Robot for RoboCup Legged Robot
Challenge in Paris '98. RoboCup 1998: 125-140

[c52]

Sreeranga P. Rajan, Masahiro Fujita:


Integration of High-Level Modeling, Formal
Verication, and High-Level Synthesis in ATM Switch
Design. VLSI Design 1998: 552-557

'00
'90
'80

1997

[j8]

Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita:


Domain-Specic High-Level Modeling and Synthesis
for ATM Switch Prototyping. Design Autom. for Emb. Sys.
2(3-4): 319-338 (1997)

[j7]

Masahiro Fujita, Patrick C. McGeer:


Introduction to the Special Issue on Multi-Terminal
Binary Decision Diagrams. Formal Methods in System
Design 10(2/3): 135-136 (1997)

[j6]

Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao,


Masahiro Fujita, J. Yang:
Spectral Transforms for Large Boolean Functions
with Applications to Technology Mapping. Formal
Methods in System Design 10(2/3): 137-148 (1997)

[j5]

Masahiro Fujita, Patrick C. McGeer, Jerry Chih-Yuan Yang:


Multi-Terminal Binary Decision Diagrams: An
Ecient Data Structure for Matrix Representation.
Formal Methods in System Design 10(2/3): 149-169 (1997)

[j4]

Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita:


Power analysis and minimization techniques for
embedded DSP software. IEEE Trans. VLSI Syst. 5(1):
123-135 (1997)

[c51]

30 of 36

Masahiro Fujita, Koji Kageyama:


An Open Architecture for Robot Entertainment.
Agents 1997: 435-442

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[c50]

Sreeranga P. Rajan, Masahiro Fujita:


ATM Switch Design: Parametric High-Level Modeling
and Formal Verication. AMAST 1997: 437-450

[c49]

Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita:


Speeding up technology-independent timing
optimization by network partitioning. ICCAD 1997:
83-90

[c48]

Alan J. Hu, Masahiro Fujita, Chris Wilson:


Formal Verication of the HAL S1 System Cache
Coherence Protocol. ICCD 1997: 438-444

[c47]

Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L.


Sangiovanni-Vincentelli:
A Survey of Techniques for Formal Verication of
Combinational Circuits. ICCD 1997: 445-454

[c46]

Masahiro Fujita, Koji Kageyama:


A proposal of a quadruped robot platform for
RoboCup. IROS 1997

[c45]

Masahiro Fujita, Hiroaki Kitano, Koji Kageyama:


A Legged Robot for RoboCup Based on "OPENR".
RoboCup 1997: 168-180

[c44]

Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L.


Sangiovanni-Vincentelli:
Formal Verication of Combinational Circuit. VLSI
Design 1997: 218-225

[c43]

Rajeev Murgai, Masahiro Fujita:


Some Recent Advances in Software and Hardware
Logic Simulation. VLSI Design 1997: 232-238

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'80

1996

[j3]

[c42]

31 of 36

Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong,


Masahiro Fujita, Ramamohan Paturi:
Solving the net matching problem in
high-performance chip design. IEEE Trans. on CAD of
Integrated Circuits and Systems 15(8): 902-911 (1996)
Masahiro Fujita:
Verication of Arithmetic Circuits by Comparing Two
Similar Circuits. CAV 1996: 159-168

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dblp: Masahiro Fujita

[c41]

Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita:


Domain-Specic High-Level Modeling and Synthesis
for ATM Switch Design Using VHDL. DAC 1996: 585-590

[c40]

Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L.


Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita:
Decomposition Techniques for Ecient ROBDD
Construction. FMCAD 1996: 419-434

[c39]

Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L.


Sangiovanni-Vincentelli:
Partitioned ROBDDs - a compact, canonical and
eciently manipulable representation for Boolean
functions. ICCAD 1996: 547-554

[c38]

Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A.


Abraham, Donald S. Fussell:
On More Ecient Combinational ATPG Using
Functional Learning. VLSI Design 1996: 107-110

[c37]

Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita,


Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A study of composition schemes for mixed
apply/compose based construction of ROBDDs. VLSI
Design 1996: 249-253

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'80

1995

32 of 36

[c36]

Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita:


Advanced Verication Techniques Based on
Learning. DAC 1995: 420-426

[c35]

Edmund M. Clarke, Masahiro Fujita, Xudong Zhao:


Hybrid decision diagrams. ICCAD 1995: 159-163

[c34]

Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose:


Logic synthesis for a single large look-up table. ICCD
1995: 415-424

[c33]

Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng:


Simple tree-construction heuristics for the fanout
problem . ICCD 1995: 671-679

[c32]

Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita:


Power analysis and low-power scheduling
techniques for embedded DSP software. ISSS 1995:

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dblp: Masahiro Fujita

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

110-115
'10 1994
'00

[c31]

Ben Chen, Michihiro Yamazaki, Masahiro Fujita:


Bug Identication of a Real Chip Design by Symbolic
Model Checking. EDAC-ETC-EUROASIC 1994: 132-136

[c30]

Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita:


LP based cell selection with constraints of timing,
area, and power consumption. ICCAD 1994: 378-381

[c29]

Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton:


A redesign technique for combinational circuits
based on gate reconnections. ICCAD 1994: 632-637

[c28]

H. Sato, Michihiro Yamazaki, Masahiro Fujita:


YEPHCAD and FLORA: Logic Synthesis for Control
and Datapath. ICCD 1994: 527-530

[c27]

Masahiro Fujita, Jerry Chih-Yuan Yang, Edmund M. Clarke,


Xudong Zhao, Patrick C. McGeer:
Fast Spectrum Computation for Logic Functions
using Binary Decision Diagrams. ISCAS 1994: 275-278

'90
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1993

[j2]

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Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga:


Variable ordering algorithms for ordered binary
decision diagrams and their evaluation. IEEE Trans. on
CAD of Integrated Circuits and Systems 12(1): 6-12 (1993)

[c26]

Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao,


Masahiro Fujita, J. Yang:
Spectral Transforms for Large Boolean Functions
with Applications to Technology Mapping. DAC 1993:
54-60

[c25]

Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita:


An ecient algorithm for the net matching problem.
ICCAD 1993: 640-644

[c24]

Masahiro Fujita, Shinji Kono:


Synthesis of Controllers from Interval Temporal
Logic Specication. ICCD 1993: 242-245

[c23]

Takeshi Sakaguchi, Masahiro Fujita, Hiroshi Watanabe, Fumio


Miyazaki:

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dblp: Masahiro Fujita

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

Motion Planning and Control for a Robot Performer.


ICRA (3) 1993: 925-931

'10
'00 1992
'90
'80

[c22]

Kuang-Chien Chen, Masahiro Fujita:


Ecient Sum-to-One Subsets Algorithm for Logic
Optimization. DAC 1992: 443-448

[c21]

Masahiro Fujita, Yuji Kukimoto:


Patching Method for Lookup-Table Type FPLs. FPL
1992: 61-70

[c20]

Yuji Kukimoto, Masahiro Fujita:


Rectication method for lookup-table type FPGA's.
ICCAD 1992: 54-61

[c19]

Masahiro Fujita:
RTL Design Verication by Making Use of Datapath
Information. ICCD 1992: 592-597

[c18]

Kiyoshi Ohishi, Masaru Miyazaki, Masahiro Fujita, Yasumasa


Ogino:
Force control without force sensor based on mixed
sensitivity H

design method. ICRA 1992: 1356-1361

1991

34 of 36

[c17]

Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga,


Masahiro Fujita:
A Resynthesis Approach for Network Optimization.
DAC 1991: 458-463

[c16]

Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien


Chen:
Application of Boolean Unication to Combinational
Logic Synthesis. ICCAD 1991: 510-513

[c15]

Masahiro Fujita, Yusuke Matsunaga:


Multi-Level Logic Minimization Based on Minimal
Support and its Application to the Minimization of
Look-Up Table Type FPGAs. ICCAD 1991: 560-563

[c14]

Kuang-Chien Chen, Masahiro Fujita:


Concurrent Resynthesis for Network Optimization.
ICCD 1991: 44-48

[c13]

Zhen-Ping Lo, Masahiro Fujita, Behnam Bavarian:

Monday 27 July 2015 11:40 PM

dblp: Masahiro Fujita

http://dblp.uni-trier.de/pers/hd/f/Fujita:Masahiro

Analysis of Neighborhood Interaction in Kohonen


Neural Networks. IPPS 1991: 246-249

'10
'00 1990
'90
'80

[c12]

Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko


Tanaka:
A Data Path Verier for Register Transfer Level
Using Temporal Logic Language Tokio. CAV 1990: 76-85

[c11]

Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro


Fujita:
Boolean Resubstitution with Permissible Functions
and Binary Decision Diagrams. DAC 1990: 284-289

[c10]

Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda:


Automatic and Semi-Automatic Verication of
Switch-Level Circuits with Temporal Logic and
Binary Decision Diagrams. ICCAD 1990: 38-41

[c9]

Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda:


Multi-Level Logic Minimization Across Latch
Boundaries. ICCAD 1990: 406-409

[] 1980 1989
1989

[c8]

Yusuke Matsunaga, Masahiro Fujita:


Multi-level logic optimization using binary decision
diagrams. ICCAD 1989: 556-559

[c7]

Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita,


Hidehiko Tanaka:
Logic Design Assistence Using Temporal Logic Based
Language Tokio. LP 1989: 174-183

1988

[c6]

Masahiro Fujita, Hisanori Fujisawa, Nobuaki Kawato:


Evaluation and improvement of Boolean comparison
method based on binary decision diagrams. ICCAD
1988: 2-5

1986

[c5]

35 of 36

Masahiro Fujita, Shinji Kono, Hidehiko Tanaka, Tohru Moto-Oka:


Tokio: Logic Programming Language Based on
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Temporal Logic and its Compilation to Prolog. ICLP


1986: 695-709

'10
'00 1985
'90
'80

[c4]

T. Aoyagi, Masahiro Fujita, Tohru Moto-Oka:


Temporal Logic Programming Language Tokio Programming in Tokio. LP 1985: 128-137

[c3]

Shinji Kono, T. Aoyagi, Masahiro Fujita, Hidehiko Tanaka:


Implementation of Temporal Logic Programming
Language Tokio. LP 1985: 138-147

[c2]

Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko


Tanaka, Tohru Moto-Oka:
Using the Temporal Logic Programming Language
Tokio for Algorithm Description and Automatic CMOS
Gate Array Synthesis. LP 1985: 246-255

1984

[c1]

Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka:


Specifying Hardware in temporal Logic & Ecient
Synthesis of State-Diagrams Using Prolog. FGCS 1984:
572-581

1983

[j1]

Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka:


Temporal Logic Based Hardware Description and Its
Verication with Prolog. New Generation Comput. 1(2):
195-203 (1983)

[+] Coauthor Index

data released under the ODC-BY 1.0 license; see also our legal information page
last updated on 2015-07-26 02:11 CEST by the dblp team

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