MAHATMA GANDHI UNIVERSITY

SCHEME AND SYLLABI

FOR

M. Tech. DEGREE PROGRAMME

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

WITH SPECIALIZATION IN
VLSI & EMBEDDED SYSTEM
(2013 ADMISSION ONWARDS)

SCHEME AND SYLLABI FOR M. Tech. DEGREE

PROGRAMME IN
VLSI & EMBEDDED SYSTEMS

SEMESTER II
Hrs / Week
Sl.
No.

Course No.

Evaluation Scheme (Marks)

Subject

Sessional
L

P
TA

CT

Sub
Total

ESE

Total

Credits
(C)

MECVE 201

Embedded System Software

Architecture

25

25

50

100

150

MECVE 202

CMOS Analog Design -II

25

25

50

100

150

MECVE 203

CMOS Digital Design -II

25

25

50

100

150

MECVE 204

Embedded System Hardware

Architecture -II

25

25

50

100

150

MECVE 205

Elective I

25

25

50

100

150

MECVE 206

Elective II

25

25

50

100

150

MECVE 207

VLSI & Embedded System Design

Lab -II

25

25

50

100

150

MECVE 208

Seminar II

50

50

50

Total

18

225

175

400

700

1100

25

Elective I (MECVE 205)

Elective II (MECVE 206)

MECVE 205 - 1 High Speed Digital Design

MECVE 206 - 1 Low Power VLSI Design

MECVE 205 - 2 Testing of VLSI Circuits

MECVE 206 - 2 VLSI Signal Processing

MECVE 205 - 3 Hardware / Software Codesign

MECVE 206 - 3 Reconfigurable Computing

MECVE 205 - 4 Embedded Networking

MECVE 206 - 4 System Design with ARM processor

L Lecture, T Tutorial, P Practical

TA Teachers Assessment (Assignments, attendance, group discussion, Quiz, tutorials,

seminars,

etc.)
CT Class Test (Minimum of two tests to be conducted by the Institute)
ESE End Semester Examination to be conducted by the University
Electives:
New Electives may be added by the department according to the needs of emerging
fields of technology. The name of the elective and its syllabus should be submitted to the University
before the course is offered.

MECVE 201

EMBEDDED SYSTEM SOFTWARE

ARCHITECTURE

L T P C
3 1 0 4

Module I
Basics of embedded system development: Introduction, Overview of linkers & linking
process, Executable and linking format, Mapping Executable Images into Target Embedded
Systems.
Embedded system initialization: Introduction, Target system tools & image transfer, Target
boot scenarios, Target system software initialization sequence, On-chip debugging.
Device drivers: Definition, Device Drivers for Interrupt Handling, Memory Device Drivers,
On-board Bus Device Drivers, Board I/O Driver examples confined to initialization of Ethernet
and RS232.
Module II
Embedded Operating Systems: Process, Multitasking and Process Management- Process
implementation - Process scheduling - Inter task communication and synchronization using
Embedded Linux as example RTOS.
Module III
Embedded Operating Systems continued: Memory Management -User memory space Kernel memory space, I/O and File System Management, OS Standards-POSIX(Portable
Operating System Interface), OS Performance Guidelines, OSes and Board Support Packages
(BSPs) with Embedded Linux as example RTOS.
Module IV
Middleware: Definition, Middleware Examples - Networking Middleware Driver ExamplesInternet Layer Middleware (Internet Protocol) -Transport Layer Middleware (User Datagram
Protocol).
Application Software: Application Layer Software Examples - File Transfer Protocol (FTP)
Client Application, Simple Mail Transfer Protocol (SMTP) and E-Mail Hypertext Transfer
Protocol (HTTP) Client and Server.
References:
1. Tammy Noergaard, Embedded Systems Architecture: A Comprehensive Guide for
Engineers and Programmers. Elsevier, 2/e, 2010.
2. Qing Li & Caroline Yao, Real-Time Concepts for Embedded Systems, CMP Books,
2003
2

3. P. Raghavan, Amol Lad & Sriram Neelakandan, Embedded Linux System Design and
Development", Auerbach Publications,2006
4. Lyla B Das, Embedded Systems-An Integrated Approach, Pearson, 2012.
5. Peter

Barry

&

Patrick

Crowley,

Modern

Embedded

Computing,

Morgan

Kaufmann,2012
6. James K Peckol, Embedded Systems: A Contemporary Design Tool, Wiley, 2007.
7. M. Barr & Anthony Massa, Programming Embedded Systems, Second Edition,
O'Reilly, 2006.
8. G. C. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms
and Applications, Second Edition, Springer, 2005.
9. A. Burns & A. Wellings, Real-Time Systems and Programming Languages: Ada 95,
Real-Time Java and Real-Time POSIX, Third Edition, Addison-Wesley, 2001.
10. A. S. Berger, Embedded Systems Design: An Introduction to Processes, Tools and
Techniques, CMP Books, 2002.
11. David E. Simon, An Embedded Software Primer, Addison-Wesley, 2006.
12. Gregory Pottie & William Kaiser, Principles of Embedded Networked Systems
Design, Cambridge University Press, 2005.
13. Daniel Lewis, Fundamentals of Embedded Software, Prentice-Hall, 2001.
14. Raj Kamal, Embedded Systems: Architecture, Programming and Design, McGraw
Hill, 2008.

MECVE 202

CMOS ANALOG DESIGN II

L T P C
3 1 0 4

Module I
CMOS operational amplifier configuration:- Characterizing the Op-Amp Compensating the
Op-Amp without Buffer The cascode input Op-Amp, Operational transconductance amplifiers
(OTAs): Wide swing OTA Folded cascode OTA, The differential Output Op-Amp: Fully
differential folded cascode OTA Gain Enhancement
Module II
Comparators: Characterization of a comparator, Two stage open loop comparators, Other
Open loop Comparatos Pushpull output comparator folded cascode comparator
comparators capable of driving very large capacitive loads, Improving the performance of open
loop comparators Autozeroing Techniques comparator using hysteresis, Discrete Time
Comparators Regenerative Comparators, High Speed Comparators

Module III
Switched capacitor circuits- switched capacitor amplifiers, switched capacitor integrator,
Circuits- dynamic comparator- dynamic current mirrors- dynamic amplifier, Switched
capacitor comparators

Module IV
Digital-to-analog converters (DAC):- Digital-to-analog converter specifications, DAC
architectures- Digital input code Resistor string R-2R Ladder networks Current Steering
Charge scaling DACs- Cyclic DAC Pipeline DAC
Analog-to-digital converters (ADC):- Analog-to-digital converter specifications, ADC
architectures Flash ADC- Two step Flash ADC Pipeline ADC Integrating ADC
Successive approximation ADC
References:
1. R. Jacob Baker, Harry W Li, David E Boyce, CMOS Circuit Design, Layout, and
Simulation,3rd Edition, 1998
2. Philip E Allen, Douglas R Holberg, CMOS Analog Circuit Design, International
Student(Second) Edition, First Indian Edition 2010

3. Behzad Razavi , Design of Analog CMOS Integrated Circuits, Tata McGraw Hill
2008
4. Gray, Hurst, Lewis, Meyer, Analysis and Design of Analog Integrated Circuits, 5th
Edition, Wiely India,2010
5. David A Johns, Ken Martin, Analog Integrated Circuit Design Wiley India, 2010

MECVE 203

CMOS DIGITAL DESIGN II

L T P C
3 1 0 4

Module I.
Static latches and registers, Dynamic latches,design and timing issues: Sequencing Static
Circuits: Sequencing Methods, Max-Delay Constraints, Min-Delay Constraints, Time
Borrowing, Clock Skew. Circuit Design of Latches and Flip-Flops: Conventional CMOS
Latches and Flip-Flops, Pulsed Latches, Resettable Latches and Flip-Flops, Enabled Latches and
Flip-Flops, Incorporating Logic into Latches, Klass Semidynamic Flip-Flop (SDFF),
Differential Flip-Flops, Dual Edge-Triggered Flip-Flops, Radiation-Hardened Flip-Flops, True
Single-Phase-Clock (TSPC) Latches and Flip-Flops. Static Sequencing Element Methodology:
Choice of Elements, Characterizing Sequencing Element Delays, State Retention Registers,
Level-Converter Flip-Flops, Design Margin and Adaptive Sequential Elements, Two-Phase
Timing Types. Sequencing Dynamic Circuits: Synchronizers, Metastability, A Simple
Synchronizer, Communicating Between Asynchronous Clock Domains, Common Synchronizer
Mistakes, Arbiters, Degrees of Synchrony
Module II.
Designing arithmetic building blocks: Adders: Design considerations, Fast adders,
Multipliers: Unsigned Array Multiplication, Two's Complement Array Multiplication, Booth
Encoding, Column Addition, Final Addition, Fused Multiply-Add, Shifters: Funnel shifter,
Barrel shifter, Datapath design case study

Module III.
Designing of memory and array structures: SRAM: SRAM Cells, Row Circuitry, Column
Circuitry, Multi-Ported SRAM and Register Files, Large SRAMs, Low-Power SRAMs. Area,
Delay and Power of RAMs and Register Files. DRAM:

Subarray Architectures, Column

Circuitry, Embedded DRAM. Read-Only Memory: Programmable ROMs, NAND ROMs, Flash
Serial Access Memories: Shift Registers, Queues (FIFO, LIFO), Content-Addressable Memory:
Programmable Logic Arrays, Robust Memory Design: Redundancy, Error Correcting Codes
(ECC), Memory reliability and yield, Power dissipation in memories. Memory design:-case
study.

Module IV.
Power, Clock, I/O:

Power Distribution: On-Chip Power Distribution Network, IR Drops,

Ldi/dt Noise, On-Chip Bypass Capacitance, Power Network Modeling, Power Supply Filtering,
Charge

Pumps,

Substrate

Noise,

Energy

Scavenging

Clocks: Definitions, Clock System Architecture, Global Clock Generation, Global Clock
Distribution, Local Clock Gaters, Clock Skew Budgets, Adaptive Deskewing, PLLs and DLLs
I/O: Basic I/O Pad Circuits, Electrostatic Discharge Protection, Mixed-Voltage I/O, High-Speed
Links, High-Speed I/O channels, Channel Noise and Interference, High-Speed Transmitters and
Receivers, Synchronous Data Transmission, Clock Recovery in Source-Synchronous Systems,
Clock Recovery in Mesochronous Systems, Clock Recovery in Pleisochronous Systems
References:
1. Weste and Harris, CMOS VLSI Design: A Circuits and System Perspective, 4/e, 2011,
Addison Wesley [an imprint of Pearson].
2. Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, 3/e, Tata
McGraw-Hill Education, 2003.
3. Rabaey, Chandrakasan and Nikolic, Digital Integrated Circuits A Design
Perspective, 2/e, Pearson Education.
4. R. Jacob Baker, Harry W. Li, David E. Boyce, CMOS, Circuit Design, Layout, and
Simulation, 3/e, Wiley Interscience.

MECVE 204

EMBEDDED SYSTEM HARDWARE

ARCHITECTURE II

L T P C
3 1 0 4

Module 1
Interrupts And Interrupt debugging in embedded systems: - Interrupt Basics, Interrupt
Vectors, Edge and Level Sensitive Interrupts, Interrupt Priority, Interrupt Hardware, Interrupt
Bus Cycles, Daisy-Chained Interrupts, Other Types of Interrupts, Using Interrupt Hardware,
Interrupt Software, Interrupt Service Mechanics, Nested Interrupts, Passing Data to or from
the ISR,

Minimizing Low-Priority Interrupt Service Time, Debugging the Interrupts-

Potential interrupt problems, UART Transmit lock up, Interrupt time, Prioritizing interrupts,
Problems with vectored interrupts, daisy chained interrupts, missing interrupts.
Module II
Timing analysis in embedded systemsIntroduction, Timing Diagram Notation Conventions,
Fan-Out and Loading Analysis: DC and AC, Logic Family IC Characteristics and Interfacing,
Design Example: Noise Margin Analysis Spreadsheet, Worst-Case Timing Analysis Example
Module III
Hardware Test and Debug-. Putting Together a Strategy, Formulating a Plan, Formalizing the
Plan - Writing a Specification and Executing the Plan - The Test Procedure and Test Cases,
Egoless Design, Design Reviews, Module Debug and The First Steps, Testing and Debugging
Combinational Logic, Path Sensitizing, Masking and Untestable Faults, Single Variable
Multiple Paths,

Bridge Faults,

Boundary Scan Testing,

Debugging - Sequential Logic,

Scan Design Testing,

Memories and Memory Systems Testing,

Other Subsystem and

System Test
Module IV
Other Hardware Design Techniques- Diagnostics, Connecting Tools,
Methods,

Electromagnetic

Compatibility,

Electrostatic

Discharge

Construction

Effects,

Hardware

Development Tools, Other Specialized Design Considerations, Processor Performance Metrics

Choosing a Microcontroller and Other Design Decisions Introduction, Choosing the Right
Core, Building Custom Peripherals with FPGAs, Choice of development hardware to be used

References:
1. Stuart R Ball, Embedded Microprocessor Systems: Real World Design , 3/e, Elseiver,
2002.
2. Stuart Ball, Debugging Embedded Microprocessor Systems, Newness, 1998.
3. Jack Ganssle, Tammy Noergaard, Fred Eady, Lewin Edwards, David J. Katz,
RickGentile, Ken Arnold, Kamal Hyder, Bob Perrin, Creed Huddleston, Embedded
Hardware Know It all, Newness,Elseiver,2008.
4. James K. Peckol, Embedded Systems: A Contemporary Design Tool, 1/e, Wiley,
2007.
5. Tammy Noergaard, Embedded Systems Architecture, A Comprehensive Guide for
Engineers and Programmers,Newness,Elseiver,2012
6. Lyla B Das , Embedded systems-An integrated approach, Pearson Education, 2013
7. Peter Barry, Patrick Crowley, Modern Embedded Computing: Designing Connected,
Pervasive, Media-rich Systems, Elsevier, 2012
8. Peter Marwedel, Embedded System Design,Springer,2006
9. Frank Vahid & Tony D. Givargis, Embedded System Design: A Unified
Hardware/Software Introduction, 2000.
10. Steve Furber , ARM System-on-chip architecture, 2/e, Pearson Education
11. Wayne Wolf , Computers as Components-principles of Embedded computer system
design, Elseveir, 2005
12. Ken Arnold,

Embedded Controller Hardware Design,

LLH

Technology

publishing,2001
13. S. E. Derenzo, Practical Interfacing in the Laboratory: Using a PC for Instrumentation,
Data Analysis and Control, Cambridge, 2003.

MECVE 205 - 1

HIGH SPEED DIGITAL DESIGN

L T P C
3 0 0 3

Module I
High Speed Digital Design Fundamentals: Frequency and time, Time and distance, Lumped vs
distributed, four kinds of reactance- ordinary capacitance and inductance, mutual capacitance
and inductance, Relation of mutual capacitance and mutual inductance to cross talk.
High Speed properties of Logic gates: Power, Quicent vs active dissipation, Active power
driving a capacitive load, Input power, Internal dissipation, drive circuit dissipation, Totem pole
and open circuit speed, Sudden change in voltage and current.Packaging of Digital Systems:
Integrated circuit packages, Wire and cable, Connectors.
Module II
Measurement Techniques; Rise time and bandwidth of oscilloscope probes, self inductance of
probe ground loop, Effects of probe load on a circuit, slow down of a system clock, observing
cross talk, measuring operating margin.Transmission Lines; Problems of point to point wiring,
signal distortion, EMI, cross talk,ideal distortion less lossless transmission line, Electrical
models of wires.
Module III
Transmission Lines at High frequency: Infinite uniform transmission line, Lossy transmission
line, Low loss transmission line, RC transmission line, Skin effect, Mechanics of skin effect,
Proximity effect, Dielectric loss, Effects of source and load impedance, Reflections of a
transmission line, End termination, Source termination, Very short line
Module IV
Termination: end termination, Rise time, dc biasing, power dissipation, Source termination,
Resistance value, Rise time, Power dissipation, Drive current, Middle terminators, Connectors
mutual, series and parasitic capacitance. Power system: Stable voltage reference, Uniform
voltage distribution, resistance and inductance distribution wiring, series resistance and lead
inductance of a capacitance Clock Distribution: schemes, Timing margin, Clock skew, delay
adjustments, Clock jitter.
References:

10

1. Howard Johnson, High-Speed Digital Design: A Handbook of Black Magic, Prentice

Hall .
2. Masakazu Shoji, High Speed Digital Circuits, Addison Wesley Publishing Company
3. Jan M, Rabaey, Digital Integrated Circuits: A Design perspective, Second
Edition,2003
4. Dally W.S. & Poulton J.W., Digital Systems Engineering, Cambridge University Press

11

MECVE 205 - 2

TESTING OF VLSI CIRCUITS

L T P C
3 0 0 3

Module I
Introduction-VLSI testing process and Test Equipment-Test Economics and Product Qualitywhy fault modeling-Fault Modeling-Logic and Fault Simulation-glossary of Faults- single
stuck-at-faults-functional equivalence-bridging faults.
Module II
Logic simulation-modeling single states-algorithm for true value simulation-serial and parallel
fault simulation-Testability Measures-Combinational Circuit Test Generation- Sequential
Circuit Test Generation.
Module III
Design for testability Digital DFT and Scan design, Built-in Self test- random logic BIST and
memory logic BIST, Boundary Scan standard.
Module IV
Memory Test-Analog and Mixed signal Test-delay test-IDDQ Test. DFT Fundamentals- ATPQ
Fundamental-Scan Architecture and Technique. System Test- Embedded Core Test-Future
Testing.
References:
1. Viswani D Agarwal and Michael L Bushnell, Essentials of Electronic Testing of
Digital Memory and Mixed Signal VLSI Circuits, Springer, 2000.
2. Alfred L Cronch, Design for Test for Digital ICs and Embedded Core system,
Prentice Hall, 1999.
3. Niraj Jha and Sanjeep K Gupta, Testing of Digital Systems, Cambridge University
Press, 2003.
4. M. Abramovici, M A Breuer and A D Friedman, Digital systems Testing and
Testable Design, IEEE Press, 1994.

12

MECVE 205 - 3

HARDWARE SOFTWARE CODESIGN

L T P C
3 0 0 3

Module I
The nature of hardware & software - Introducing Hardware/Software Codesign The Quest for
Energy Efficiency The Driving Factors in Hardware/Software Codesign The Hardware
Software Codesign Space The Dualism of Hardware Design and Software Design More on
Modeling Concurrency and Parallelism
Data Flow Modeling and Implementation- The Need for Concurrent Models: An Example
Tokens, Analyzing Synchronous Data Flow Graphs Control Flow Modeling and the Limitations
of Data Flow Models Software Implementation of Data Flow Hardware Implementation of Data
Flow
Analysis of Control Flow and Data Flow- Data and Control Edges of a C Program,
Implementing Data and Control EdgesContruction of the Control Flow Graph Construction of
the Data Flow Graph Application: Translating C to Hardware Single-Assignment Programs
Module II
The Design Space of Custom Architectures: Finite State Machine with Datapath(FSMD)Cycle-Based Bit-Parallel Hardware, Hardware Modules, Finite State Machines, Finite State
Machines with Datapath Simulation and Register Transfer Level(RTL) Synthesis of FSMD
Proper FSMD. Greatest Common Divisor(GCD) in Verilog (GCD mapping in other languages
not required)
Microprogrammed Architectures-Limitations of Finite State Machines, Microprogrammed
Control, Microinstruction Encoding, The Microprogrammed Datapath Implementing a
MicroprogrammedMachine Microprogram Interpreters Microprogram Pipelining - Picoblaze: A
Contemporary Microprogram Controller
Module III
General-Purpose Embedded Cores-Processors, The Reduced Instruction Set Computer
(RISC) Pipeline, Program Organization, Analyzing the Quality of Compiled Code
SystemOnChip-The System-on-Chip(SoC) Concept, Four Design Principles in SoC
Architecture, Example: Portable Multimedia System

13

Module IV
Hardware/Software Interfaces & Applications: On-Chip Busses-Connecting Hardware and
Software On-Chip Bus Systems Bus Transfers Multimaster Bus Systems On-Chip Networks
Hardware/Software Interfaces- The Hardware/Software Interface, Synchronization Schemes,
Memory-Mapped Interfaces(Gezel modeling not required), Coprocessor Interfaces, CustomInstruction Interfaces
Trivium Crypto-Coprocessor- The trivium stream cipher algorithm Trivium for 8 bit platforms
References:
1.

Patrick

Schmount,

practical

introduction

to

hardware/software

Codesign,Springer,2010 (Module 1,2,3&4)

2.

Jrgen Staunstrup and Wayne Wolf, Hardware/Software Co-Design: Principles

and Practice ,Springer,

3.

Frank Vahid and Tony D. Givargis, Embedded System Design: A Unified

Hardware/Software Introduction,2000

4.

J. Banks, J. S. Carson II, B. L. Nelson, and D. M. Nicol,` Discrete-Event System

Simulation , Prentice-Hall, 2001.

5.

A. Jantsch, Modeling Embedded Systems and SoCs - Concurrency and Time in

Models of Computation: Morgan Kaufmann, 2003.

6.

S. A. Edwards, Languages for Digital Embedded Systems: Kluwer Academic

Publishers, 2000

14

MECVE 205 - 4

EMBEDDED NETWORKING

L T P C
3 0 0 3

Module I
Embedded Networking Requirements: Introduction to Network for Embedded Systems,
Introduction to buses and protocols for embedded networking: CAN Bus, I2C, SPI, USB,
Ethernet protocol, TCP/IP Protocol, Internet connectivity over an Ethernet connection, Wireless
- Bluetooth, ZigBee standard.
Module II
Controller Area Network : CAN Overview, Introduction, CAN 2.0b Standard (covering
Physical Layer, Message Frame Formats, Bus Arbitration, Message Reception and Filtering,
Error Management), Selecting a CAN Controller, CAN Development Tools,
Evaluating system requirements choosing devices and tools, Configuring single devices, Overall
network configuration, Network simulation, Network Commissioning, Advanced features and
testing.
Module III
SPI : Introduction, Features, Modes of Operation , External Signal Description, Functional
Description(Covering Master Mode, Slave Mode, Transmission Formats, Baud Rate Generation,
Error Conditions, Low Power Mode Options)
I2C : I2C-bus features, Modes of Operation - Standard-mode, Fast-mode ,Fast-mode plus, Ultra
fast mode(covering the following topics - Signals and Logic levels, Start/Stop conditions, byte
format, Acknowledge and Not-Acknowledge, Clock Synchronization, Arbitration, Clock
Stretching, Addressing, Call Addresses, Reset, DeviceID),Applications of I2C bus protocol.
Module IV
TCP/IP: TCP/IP: Introduction to TCP/IP: History, Architecture, Standards and Applications,
TCP/IP Architecture: Layering, Protocol Overview, Routers & Topology, IP routing, TCP
Architecture, UDP Architecture, Security Concepts.
ZigBee: Introduction , Comparison with Bluetooth, Short range wireless networking classes,
Zigbee & IEEE802.15.4 standard, Operating frequencies, data rate, interoperability, Device
types, Topologies, Communication basics, Association and Disassociation, binding, Selfforming and self-healing characteristics, Networking Layer functions, ZigBee gateway, Zigbee
Metaphor, Networking Examples - Home Automation

15

References:
1. Lyla B Das, Embedded Systems-An Integrated Approach, Pearson, 2012.
2. Olaf P Feiffer, Andrew Ayre & Christian Keyold, Embedded Networking with CAN and
CAN Open, Embedded System Academy 2005.
3. Marco Di Natale, Haibo Zeng, Paolo Giusto & Arakadeb Ghosal, Understanding and
Using the Controller Area Network ,Springer, 2012.
4. John Catsoulis, Designing Embedded Hardware, O'Reilly Media, Inc., 2002
5. NXP Semiconductors, I2C-bus Specification and User Manual , Rev. 5, October 2012.
(Available at http://www.nxp.com/documents/user_manual/UM10204.pdf)
6. Motorola Inc., S12SPIV3/D:SPI Block Guide V03.06, Feb 2003, (Available at
http://www.ee.nmt.edu/~teare/ee308l/datasheets/S12SPIV3.pdf)
7. Dr. Sidnie Feit, TCP/IP : Architectures, Protocols and Implementations with IPv6 and IP
Security, Tata McGraw Hill, Second Edition, 2008.
8. Martin W. Murhammer, Orcun Atakan, Stefan Bretz,Larry R. Pugh, Kazunari Suzuki,
David H. Wood, TCP/IP Tutorial and Technical Overview, International Technical
Support Organization-IBM, Sixth Edition ,October 1998.
9. Wayne Wolf, Computers as Components: Principles of Embedded Computing System
Design, Morgan Kaufman Publishers, 2008.

16

MECVE 206 - 1

LOW POWER VLSI DESIGN

L T P C
3 0 0 3

Module I
Physics of Power dissipation in MOSFET devices, Power dissipation CMOS.Circuit techniques
for leakage power reduction standby leakage control using transistor stacks, multiple Vth
techniques, Dynamic Vth techniques, supply voltage scaling technique
Module II
Design and test of low voltage CMOS Circuit design style, Non clocked logic, NMOS and
pseudo NMOS logic, Differential Cascade Voltage Switch logic, pass transistor logic, Clocked
logic family, Domino logic, Differential Current Switch Logic, Leakage current in deep sub
micron transistors, Deep submicron device design issues, Minimizing short channel effect, Low
voltage circuit design techniques
Module III
Low power static RAM organization of static RAM, MOS static RAM cell, Banked
organization of SRAMs, Reducing swings on bit lines, reducing power in write driver circuits,
reducing power in sense amplifier circuits
Module IV
Adiabatic switching Adiabatic charging, Adiabatic amplification, one stage and two stage
adiabatic buffer, fully adiabatic system, Adiabatic logic gates, fully adiabatic sequential circuits,
partially adiabatic sequential circuits, stepwise charging, pulsed power supplies
Reference
1. Kaushik Roy, Sharat C Prasad, Low power CMOS VLSI circuit design, Wiley India
2. Anatha P Chandrakasan, Robert W Brodersen, Low power digital CMOS Design, Kluwer
Academic
3. Kiat Seng Yeo, Kaushik Roy, Low voltage, low power VLSI sub systems, Tata McGraw
Hill
4. Gray Yeap, Practical low power digital VLSI design, Springer
5. Christian Piguet, Low power CMOS circuits, Taylor & Francis
6. Abdellatif Bellaouar, Mohamed I Elmasry, Low power digital VLSI design, Kluwer
Academic
17

MECVE 206 - 2

VLSI SIGNAL PROCESSING

L T P C
3 0 0 3

Module I
Representation of DSP algorithms. Iteration Bound: Loop Bound, Iteration Bound, LPM
Algorithm for iteration bound computation, Iteration Bound for multirate data flow graphs.
Pipelining and Parallel Processing: Introduction.
Module II
Timing Techniques: Retiming: introduction, properties, system inequalities, retiming
techniques Unfolding: Introduction, algorithm, properties, critical path, sample period reduction
Systolic architecture design: Introduction, Design Methodologies, Design B1 and B2.

Module III
Arithmetic architecture: Bit level arithmetic architecture, parallel multipliers, bit serial
multipliers, Canonic Singed digit arithmetic, distributed arithmetic.
The CORDIC Algorithms: Rotations and pseudo rotations, Basic CORDIC iterations, CORDIC
hardware, Generalized CORDIC
Module IV
Fast convolution algorithms: Cook Toom, Winograd, Parallel FIR filters: Fast FIR, Pipelining of
recursive filters: Introduction, pipeline interleaving, parallel processing in IIR filters.Scaling and
round off noise computation.

References:
1. Keshab V Parhi, VLSI Digital Signal Processing, Willey India.
2. Peter Pirsch, Architecture for Digital Signal Processing, Wiley.
3. Magdy A Bayoumi, VLSI design methodologies for DSP architecture.
4. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs, 2nd edition,
Oxford University Press, New York, 2010.
5. Israel Koren, Computer Arithmetic Algorithms, 2nd Edition, CRC Press, 2001
6. M.D. Ercegovac and T. Lang, Digital Arithmetic, Morgan Kaufmann Publishers - An
Imprint of Elsevier Science, 2004

18

MECVE 206 - 3

RECONFIGURABLE COMPUTING

L T P C
3 0 0 3

Module I:
Introduction to Adaptive/Reconfigurable Computing Computing Requirements, area, and
VLSI scaling Instructions Introduction to FPGA Custom Computing Machine Overview
Comparing Computing Machines.
Module II:
FPGA Technology and Architectures LUT devices and mapping (Look-up Table) ALU design
Placement and partitioning algorithms Routing algorithms - Spatial Computing architectures
Systolic Architectures and Algorithms Systolic Structures Bit Serial.
Module III:
Adaptive Network Architectures Static and Dynamic network Routing/embedding
Rearrangeable networks Reconfigurable bus Dynamic reconfiguration issues
Reconfiguration delay Partial reconfiguration OS support Reconfigurable Operating
Systems Device and task models Multitasking and runtime systems Dynamically
Reconfigurable Adaptive Viterbi Decoder.
Module IV:
Reconfigurable Computing Architectures Reconfigurable coprocessor based architectures
Compiler technology for coprocessor based architectures Mapping/scheduling algorithm
Reconfigurable pipelines Reconfigurable memories & caches Reconfigurable Computing
Applications, reconfigurability using Virtex T series.
References:
1. John V.Oldfield and Richard C. Dorf, Field Programmable Gate Arrays:
Reconfigurable Logic for Rapid Prototyping and Implementation of Digital
Systems, John Wiley & Sons, Inc., 1995.
2. Configware Reiner W. Hartenstein, Viktor K. Prasanna (Eds.): Reconfigurable
Architectures: High Performance, IT press Verlag, 1997.
3. Wayne Wolf, FPGA- based System Design, Prentice Hall, 2004.
4. R.Vaidynathan and J. I., Trahan, Dynamic Reconfiguration: Architectures and
Algorithms, Khuwer Academic/Plenum Publishers, New York, 2004.
19

MECVE 206 - 4

SYSTEM DESIGN WITH ARM PROCESSOR

L T P C
3 0 0 3

Module I:
ARM Introduction: Introduction to processor design-architecture and organization, Abstraction
in hardware design, Instruction set design, Processor design tradeoffs, RISC.
Overview of ARM architecture Architecture inheritance, Programmer`s model, Development
tools.
Module II:
Architectural support for high level languages: Data types, Floating point data types,
Conditional statements, Loops, Use of memory, Run-time environment.
Thumb instruction set-Thumb bit, Thumb programmer`s model, Thumb branch instructions,
Thumb software interrupt instructions.
Module III:
Architectural support for system development: ARM memory interface, AMBA, ARM
reference peripheral specifications, H/W system prototyping tools, ARM Emulator, JTAG,
ARM debug architecture, Embedded trace, signal processing support, ARM processor cores.
Module IV:
Memory Hierarchy: Memory size and speed, On-chip memory, Caches, Memory Management.
Architectural support for OS-Introduction, ARM system control coprocessor, ARM MMU
architecture, Context switching.
References
1. Steve Furber, ARM System-On-Chip Architecture, Pearson Education
2. Andrew N Sloss, Dominic Symes, Chris Wright, ARM System Developer`s Guide,
Elseveir, 2004
3. Wayne Wolf, Computers as Components: Principles of Embedded Computer
System Design, Elseveir

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MECVE 207

VLSI &EMBEDDED SYSTEM DESIGN LAB-II

L T P C
0 0 3 2

VLSI
Analog/Digital Based Experiments using appropriate Simulation Tool (sub micron technology)
I.

Part A (Analog VLSI Design)

Schematic Design, Simulation and Characterization of the following Analog Circuits

1. OPAMP
2. 2 - Stage OPAMP with CMFB
3. Comparator
4. 8 - Bit Current Steering DAC/ Charge Scaling DAC
5. 8- Bit SAR ADC

II.

Part B (Digital VLSI Design)

Schematic Design, Simulation and Characterization of the following CMOS Logic Circuits
1. Adders (Half adder, Full adder)
2. Flip-Flop (Master- Slave)
3. Combinational components (Encoders, Decoders & Multiplexers)
4. CMOS SRAM Cell, CMOS Memory (8X8) with R/W control

Embedded Experiments
I.

Part A HDL Based experiments (All the experiments should be verified by

downloading the programming file to FPGA/CPLD using JTAG interface.)
1. Familiarization of User Constraints File and generation of programming file.
2. Familiarization of IP core generator, Instantiation of Dual port RAM, FIFO,
Initialization of RAM using COE file.
3. Digital clock manager, clock multiplication/ division.
4. Realization of SPI master and slave (different port lines of the same FPGA may be used
for both transmission and reception).
5. Implementation of UART transmitter and receiver.
And applications of the above such as
6. Sync pulse generation and test pattern generation for VGA monitors.
7. Symmetrical and asymmetrical PWM generation.
8. Arbitrary waveform generation using parallel/SPI DAC
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9. Implementation of digital filters (input may be taken using Parallel ADC and output may
be observed using parallel DAC).

II.

Part B Embedded Processor /Controller based experiments to be done on a 16/32

bit Processor/Controller based boards (Note: All the experiments should be tested by
downloading the programming file to the target device)
a) Memory interfacing based experiments
b) Peripheral Interfacing based experiments (serial/parallel port based)
c) Bus arbitration based experiments
d) Experiments based on real time operating systems using Free RTOS or similar tools.
Exam duration of 3 hrs should be split into two slots of 1.5 hours each
Slot 1 Analog/Digital VLSI design based questions (as per the syllabus above)
Slot 2 Embedded based questions (a per the syllabus above)

MECVE 208

SEMINAR- II

L T P C
0 0 2 1

Each student shall present a seminar on any topic of interest related to the core / elective courses
offered in the first semester of the M. Tech. Programme. He / she shall select the topic based on
the references from international journals of repute, preferably IEEE journals. They should get
the paper approved by the Programme Co-ordinator / Faculty member in charge of the seminar
and shall present it in the class. Every student shall participate in the seminar. The students
should undertake a detailed study on the topic and submit a report at the end of the semester.
Marks will be awarded based on the topic, presentation, participation in the seminar and the
report submitted.

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