Fan 7392N

FAN7392
High-Current, High- and Low-Side, Gate-Drive IC

Features
Description
Floating Channel for Bootstrap Operation to +600V
The FAN7392 is a monolithic high- and low-side gate

drive IC, that can drive high-speed MOSFETs and IGBTs
that operate up to +600V. It has a buffered output stage
with all NMOS transistors designed for high pulse current
driving capability and minimum cross-conduction. Fairchilds high-voltage process and common-mode noise
canceling techniques provide stable operation of the
high-side driver under high dv/dt noise circumstances.
An advanced level-shift circuit offers high-side gate driver
operation up to VS=-9.8V (typical) for VBS=15V. Logic
inputs are compatible with standard CMOS or LSTTL
output, down to 3.3V logic. The UVLO circuit prevents
malfunction when VCC and VBS are lower than the specified threshold voltage. The high-current and low-output
voltage drop feature makes this device suitable for halfand full-bridge inverters, like switching-mode power supply and high-power DC-DC converter applications.
3A/3A Sourcing/Sinking Current Driving Capability

Common-Mode dv/dt Noise Canceling Circuit
3.3V Logic Compatible
Separate Logic Supply (VDD) Range from 3.3V to 20V
Under-Voltage Lockout for VCC and VBS
Cycle-by-Cycle Edge-Triggered Shutdown Logic
Matched Propagation Delay for Both Channels
Outputs In-phase with Input Signals
Available in 14-DIP and 16-SOP (Wide) Packages
Applications
High-Speed Power MOSFET and IGBT Gate Driver
Server Power Supply
Uninterrupted Power Supply (UPS)
Telecom System Power Supply
14-PDIP
16-SOP
Distributed Power Supply

Motor Drive Inverter
Ordering Information
Part Number
Operating
Temperature Range
FAN7392N
FAN7392M
Package
Eco Status
14-PDIP
-40C to +125C
FAN7392MX
16-SOP
Packing Method
Tube
RoHS
Tube
Tape and Reel
For Fairchilds definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
2009 Fairchild Semiconductor Corporation

FAN7392 Rev. 1.0.2
www.fairchildsemi.com
FAN7392 High-Current, High- and Low-Side, Gate-Drive IC
July 2009
Typical Application Diagrams
Up to 600V
Q1
15V
R1
NC
HO
VDD
VB
10
HIN
VS
CBOOT
HIN
Load
DBOOT
Controller SD
11
SD
NC
LIN
12
LIN
VCC
RBOOT
15V
C1
13
VSS
COM
Q2
R2
14
NC
LO
Figure 1. Typical Application Circuit (Referenced 14-DIP)
Up to 600V
Q1
R1
NC
HO
10
NC
VB
11
VDD
VS
HIN
12
HIN
NC
Controller SD
13
SD
NC
LIN
14
LIN
VCC
15V
CBOOT
Load
DBOOT
RBOOT
15V
C1
15
VSS
COM
Q2
R2
16
NC
LO
Figure 2. Typical Application Circuit (Referenced 16-SOP)

FAN7392 Rev. 1.0.2
2
VB
HO
VS
VCC
LO
COM
UVLO
9
PULSE
GENERATOR
HIN
DRIVER
VDD
10
SCHMITT
TRIGGER INPUT
12
SD
11
VSS
13
HS(ON/OFF)
UVLO
CYCLE-By-CYCLE
EDGE TRIGGERED
SHUTDOWN
LS(ON/OFF)
VSS/COM
LEVEL
SHIFT
DELAY
DRIVER
LIN
NOISE
CANCELLER
Pin 4, 8, and 14 are no connection
Figure 3. Functional Block Diagram (Referenced 14-Pin)
VB
HO
VS
VCC
LO
COM
UVLO
11
PULSE
GENERATOR
HIN
DRIVER
VDD
12
SCHMITT
TRIGGER INPUT
14
SD
13
VSS
15
HS(ON/OFF)
UVLO
CYCLE-By-CYCLE
EDGE TRIGGERED
SHUTDOWN
LS(ON/OFF)
VSS/COM
LEVEL
SHIFT
DELAY
DRIVER
LIN
NOISE
CANCELLER
Pin 4, 5, 9,10 and 16 are no connection
Figure 4. Functional Block Diagram (Referenced 16-SOP)

FAN7392 Rev. 1.0.2
3
Internal Block Diagram
Pin Configuration
14
NC
COM
13
VSS
VCC
12
LIN
NC
11
SD
VS
10
HIN
VB
VDD
HO
NC
(a) 14-DIP
16
NC
COM
15
VSS
VCC
14
LIN
NC
13
SD
NC
12
HIN
VS
11
VDD
VB
10
NC
HO
NC
FAN7392M
FAN7392
LO
LO
(b) 16-SOP (Wide Body)
Figure 5. Pin Configurations (Top View)
Pin Definitions
14-Pin
16-Pin
Name
LO
COM
Low-Side Return
VCC
Low-Side Supply Voltage
VS
High-Voltage Floating Supply Return
VB
High-Side Floating Supply
HO
High-Side Driver Output
11
VDD
Logic Supply Voltage
10
12
HIN
Logic Input for High-Side Gate Driver Output
11
13
SD
Logic Input for Shutdown Function
12
14
LIN
Logic Input for Low-Side Gate Driver Output
13
15
VSS
Logic Ground
4,8,14
4, 5, 9, 10, 16
NC
No Connect

FAN7392 Rev. 1.0.2
Description
Low-Side Driver Output
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25C unless otherwise specified.
Symbol
Characteristics
Min.
Max.
Unit
VB
High-Side Floating Supply Voltage
-0.3
625.0
VS
High-Side Floating Offset Voltage
VB-25.0
VB+0.3
VHO
High-Side Floating Output Voltage
VS-0.3
VB+0.3
VCC
-0.3
25.0
VLO
Low-Side Floating Output Voltage
-0.3
VCC+0.3
VDD
VSS
Logic Supply Offset Voltage
VIN
Logic Input Voltage (HIN, LIN and SD)
dVS/dt
VSS+25.0
VCC+0.3
VSS-0.3
VDD+0.3
50
V/ns
Allowable Offset Voltage Slew Rate
PD
Power Dissipation(1, 2, 3)
JA
Thermal Resistance
TJ
Maximum Junction Temperature
TSTG
-0.3
VCC-25.0
14-PDIP
1.6
16-SOP
1.3
14-PDIP
75
16-SOP
95
Storage Temperature
-55
W
C/W
+150
+150
Notes:
1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
2. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions, natural convection; and
JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.
3. Do not exceed power dissipation (PD) under any circumstances.
Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
VB
High-Side Floating Supply Voltage
VS+10
VS+20
VS
High-Side Floating Supply Offset Voltage
6-VCC
600
VHO
High-Side Output Voltage
VS
VB
VCC
10
20
VLO
Low-Side Output Voltage
VCC
VDD
VSS+3
VSS+20
VSS
Logic Supply Offset Voltage
-5
VIN
Logic Input Voltage
VSS
VDD
TA
Operating Ambient Temperature
-40
+125

FAN7392 Rev. 1.0.2
5
Absolute Maximum Ratings
VBIAS(VCC, VBS, VDD)=15.0V, VSS=COM=0V and TA=25C, unless otherwise specified. The VIH, VIL, and IIN
parameters are referenced to VSS and are applicable to the respective input leads: HIN, LIN, and SD. The VO and IO
parameters are referenced to VS and COM and are applicable to the respective output leads: HO and LO.
Symbol
Characteristics
Test Condition
Min. Typ. Max. Unit
Low-Side Power Supply Section

80
10
IQCC
Quiescent VCC Supply Current
VIN=0V or VDD
IQDD
Quiescent VDD Supply Current
VIN=0V or VDD
IPCC
Operating VCC Supply Current
fIN=20kHz, rms, VIN=15VPP
430
IPDD
Operating VDD Supply Current
fIN=20kHz, rms, VIN=15VPP
300
ISD
Shutdown Supply Current
SD=VDD
120
VCCUV+
VCC Supply Under-Voltage

Positive-Going Threshold Voltage
VIN=0V, VCC=Sweep
7.7
8.8
9.9
VCCUV-
VCC Supply Under-Voltage

Negative-Going Threshold Voltage
VIN=0V, VCC=Sweep
7.3
8.4
9.5
VCCUVH
VCC Supply Under-Voltage Lockout

Hysteresis Voltage
VIN=0V, VCC=Sweep
0.4
40
Bootstrapped Supply Section

A
IQBS
Quiescent VBS Supply Current
VIN=0V or VDD
60
IPBS
Operating VBS Supply Current
fIN=20kHz, rms value
500
VBSUV+
VBS Supply Under-Voltage

Positive-Going Threshold Voltage
VIN=0V, VBS=Sweep
7.7
8.8
9.9
VBSUV-
VBS Supply Under-Voltage

Negative-Going Threshold Voltage
VIN=0V, VBS=Sweep
7.3
8.4
9.5
VBSUVH
VBS Supply Under-Voltage Lockout

Hysteresis Voltage
VIN=0V, VBS=Sweep
Offset Supply Leakage Current
VB=VS=600V
ILK
130
0.4
V
50
Input Locic Section (HIN, LIN, and SD)

VDD=3V
2.4
VDD=15V
9.5
VIH
Logic 1 Input Threshold Voltage
VIL
Logic 0 Input Threshold Voltage
IIN+
Logic Input High Bias Current
VIN=VDD
IIN-
Logic Input Low Bias Current
VIN=0V
RIN
Logic Input Pull-Down Resistance
VDD=3V
0.8
VDD=15V
6.0
40
20
375
750
Gate Driver Output Section

VOH
High-Level Output Voltage (VBIAS - VO)
No Load (IO=0A)
1.5
VOL
Low-Level Output Voltage
No Load (IO=0A)
200
mV
IO+
Output High, Short-Circuit Pulsed Current(4)
VO=0V, PW 10s
2.5
3.0
IO-
Current(4)
VO=15V, PW 10s
2.5
3.0
Output Low, Short-Circuit Pulsed
VSS/COM VSS-COM/COM-VSS Voltage Educability

- VS
-5.0
Allowable Negative VS Pin Voltage for HIN

Signal Propagation to HO

FAN7392 Rev. 1.0.2
-9.8
5.0
-7.0
6
Electrical Characteristics
VBIAS(VCC, VBS, VDD)=15.0V, VSS=COM=0V, CLOAD=1000pF, TA=25C, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
130
180
ns
ton
Turn-On Propagation Delay Time
VS=0V
toff
Turn-Off Propagation Delay Time
VS=0V
150
200
ns
tsd
Shutdown propagation Delay Time(4)
130
180
ns
tr
Turn-On Rise Time
25
50
ns
tf
Turn-Off Fall Time
20
45
ns
35
ns
MT
Delay Matching, HO & LO Turn-On/Off
Note:
4. These parameters guaranteed by design.

FAN7392 Rev. 1.0.2
7
Dynamic Electrical Characteristics
200
160
180
tOFF [ns]
tON [ns]
180
140
160
120
140
100
120
80
-40
-20
20
40
60
80
100
100
-40
120
-20
Temperature [C]
50
50
40
40
30
20
10
10
20
40
60
80
100
0
-40
120
-20
Temperature [C]
100
120
20
40
60
80
100
120
Figure 9. Turn-Off Fall Time

vs. Temperature
30
30
MTOFF [ns]
MTON [ns]
80
Temperature [C]
Figure 8. Turn-On Rise Time

vs. Temperature
20
10
0
-40
60
30
20
-20
40
Figure 7. Turn-Off Propagation Delay

vs. Temperature
tF [ns]
tR [ns]
Figure 6. Turn-On Propagation Delay

vs. Temperature
0
-40
20
Temperature [C]
20
10
-20
20
40
60
80
100
0
-40
120
Temperature [C]
20
40
60
80
100
120
Temperature [C]
Figure 10. Turn-On Delay Matching vs. Temperature

FAN7392 Rev. 1.0.2
-20
Figure 11. Turn-Off Delay Matching vs. Temperature
8
Typical Characteristics
180
40
160
IIN+ [A]
tSD [ns]
30
140
120
10
100
80
-40
20
-20
20
40
60
80
100
0
-40
120
-20
Temperature [C]
20
40
60
80
100
120
Temperature [C]
Figure 12. Shutdown Propagation Delay

vs. Temperature
Figure 13. Logic Input High Bias Current

vs. Temperature
80
120
70
100
IQBS [A]
IQCC [A]
60
50
40
30
80
60
40
20
20
10
0
-40
-20
20
40
60
80
100
0
-40
120
-20
Temperature [C]
40
60
80
100
120
Figure 15. Quiescent VBS Supply Current

vs. Temperature
1000
1000
800
800
IPBS [A]
IPCC [A]
Figure 14. Quiescent VCC Supply Current

vs. Temperature
600
400
600
400
200
200
0
-40
20
Temperature [C]
-20
20
40
60
80
100
0
-40
120
Figure 16. Operating VCC Supply Current

vs. Temperature

FAN7392 Rev. 1.0.2
-20
20
40
60
80
100
120
Temperature [C]
Temperature [C]
Figure 17. Operating VBS Supply Current

vs. Temperature
9
Typical Characteristics (Continued)
9.5
9.0
VCCUV- [V]
VCCUV+ [V]
9.5
9.0
8.5
8.0
8.0
-40
8.5
7.5
-20
20
40
60
80
100
-40
120
-20
20
40
60
80
100
120
Temperature [C]
Temperature [C]
Figure 18. VCC UVLO+ vs. Temperature
Figure 19. VCC UVLO- vs. Temperature
9.5
9.0
VBSUV- [V]
VBSUV+ [V]
9.5
9.0
8.5
8.0
8.0
-40
8.5
7.5
-20
20
40
60
80
100
-40
120
-20
20
40
60
80
100
120
Temperature [C]
Temperature [C]
Figure 20. VBS UVLO+ vs. Temperature
Figure 21. VBS UVLO- vs. Temperature
1.5
20
15
10
VOH [V]
VOL [mV]
1.0
5
0
-5
0.5
-10
-15
0.0
-40
-20
20
40
60
80
100
-20
-40
120
Temperature [C]
20
40
60
80
100
120
Temperature [C]
Figure 22. High-Level Output Voltage

vs. Temperature

FAN7392 Rev. 1.0.2
-20
Figure 23. Low-Level Output Voltage

vs. Temperature
10
10
11
9
10
VIL [V]
VIH [V]
8
7
6
5
7
6
-40
-20
20
40
60
80
100
3
-40
120
-20
20
Figure 24. Logic High Input Voltage

vs. Temperature
80
100
120
Logic Threshold Voltage [V]
12
-8
VS [V]
60
Figure 25. Logic Low Input Voltage

vs. Temperature
-7
-9
-10
-11
-12
-40
40
Temperature [C]
Temperature [C]
-20
20
40
60
80
100
10
8
6
4
VIH
VIL
2
0
120
Temperature [C]
10
12
14
16
18
20
VDD Logic Supply Voltage [V]
Figure 26. Allowable Negative VS Voltage

vs. Temperature
Figure 27. Input Logic (HIN & LIN) Threshold Voltage

vs. VDD Supply Voltage
VS [V]
-4
VCC=VBS
-6
COM=0V
-8
TA=25C
-10
-12
-14
-16
10
11
12
13
14
15
16
17
18
19
20
Supply Voltage [V]
Figure 28. Allowable Negative Vs Voltage for HIN

Signal Propagation to High Side vs. Supply Voltage

FAN7392 Rev. 1.0.2
11
Switching Time Definitions
15V
NC
HO
VDD
VB
HIN
10
HIN
VS
SD
11
SD
NC
HO
10F
1nF
100nF
15V
(0 to 600V)
10F
15V
LIN
LIN
VCC
13
VSS
COM
14
NC
LO
12
10F
100nF
LO
1nF
Figure 29. Switching Time Test Circuit (Referenced 14-DIP)
HIN
LIN
SD
HO
LO
Shutdown
Skip
Figure 30. Input/Output Timing Diagram
HIN
LIN
50%
tON
50%
tR
tOFF
90%
HO
LO
tF
90%
10%
10%
Figure 31. Switching Time Waveform Definitions

FAN7392 Rev. 1.0.2
12
Switching Time Definitions (Continued)
50%
SD
tSD
90%
HO
LO
Figure 32. Shutdown Waveform Definition
HIN
LIN
50%
LO
10%
50%
MT
HO
10%
90%
90%
LO
MT
HO
Figure 33. Delay Matching Waveform Definitions

FAN7392 Rev. 1.0.2
13
Negative VS Transient
Figure 36 and Figure 37 show the commutation of the
load current between high-side switch, Q1, and low-side
freewheelling diode, D3, in same inverter leg. The parasitic inductances in the inverter circuit from the die wire
bonding to the PCB tracks are jumped together in LC and
LE for each IGBT. When the high-side switch, Q1, and
low-side switch, Q4, are turned on, the VS1 node is
below DC+ voltage by the voltage drops associated with
the power switch and the parasitic inductances of the circuit due to load current is flows from Q1 and Q4, as
shown in Figure 36. When the high-side switch, Q1, is
turned off and Q4, remained turned on, the load current
to flows the low-side freewheeling diode, D3, due to the
inductive load connected to VS1 as shown in Figure 37.
The current flows from ground (which is connected to the
COM pin of the gate driver) to the load and the negative
voltage present at the emitter of the high-side switching
device.
The bootstrap circuit has the advantage of being simple

and low cost, but has some limitations. The biggest difficulty with this circuit is the negative voltage present at
the emitter of the high-side switching device when highside switch is turned-off in half-bridge application.
If the high-side switch, Q1, turns-off while the load current is flowing to an inductive load, a current commutation occurs from high-side switch, Q1, to the diode, D2,
in parallel with the low-side switch of the same inverter
leg. Then the negative voltage present at the emitter of
the high-side switching device, just before the freewheeling diode, D2, starts clamping, causes load current to
suddenly flow to the low-side freewheeling diode, D2, as
shown in Figure 34.
DC+ Bus
Q1
D1
iLOAD
In this case, the COM pin of the gate driver is at a higher

potential than the VS pin due to the voltage drops associated with freewheeling diode, D3, and parasitic elements, LC3 and LE3.
ifreewheeling
Load
VS
DC+ Bus
Q2
LC1
D2
LC2
VLC1
Q2
Q1
D1
D2
iLOAD
LE1
Figure 34. Half-Bridge Application Circuits
VLE1
LE2
Load
VS1
This negative voltage can be trouble for the gate drivers

output stage, there is the possibility to develop an overvoltage condition of the bootstrap capacitor, input signal
missing and latch-up problems because it directly affects
the source VS pin of the gate driver, as shown in Figure
35. This undershoot voltage is called negative VS transient.
ifreewheeling
VS2
LC3
VLC4
LC4
Q4
Q3
D3
D4
LE3
VLE4
LE4
Figure 36. Q1 and Q4 Turn-On

Q1
DC+ Bus
GND
LC2
LC1
Q2
Q1
D1
D2
iLOAD
ifreewheeling
LE1
VS
GND
LC3
LE2
Load
VS1
VLC3
VS2
VLC4
Freewheeling
D3
LE3
LC4
Q4
Q3
VLE3
D4
VLE4
LE4
Figure 35. VS Waveforms During Q1 Turn-Off

Figure 37. Q1 Turn-Off and D3 Conducting

FAN7392 Rev. 1.0.2
14
Application Information
The FAN7392 has a negative VS transient performance

curve, as shown in Figure 38.
The recommended placement and selection of component as follows:

Place a bypass capacitor between the VDD and VSS
pins. A ceramic 1F capacitor is suitable for most

applications. This component should be placed as
close as possible to the pins to reduce parasitic elements.
The bypass capacitor from VCC to COM supports both
the low-side driver and bootstrap capacitor recharge.
A value at least ten times higher than the bootstrap
capacitor is recommended.
The bootstrap resistor, RBOOT, must be considered in
sizing the bootstrap resistance and the current developed during initial bootstrap charge. If the resistor is
needed in series with the bootstrap diode, verify that
VB does not fall below COM (ground). Recommended
use is typically 5 ~ 10 that increase the VBS time
constant. If the votage drop of of bootstrap resistor
and diode is too high or the circuit topology does not
allow a sufficient charging time, a fast recovery or
ultra-fast recovery diode can be used.
The bootstrap capacitor, CBOOT, uses a low-ESR
capacitor, such as ceramic capacitor.
-100
-90
-80
-70
VS [V]
-60
-50
-40
-30
-20
-10
0
0
100
200
300
400
500
600
700
800
900 1000
Pulse Width [ns]
Figure 38. Negative VS Transient Chracteristic

Even though the FAN7392 has been shown able to handle these negative VS tranient conditions, it is strongly
recommended that the circuit designer limit the negative
VS transient as much as possible by careful PCB layout
to minimized the value of parasitic elements and component use. The amplitude of negative VS voltage is proportional to the parasitic inductances and the turn-off
speed, di/dt, of the switching device.
It is stongly recommended that the placement of components is as follows:

Place components tied to the floating voltage pins (VB
and VS) near the respective high-voltage portions of

the device and the FAN7392. NC (not connected) pins
in this package maximize the distance between the
high-voltage and low-voltage pins (see Figure 5).
Place and route for bypass capacitors and gate resistors as close as possible to gate drive IC.
Locate the bootstrap diode, DBOOT, as close as possible to bootstrap capacitor, CBOOT.
The bootstrap diode must use a lower forward voltage
drop and minimal switching time as soon as possible
for fast recovery or ultra-fast diode.
General Guidelines
Printed Circuit Board Layout
The relayout recommended for minimized parasitic elements is as follows:
Direct tracks between switches with no loops or devia-
tion.
Avoid interconnect links. These can add significant
inductance.
Reduce the effect of lead-inductance by lowering
package height above the PCB.

Consider co-locating both power switches to reduce
track length.
To minimize noise coupling, the ground plane should
not be placed under or near the high-voltage floating

side.
To reduce the EM coupling and improve the power
switch turn-on/off performance, the gate drive loops
must be reduced as much as possible.

FAN7392 Rev. 1.0.2
15
Placement of Components
19.56
18.80
14
8
6.60
6.09
(1.74)
8.12
7.62
1.77
1.14
3.56
3.30
0.35
0.20
5.33 MAX
0.38 MIN
3.81
3.17
0.58
0.35
8.82
2.54
NOTES: UNLESS OTHERWISE SPECIFIED

THIS PACKAGE CONFORMS TO
A) JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS ARE EXCLUSIVE OF BURRS,
C) MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
Figure 39. 14-Lead Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

FAN7392 Rev. 1.0.2
16
Physical Dimensions
Physical Dimensions (Continued)

.
10.300.20
9.44
8.890
16
7.500.10
9.2 10.95
10.325
1
PIN ONE
INDICATOR
0.51
0.35
0.25
8
1.27
M
1.75 TYP
C B A
0.55 TYP
1.27 TYP
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10 C
0.200.10
0.75
0.25
SEATING PLANE
X 45
(R0.10)
GAGE PLANE
(R0.10)
0.25
8
0
NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, ISSUE E, DATED SEPT 2005.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
pdip8_dim.pdf
D) LANDPATTERN STANDARD: SOIC127P1030X265-16L
E) DRAWING FILENAME: MKT-16Brev2
SEATING PLANE
0.40~1.27
(1.40)
DETAIL A
SCALE: 2:1
M16BREV2
Figure 40. 16-Lead Small Outline Package (SOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

FAN7392 Rev. 1.0.2
17

FAN7392 Rev. 1.0.2
18

Fan 7392N

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FAN7392

High-Current, High- and Low-Side, Gate-Drive IC

Floating Channel for Bootstrap Operation to +600V

The FAN7392 is a monolithic high- and low-side gate

3A/3A Sourcing/Sinking Current Driving Capability

Distributed Power Supply

For Fairchilds definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

2009 Fairchild Semiconductor Corporation

FAN7392 High-Current, High- and Low-Side, Gate-Drive IC

FAN7392 High-Current, High- and Low-Side, Gate-Drive IC

Typical Application Diagrams

Figure 1. Typical Application Circuit (Referenced 14-DIP)

Figure 2. Typical Application Circuit (Referenced 16-SOP)

2009 Fairchild Semiconductor Corporation

Pin 4, 8, and 14 are no connection

Figure 3. Functional Block Diagram (Referenced 14-Pin)

Pin 4, 5, 9,10 and 16 are no connection

Figure 4. Functional Block Diagram (Referenced 16-SOP)

2009 Fairchild Semiconductor Corporation

FAN7392 High-Current, High- and Low-Side, Gate-Drive IC

Internal Block Diagram

FAN7392 High-Current, High- and Low-Side, Gate-Drive IC

(b) 16-SOP (Wide Body)

Figure 5. Pin Configurations (Top View)

Low-Side Supply Voltage

High-Voltage Floating Supply Return

High-Side Floating Supply

High-Side Driver Output

Logic Supply Voltage

Logic Input for High-Side Gate Driver Output

Logic Input for Shutdown Function

Logic Input for Low-Side Gate Driver Output

2009 Fairchild Semiconductor Corporation

High-Side Floating Supply Voltage

High-Side Floating Offset Voltage

High-Side Floating Output Voltage

Low-Side Supply Voltage

Low-Side Floating Output Voltage

Logic Supply Voltage

Logic Supply Offset Voltage

Logic Input Voltage (HIN, LIN and SD)

Allowable Offset Voltage Slew Rate

Maximum Junction Temperature

Recommended Operating Conditions

High-Side Floating Supply Voltage

High-Side Floating Supply Offset Voltage

High-Side Output Voltage

Low-Side Supply Voltage

Low-Side Output Voltage

Logic Supply Voltage

Logic Supply Offset Voltage

Logic Input Voltage

Operating Ambient Temperature

2009 Fairchild Semiconductor Corporation

FAN7392 High-Current, High- and Low-Side, Gate-Drive IC

Absolute Maximum Ratings

Min. Typ. Max. Unit

Low-Side Power Supply Section

Quiescent VCC Supply Current

Quiescent VDD Supply Current

Operating VCC Supply Current

fIN=20kHz, rms, VIN=15VPP

Operating VDD Supply Current