.

RAM ADDRESS DECODERS

Open Defects in CMOS RAM

Address Decoders
MANOJ SACHDEV
Philips Research Laboratories

Field failures of
embedded SRAMs led
the author to identify
open defects that escape
detection by
conventional march tests.
Appropriate decodertesting and DFT
strategies can uncover
these hard-to-detect
defects.

26

RANDOM-ACCESS

MEMORIES enjoy a
strategic position in the microelectronics industry. In many respects, RAM testing is different from conventional logic testing. RAMs
are the largest and densest circuits produced. Their small feature size and huge
chip size result in an enormous critical area
for defects.1 High complexity and defect sensitivity have pushed RAM test costs to the extreme. To cope with these economic and
qualitative issues, researchers have proposed a variety of test solutions (van de Goor
provides an overview2).
A common method of testing RAMs is to
perform what are known as march tests.2 In
a march test, individual march elements traverse all RAM addresses and perform a specified combination of read and write
operations. For example, a typical march element first reads each RAM address location
and then writes back the complement of expected data values. Together, all the march
elements should cover all the likely faults in
a given RAM.
After compiling the likely faults into a
RAM fault model, the test engineer develops
a test algorithm to cover it. The total number
of memory operations performed by all
march elements for a given RAM address determines a test algorithms overall complexity. The complexity of march test algorithms
is linear with respect to the address space;

0740-7475/97/$10.00 1997 IEEE

hence, they are also known as linear algorithms. Algorithms designated 13N, 6N, and
9N3,4 are examples of march tests.
Conventional wisdom suggests that we
can map RAM decoder defects as RAM array faults and detect them by testing the
RAM array.5 Hence, it would seem, address
decoders need no special testing. Recently,
however, Philips researchers came across
some open defects in RAM address decoders
that march tests did not detect and that resulted in field failures. This development
prompted us to look into the test implications of such defects.
Open defects, or stuck-open transistor
faults, cause sequential behavior in CMOS
circuits and require a two-pattern test sequence, T1 and T2, for their detection.6 Open
defects in RAM matrixes appear as cell read
failures, row/column read failures, or cell
stuck-at (SA) faults, 3,4 all detectable by
march tests. But march tests fail to detect one
class of open defects in address decoders.
Transistor and logic testability for stuckopen faults has received considerable
attention, resulting in a number of design-fortestability (DFT) solutions.6,7 However, performance and area constraints make
application of these solutions to RAM decoders unlikely. Furthermore, address decoder defects are not directly observable. The
tester must excite them in a way that makes

IEEE DESIGN & TEST OF COMPUTERS

them detectable via a read

operation in the RAM.
Finally, owing to addressingsequence constraints, march
tests cannot ensure the detection of these open defects.
For these reasons, existing
DFT solutions are impractical
for RAM decoders, and testing for these faults remains a
challenge. Hence, we propose test and testability strategies for their detection.

Motivation: CMOS

WL63
A10

A9

Output

WL62

WL61

Inputs

WL60
A8
(a)
A7

WL03

A6

WL02
Output
WL01

Most previous research on

WL00
RAM testing focused on de- A5
Inputs
veloping efficient test algorithms for a variety of fault
models. These fault models Phix A11
ranged from simple SA faults
(b)
to complex pattern-sensitive
faults in the RAM array. Figure 1. A typical address decoder with NMOS (a) and CMOS (b) five-input NAND gate
However, researchers paid implementations. Phix: timing signal; A: address bits; WL: word line.
little attention to faults in address decoders or other RAM
building blocks. They assumed that RAM array tests would detection by march tests.
Figure 1 illustrates a typical address decoder, with NMOS
test address decoder faults implicitly.
An address decoder is a combinational circuit that selects and CMOS logic implementations. An NMOS logic gate uses
a unique RAM cell for each given RAM address. Assuming a depletion-mode NMOS load transistor and switching enthat a faulty address decoder does not become sequential hancement-mode transistors. In contrast, a fully static CMOS
in its operation, Thatte and Abraham5 held that a faulty ad- logic gate consists of an equal number of enhancementmode PMOS and NMOS transistors.
dress decoder behaves in one of two ways:
An address decoder selects a word line according to the
input address. This requires logic gate outputs in the address
no accessthe decoder will not access the addressed
cell. In addition, it may access nonaddressed cell(s). decoder to be active only for a unique input address and in multiple accessthe decoder will access multiple cells,
active for the rest. For example, for the NAND gates in Figure
including the addressed cell.
1, the output is active (logic 0) only if all the gates inputs
are high, and inactive (logic 1) in the rest of the cases.
In the case of no access, the cell contains either an SA0 or
In NMOS technology, the depletion-mode load transistor
SA1 fault. In the case of multiple access, the fault is a RAM- pulls up the output to the inactive state when inputs are not
matrix coupling fault between different cells. In simple activating the gate. An open defect in an NMOS logic gates
terms, Thatte and Abrahams position is that decoder faults switching transistor causes the gate to remain inactive when
manifest themselves as RAM-matrix faults, which we can test it should be active. In other words, such a defect prevents the
using conventional algorithms.
address decoder from accessing the addressed cell. On the
However, Thatte and Abraham conducted their study on other hand, if there is an open defect in the load transistor, the
an NMOS decoder. Open defects in NMOS address decoders logic gate remains active, resulting in a multiple-access fault.
A CMOS logic gate in the address decoder arrives at the accause logic SA faults. As the technology changed to CMOS,
researchers did not reevaluate the prevailing assumptions tive state in the same manner. But it reaches the inactive state
validity for the newer technology. In CMOS technology, only by several parallel paths (depending on the fan-in) selected
a subset of open defects cause logic SA behavior. The rest by the input addresses. We shall see later that open defects
cause sequential behavior in logic gates and thus escape in these parallel paths to inactivation cause the problem.

APRILJUNE 1997

27

RAM ADDRESS DECODERS

A2 A1 A0

Column decoder

111

A7
A6
A5
A4
A3

Word-line decoder

00100

1. Write C (10110 111) with logic 1.

2. Write A (00100 111) with logic 0.
3. Read C: result is logic 1, which is correct.

Observation: Address input A4 has changed; the RAM behaves normally.

RAM matrix
00110

10110

Figure 2. A failure in an embedded SRAM.

A missing contact or via is a dominant source of open defects in CMOS technology. For a DRAM process, the contact
depth is much higher than in a logic process, increasing the
sensitivity to open defects. According to the Semiconductor
Industry Associations semiconductor technology roadmap,8
the contact/via height-width aspect ratio is 4.5:1 for a typical DRAM process; for a typical logic process, it is 2.5:1. In
future DRAM generations, the association expects the contact/via aspect ratio to become 10.5:1 and the logic aspect
ratio to become 6.2:1. The projected increase in aspect ratio is a compromise to alleviate the large increase in per-unit
interconnect resistance and to prevent cross talk.8
Effectively, the increase means that in future CMOS devices
in general, and DRAMs in particular, it will be much harder
to make good, low-resistance contacts. Furthermore, DRAMs
require the tightest metal pitch and the highest packing density. Therefore, most contact locations have no room for multiple contacts. All of these characteristics make present and
future CMOS RAMs especially vulnerable to open defects.

Failure and analysis

Figure 2 helps explain the undetected faults in address
decoders. It diagrams part of an embedded SRAM, showing
the matrix and the word-line and column decoders. The figure shows three SRAM cells, A, B, and C, for which the addresses (A7A0) are 00100 111; 00110 111; and 10110 111.
The SRAM address space is 8 bits wide (256 addresses) and
has a word size of 8 bits. Different bits of a word are not close
to each other, so there is no possibility of intraword coupling
faults. Address bits A7A3 decode the word lines, and the

28

other three bits select the column (or bit) line. In our experiment, Cell C failed conditionally, producing the following observed symptoms:

4. Write B (00110 111) with logic 0.

5. Read C: result is logic 0, which is wrong.
Observation: None of the address inputs A3, A4, or A5 have
changed; the failure occurs.
The read operation on cell C yields the wrong data value
only if certain address bits (A5, A4, and A3) remain unchanged between write and read operations to cell C. If any
of these bits changes, the read operation to cell C yields the
expected data value. Furthermore, the fault is completely
data independent. The failure does not write data into another cell; it seems to be a read-only error.
Analysis. From the failure symptoms and further tests,
we made the following observations:
1. All three cells have the same column address (111).
2. Cell C yields a read failure when address bits A5, A4,
and A3 remain unchanged.
3. The fault causes only the read failure in cell C, and writing in cell C does not affect the contents of other cells
in any manner.
4. The 6N march test algorithm, used in the SRAMs original testing, cannot detect the fault.
On the basis of the first observation, it appears that enabling cell B after accessing cell C somehow also enables
(or does not disable) cell C. The corresponding word line
controls cell C. Consider a situation in which an operation
enables word lines B and C. If a write operation writes data
complementary to the contents of cell C into cell B, it overwrites cell C as well. Hence, a subsequent read operation
on cell C results in a read failure.
The second observation shows that cell C is sensitive only
when address bits A5, A4, and A3 have not changed. In other words, not all cells in the column are capable of introducing a fault in cell C. The third observation strengthens
the implications of the first.
There are two possible explanations for all the symptoms
and subsequent observations: 1) Enabling cell Bs word line
enables cell Cs word line, or 2) enabling cell B does not dis-

IEEE DESIGN & TEST OF COMPUTERS

APRILJUNE 1997

111

111

able cell Cs word line. The

Bit line
Bit line
WL31
first possibility is very un- A7
likely. However, such an ocWL23
currence could result from a
Cell C
WL30
decoder design error or a
low-resistance bridging fault
WL22 10110
between the word lines of
A5
cells B and C. We can rule
out a decoder design error,
Cell B
WL14
since this would cause a
large number of devices to
WL06 00110
fail under the test condi- A4
Cell A
tions. The low-resistance
WL12
bridging fault explanation
also seems unlikely, since
WL04 00100
the fault would be bidirec- A3
tional. Moreover, such a deOpen defect
WL08
fect is a typical case of a
decoder fault mapped onto
WL00
the matrix coupling fault,
A6
Output
which would be detected by
A3
the 6N march test algorithm.
A4
Therefore, the second possi- Phix
bility is the likely cause.
A5
To understand that arguA7
ment, consider Figure 3,
which illustrates part of the
word-line address-decoding Figure 3. Word-line decoder, with RAM cells and the defective NAND gate.
logic and corresponding bit
lines. The figure does not
show the word-line drivers and input buffers. The word-line through that path. If a read/write operation disables the
decoder has a 5-bit address. The buffered address bits gen- word line through the faulty path (for example, by selecting
erate true and complement values. Address decoding re- cell B), it selects two cells at the same time. Therefore, a
quires the help of the four-input NAND gates. Subsequently, write operation to another selected cell also writes to cell
the three-input NOR gates decode the outputs of the NAND C. Now, a read operation to cell C, depending on the origgates with address bit A6. A periodic timing signal, phix, inal stored data value and new data value, results in deforms the third input to the NOR gates. The NOR gate out- tection of a fault. However, if an operation accesses cell A
after cell C, another parallel p-channel path in the faulty
puts are buffered to drive the word lines.
Lets assume for a moment that the NAND gate in cell Cs NAND gate can disable the corresponding word line, and
word-line decoder has an open defect: a p-channel transis- the fault will not become active.
Our analysis demonstrated that the transistor had a stucktor with A7 as its input is disconnected from VDD. Now, if we
repeat our earlier experiment, we easily see that we can pro- open fault caused by a missing source-to-VDD contact. A missduce the same results with the defect on cell C. In a decoder ing contact between source (or drain) diffusion and metal
consisting of NAND gates, all high logic inputs put n-chan- 1 is the most likely cause. Another possibility is an open denel transistors in conduction mode, hence enabling the par- fect in the metalization layer.
ticular word line.
For example, 1111 on A7, A5, A4, A3 and 0 on A6 select
Why tests fail. Why doesnt the popular and time-tested
the word line corresponding to cell C. However, the dis- 6N SRAM march test detect this fault? Figure 4 (next page)
abling on that particular path can occur through four paths illustrates the 6N algorithm. The first step initializes the RAM
(depending on the fan-in of the NAND gate). If one of the with logic 0. Next, March 1 reads the initialized value and
paths has an open defect in the transistors source or drain, writes logic 1 in each RAM cell in ascending address order.
the transistor cannot pull the word line high (disable it) The binary address following word line C (address 10110) is

29

RAM ADDRESS DECODERS

Address
0
1

Initialize

March 1

March 2
R(1),W(0),R(0)

R(0),W(1)

Wr(0)
Wr(0)

R(0),W(1)

R(1),W(0),R(0)
N1

Wr(0)

R(0),W(1)

R(1),W(0),R(0)

Figure 4. The 6N SRAM march test algorithm. The doubleheaded arrow indicates that the same operation is repeated
over the entire address space (0 N 1).

WL63

A10

WL62
A9

WL61
WL60

A8

A7
1
A6

WL03
WL02

meet this condition and so are not detected by march tests.

A march test may use any address order, as long as it accesses all addresses. For simplicity, we usually choose either an ascending or a descending address. In general,
however, no addressing sequence is likely to detect all open
defects in an address decoder. Furthermore, no linear test algorithm will detect such defects because they change the
address decoder into a faulty sequential circuit usually requiring a two-pattern test: fault sensitizing and evaluation.6
Thus, the basic assumption that under faulty conditions address decoders remain combinational is untrue. Such defects are generic to decoders implemented with static CMOS
logic gates. In decoders implemented with dynamic logic
(or NMOS), these faulty conditions may not arise.
RAM test algorithms other than march tests are also unlikely to detect these defects because they do not ensure a
two-pattern test sequence for all potential defects. For example, complex algorithms for neighborhood patternsensitive faults cannot ensure open-fault detection in
decoders. Arguably, a Galpat (galloping pattern) algorithm2
of complexity O(n2) will detect these defects. However, applying this algorithm even for moderate-size RAMs is impossible due to its excessively long test time. Instead,
companies are making significant efforts to reduce RAM matrix test costs by using parallel test techniques.9,10
Unfortunately, parallel techniques test for address decoder
faults less vigorously. As a result, RAM address decoder testing is becoming a quality and economics issue.

WL01
A5

WL00

Phix A11

Figure 5. A typical word-line address decoder. Shading

indicates faults the 6N algorithm cannot detect.

10111, which modifies the A3 bit, disabling word line C as in

a fault-free case (Figure 3). In other words, March 1 neither
activates nor detects the fault.
Similarly, March 2 does not detect the fault. March 2 proceeds in descending address order. After word line C activates, the next word-line address is 10101, which modifies
the A4 and A3 bits. As a result, word line C becomes disabled once again, and the fault goes undetected. A march
test (or a linear algorithm) can detect this type of fault only
if the next word-line address activates the fault in at least
one march direction. It must remain activated until a read
operation to the cell detects it. Then, depending on the original and overwritten data values, a march test can detect the
defect. However, most open defects in NAND gates do not

30

Proposed test procedure

March tests fail to detect only a subset of all open defects
in an address decoder. To determine which open defects
these are and devise a test only for them, we consider the
embedded-RAM row decoder shown in Figure 5. The decoder decodes a 6-bit address (A10A5) to 64 word lines.
Address bit A11 determines the selected quadrant, and periodic timing signal phix controls the timing of the word-line
decoder. Instead of four-input NAND gates, this decoder uses
32 five-input NAND gates, as well as 64 two-input NOR gates
to further decode the sixth bit (A5).
Generally, open defects in an address decoder occur either between or inside logic gates. Defects 1 and 2 in Figure
5 exemplify the intergate class. These defects cause a break
in an interconnect line. As a result, at least one RAM cell cannot be addressed and therefore appears to have a stuck-at
fault. In other words, intergate open defects do not cause sequential behavior, and march tests such as the 6N algorithm
detect their effects. However, intragate open defects (defects
3 and 4) are difficult to detect because they may influence
only a single transistor. Hence, they may result in sequential
behavior. If an intragate open defect disconnects all paths
between the output and VDD (or VSS), it effectively causes an

IEEE DESIGN & TEST OF COMPUTERS

output SA0 (or SA1) fault and is detected by the march test.
However, if it disconnects only one path between the output
and VDD (or VSS), it causes sequential behavior.
Lets assume that defect 3 causes a disconnection from
VSS of an n-channel transistor in a two-input NOR gate. There
is only one other n-channel transistor in parallel to the defective transistor. Therefore, either the ascending March 1
or the descending March 2 will detect the defect, depending
on which transistor is faulty. A condition of this detection is
that the inputs to the faulty gate must change in Gray code
mannerthat is, only one input should change at a time. In
this case, address bit A11 and the decoded A10A5 bits
should change in Gray code manner.
The situation becomes grave as the number of inputs to
a gate rises to three or more. Using the reasoning of the previous section, we can conclude that a march test does not
guarantee detection of all open defects in a logic gate with
three or more inputs. In this example, at least three open defects in each five-input NAND gate will escape detection (the
other two will be detected by descending or ascending
march elements). The decoders 32 NAND gates give rise to
at least 96 potentially undetected defects.
Supplementary test algorithm. Once we knew of all
likely fault detection escapes, we devised a test solution. We
appended a small loop to the 6N algorithm to detect the
hard-to-detect address decoder stuck-open faults. However,
this loop is specific to address decoders and is independent
of the 6N march test algorithm, so it can be added to any
other march or linear test algorithm.
Lets assume that m is the number of input bits of the wordline decoder, and the number of word lines is 2m. To test the
row-decoding logic, we can select any arbitrary column address for read and write operations. In the following algorithm,
we set the column address to 0. The least significant bit (in
Figure 5, bit A5) is a dont care and remains 0 during the test.
To test for the hard-to-detect opens, we must test the NAND
gates in the decoding logic sequentially. For each NAND gate,
the corresponding word line (remember that bit A5 is set to
0) writes a logic 0 to the selected cell (say D). Next, we change
the word-line address such that only one address bit changes
(say A6). This allows a particular p-channel transistor in the
NAND gate to disable that NAND gate. Then, we write a logic
1 to the new address location (say E). If the p-channel transistor has an open defect, cell D is still enabled and the write
operation to cell E can also overwrite the content of cell D. A
subsequent read operation to cell D will detect a read failure
and hence the open defect.
We repeat this procedure for all address bits to NAND
gates and for all NAND gates. For example, we apply the following test sequence for the five-input NAND gate (shaded)
containing defect 4 in Figure 5:

APRILJUNE 1997

Keep Y decoder address constant,

keep A5 = 0 and A11 (if available) = 0
Let A10A6 = 00000, Write(1);
A10A6 = 00001, Write(0);
A10A6 = 00000, Read(1);
A10A6 = 00010, Write(0);
A10A6 = 00000, Read(1);
A10A6 = 00100, Write(0);
A10A6 = 00000, Read(1);
A10A6 = 01000, Write(0);
A10A6 = 00000, Read(1);
A10A6 = 10000, Write(0);
A10A6 = 00000, Read(1);
In general, it is possible to develop an algorithm for a given
address decoder that can supplement any RAM test algorithm.
In the algorithmic description, the address values in the read
and write operations correspond to the binary code at the
word-line decoders input bits (A10A5). The following is an
algorithm for testing the address decoder in Figure 5:
Column_address = 0
For i = 0 to 2(m1) Do
Base_address = 2 i
Write 0 to Base_address
For j = 0 to M Do
Write_address = Base_address XORbinary 2j
Write 1 to Write_address
Read 0 from Base_address
End For
End For
This algorithm executes the inner loop m1 times for each
i and consists of one write and one read operation. The main
loop executes 2(m1) times and takes one extra write operation. This makes the algorithms total complexity (2m1)
2(m1) read or write operations.
To compare this algorithms complexity with that of the
6N algorithm, we consider a RAM with 6 bits devoted to column decoding and another 6 bits to word-line decoding.
The 6N algorithm performs 6 212 = 24,576 read or write operations. This algorithm performs only 11 25 = 352 read or
write operations. So the additional test complexity is less
than 2% that of the 6N test.
We can expect that similar open defects in the column
decoder and the block decoder (Z) also cause hard-todetect faults. We can analyze these decoders and devise
similar test algorithms for them.
Layout measures: DFT. Layout improvement is probably the simplest and most effective way to reduce the oc-

31

RAM ADDRESS DECODERS

VDD

D
VSS

(a)

(b)
Diffusion

Poly

Contact

Metal

Figure 6. Layout transformation for open-defect testability of a

four-input NAND gate: original (a) and modified layout (b).

WL63

A10

WL62
A9

WL61
WL60

A8

A7
WL03
A6

WL02
WL01
WL00

A5

Phix
A11

Figure 7. A row decoder with built-in fault tolerance against

hard-to-detect open defects.

currence of hard-to-detect open defects. Circuit layout greatly affects testability. By preventing hard-to-detect faults, simple layout modifications can ease test generation. For
example, placing multiple contacts at hard-to-detect defect
locations (parallel transistors) in the decoder will make
these locations robust against open defects. The literature
documents these layout techniques well.11,12 Future RAM decoder designs will require such layout techniques for two

32

reasons: 1) Manufacturers test decoder circuitry implicitly

by testing only the matrix. 2) They often test RAMs with
march algorithms that restrict decoder excitation so as to
cover the fault model in only a few operations.
Figure 6 shows the modification of a four-input NAND
gate. This transformation is similar to one proposed by Levitt
and Abraham.12 In the unmodified layout, an open at a contact can occur at any branch of a set of parallel transistors
or metal line. A simple test may not detect such an open defect, and all the parallel branches must be tested separately. We can assume that the probability of an open defect
due to a poor contact is greater than the probability of an
open defect due to a break in diffusion. Thus, the transformation results in a robust layout as well as simpler test generation for open defects. Although the transformed gates
area and delay may increase fractionally, the number of
hard-to-detect faults decreases drastically.12
Logical measures: fault tolerance. Layout techniques,
in principle, can reduce the occurrence of open defects in
sensitive decoder locations, but they cannot eliminate their
occurrence completely. Therefore, we propose using logical
measures to build fault tolerance into key decoder locations.
By fault tolerance we mean that the decoder as well as the
RAM functions correctly in spite of a defect. Together with
layout transformations, fault tolerance also enhances the
decoders robustness.
Figure 7 illustrates the concept of logical measures. This
diagram is the same as Figure 5 except for the shaded areas,
an inverter, and an additional net (the broken line). From
our earlier reasoning, we conclude that opens affecting only
single p-channel transistors in five-input NAND gates are hard
to detect. The p-channel network provides the disabling
paths to the word lines (since a particular word line is selected if and only if the corresponding NAND gates output
is logic 0). Therefore, we can add an extra p-channel transistor in each five-input NAND gate. This transistor provides
an alternative path for word-line disabling by disabling all
NAND gates before application of a new address. In other
words, the p-channel transistor selects no word line. We also
add a corresponding n-channel transistor to avoid logical
conflicts and effectively make the gate a six-input NAND
gate. The figure shows the modified NAND gates as shaded.
The inputs of these transistors are driven by the phix timing signal, which activates the word-line address. Effectively,
phix now controls the address decoders timing through address bits A10A6 instead of A5 and A11 (see Figure 4). The
decoder needs the extra inverter to invert the timing signal.
A decoder using five-input NOR gates instead of NAND gates
doesnt need the extra inverter.
Building in fault tolerance has not changed the decoders
logical function. We can optimize the design for correct tim-

IEEE DESIGN & TEST OF COMPUTERS

ing without sacrificing the gains achieved through logical

measures. Furthermore, logical modifications reduce the
shaded three-input NOR gates to two-input NOR gates.
ICS AND SYSTEMS ARE BECOMING increasingly complex
and RAM intensive. We cannot meet IC quality and system
reliability requirements without adequately testing RAMs.
RAM testing procedures must focus on likely manufacturing defects, using both testing and DFT strategies. Built-in
self-test is an efficient methodology for testing RAMs, often
implemented with march test algorithms. For improved effectiveness, these algorithms must take into account the
schematic characteristics of address decoders.

Manoj Sachdev is a scientific staff member in

the VLSI Design Automation and Test Group at
Philips Research Laboratories, Eindhoven, the
Netherlands. His responsibilities and research
interests include defect and fault modeling,
memory testing, and DFT techniques for analog and digital circuits. Previously, he was with SCL in India and
SGS-Thomson in Italy, working on various aspects of IC design. He
has written several technical papers for conferences and journals.
He holds 12 granted and pending patents in VLSI design and test.
Sachdev received his BE in electronics and communication engineering from the University of Roorkee, India, and his PhD from
Brunel University, UK. He is a senior member of the IEEE.

References
1. A.V. Ferris-Prabhu, Computation of the Critical Area in Semiconductor Yield Theory, Proc. European Conf. Electronic Design Automation, Publication 232, IEEE, Piscataway, N.J., 1984,
pp. 171-173.
2. A.J. van de Goor, Testing Semiconductor Memories, Theory and
Practice, John Wiley & Sons, New York, 1991.
3. R. Dekker, F. Beenker, and L. Thijssen, Fault Modeling and
Test Algorithm Development for Static Random Access Memories, Proc. IEEE Intl Test Conf., IEEE Computer Society Press,
Los Alamitos, Calif., 1988, pp. 343-352.
4. M. Sachdev and M. Verstraelen, Development of a Fault Model and Test Algorithms for Embedded DRAMs, Proc. IEEE Intl
Test Conf., IEEE CS Press, 1993, pp. 815-824.
5. S.M. Thatte and J.A. Abraham, Testing of Semiconductor Random Access Memories, Proc. Intl Conf. Fault-Tolerant Computing, 1977, IEEE CS Press, pp. 81-87.
6. S.K. Jain and V.D. Agrawal, Test Generation for MOS Circuits
Using D-Algorithm, Proc. 20th Design Automation Conf., IEEE
CS Press, 1983, pp. 65-70.
7. A.P. Jayasumana, Y.K. Malaiya, and R. Rajsuman, Design of
CMOS Circuits for Stuck-Open Fault Testability, IEEE J. SolidState Circuits, Vol. 26, No. 1, Jan. 1991, pp. 58-61.
8. The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1994, San Jose, Calif., pp. 94-99.
9. Y. Matasuda et al., A New Array Architecture for Parallel Testing in VLSI Memories, Proc. Intl Test Conf., IEEE CS Press, 1989,
pp. 322-326.
10. M. Sachdev, Reducing the CMOS RAM Test Complexity with
Voltage and IDDQ Testing, J. Electronic Testing: Theory and
Applications (JETTA), Vol. 6, No. 2, Apr. 1995, pp. 191-202.
11. S. Koeppe, Optimal Layout to Avoid CMOS Stuck-Open
Faults, Proc. 24th Design Automation Conf., IEEE CS Press,
1987, pp. 829-835.
12. M.E. Levitt and J.A. Abraham, Physical Design of Testable
VLSI: Techniques and Experiments, IEEE J. Solid-State Circuits,
Vol. 25, No. 2, Apr. 1990, pp. 474-481.

APRILJUNE 1997

Address questions or comments about this article to Manoj

Sachdev, WAY 41, Philips Research Laboratories, Prof. Holstlaan
4, 5656 AA Eindhoven, The Netherlands; sachdev@natlab.
research.philips.com.

ONLINE TEST

Academic Research and Industrial Needs:

How Do They Correlate?
The growing complexity of electronic systems has produced increasing reliability needs in various application
domains. This has created a corresponding demand for
viable online test solutions for use in chips, boards, and
systems.
A panel will meet this July at the IEEE Third International
Online Test Workshop in Aghia Pelaghia Headland,
Greece, to discuss these issues. This panel will provide an
informal forum to address todays industrial needs for online test solutions and to compare their overlap with the
ongoing research in online test in the academic domain.
Yervant Zorian, LogicVision, USA, will lead the discussions
with panel members T. Chakrabourty, Lucent Technologies,
USA; M. Nicolaidis, TIMA, France; Ravi Iyer, University of
Illinois, and T. Nanya, Tokyo Inst. of Technology, Japan.
Join us July 7, 1997, 18:10-19:30
Check time and room number at registration.
IEEE Third International On-Line Test Workshop
The workshop and IEEE Design & Test of Computers
coorganized the panel.

33