DIGITAL ELECTRONICS (331102)

PRACTICAL: 13

TO STUDY D FLIP FLOP

1.0 AIM :

 To study D flip flop

2.0 PRIOR CONCEPTS :

 Knowledge of working of AND, OR, NOT gate.

 Knowledge of working of NAND and Ex - OR gates.

 Difference between sequential circuit and combinational circuit.

 Working of R – S flip flop.

3.0 INTRODUCTION

 It is possible to create a latch which has no race condition, simply by providing

only one input to a RS latch, and generating an inverted signal to present to the
other terminal of the latch.

 In this case, the S and R inputs are always inverted with respect to each other,
and no race condition can occur.

 A D flip-flop, also called a delay flip-flop.

 It can be used to provide temporary storage of one bit of information .

 It has only one input called DELAY

(D) input and the two outputs Q
and Q’.

 An RS-flipflop is rarely used in

actual sequential logic. However,
it is the fundamental building
block for the very useful D-flipflop.

 The D-flipflop has only a single data input. That data input is connected to the S
input of an RS-flip flop, while the inverse of D is connected to the R input.

 This prevents that the input combination ever occurs.

 To allow the flipflop to be in a holding state, a D-flip flop has a second input
called ``Enable.''

52 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
 DIGITAL ELECTRONICS (331102)

 The Enable-input is AND-ed with the D-input, such that when Enable=0, the R
and S inputs of the RS-flipflop are 0 and the state is held.

 When the Enable-input is 1, the S input of the RS flipflop equals the D input and
R is the inverse of D. Hence, the value of D determines the value of the output Q
when Enable is 1.

 When Enable returns to 0, the most recent input D is ``remembered.''

 The two asynchronous inputs, PRESET and CLEAR enable the flip-flop to be set to
a predetermined state, independent of the CLOCK.

 Note the invert bubble on these lines which indicates that these lines are normally
held at 1 and that the function (CLEAR or PRESET) is performed by taking the line
to 0.

4.0 WORKING OF D – FLIP FLOP :

 The delay flip-flop

transfers whatever is at
the external input D to
the output Q.

 This does not happen

immediately however
and only happens on an
rising clock pulse (i.e. as
CLK goes from 0 to 1).

 The input is thus delayed

by up to a clock pulse before appearing at the output. This is illustrated in the
timing diagram below.

 The DFF is an edge-triggered

device which means that the change of
state occurs on a clock transition (in this
case the rising clock pulse as it goes from
0 to 1).

 The delay flip-flop can also be configured

from a JK flip-flop where the input
connected to J and the complement of
the input is connected to K.

 A D flip-flop should not be confused with

a D latch.

 In a D flip-flop, the data on the D input

53 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
 DIGITAL ELECTRONICS (331102)

are transferred to the Q output on the positive- or negative-going transition of

the clock signal, depending upon the flip-flop, and this logic state is held at the
output until we get the next effective clock transition.

5.0 EXERCISE :

5.1 What is D flip flop?

Ans :

5.2 Why race condition doesnot occur in D flip flop?

Ans :

5.3 Show how S R flip flop can be converted into D flip flop.

Ans :

54 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
 DIGITAL ELECTRONICS (331102)

6.0 ASSIGNMENT :

6.1 Differentiate between a D flip-flop and a D latch.

6.2 What is advantage of D flip flop over R S flip flop.
6.3 Explain the function of D flip flop using a suitable diagram and discuss how
it works as a latch.

Grades for Exercise: .................................................

Grades for Assignment: .................................................

Signature of Lab Co-ordinators: .................................................

55 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))