Circuit & Electronics PDF

6.
002
CIRCUITS AND
ELECTRONICS
Introduction and Lumped Circuit Abstraction
6.002 Fall 2000
Lecture 1
ADMINISTRIVIA
Lecturer: Prof. Anant Agarwal

Textbook: Agarwal and Lang (A&L)
Readings are important!

Handout no. 3
Assignments
Homework exercises
Labs
Quizzes
Final exam
6.002 Fall 2000
Lecture 1
Two homework assignments can

be missed (except HW11).
Collaboration policy
Homework
You may collaborate with
others, but do your own
write-up.
Lab
You may work in a team of
two, but do you own write-up.
Info handout
Reading for today
Chapter 1 of the book
6.002 Fall 2000
Lecture 1
What is engineering?
Purposeful use of science
What is 6.002 about?

Gainful employment of
Maxwells equations
From electrons to digital gates
and op-amps
6.002 Fall 2000
Lecture 1
Nature as observed in experiments

V
12
0.1
0.2
0.3
0.4
6.002
Physics laws or abstractions

Maxwells
abstraction for
Ohms
tables of data
V=RI
Lumped circuit abstraction
+
V
C
L
R
Simple amplifier abstraction

Operational
amplifier abstraction
abstraction
+
-
Filters
Analog system
components:
Modulators,
oscillators,
RF amps,
power supplies 6.061
Digital abstraction
Combinational logic
Clocked digital abstraction

Instruction set abstraction
Pentium, MIPS 6.004
Programming languages
Java, C++, Matlab 6.001
Software systems 6.033
Operating systems, Browsers
Mice, toasters, sonar, stereos, doom, space shuttle

6.455
6.170
5
6.002 Fall 2000

Lecture 1
Lumped Circuit Abstraction
Consider
The Big Jump

from physics
to EECS
I
Suppose we wish to answer this question:

What is the current through the bulb?
6.002 Fall 2000
Lecture 1
We could do it the Hard Way

Apply Maxwells
Differential form
B
Faradays
E =
t
Continuity J =
t
Others
E =
0
6.002 Fall 2000
Lecture 1
Integral form
B
E dl = t
q
J dS = t
q
E
dS
=
Instead, there is an Easy Way
First, let us build some insight:

Analogy
F
a?
I ask you: What is the acceleration?

You quickly ask me: What is the mass?
I tell you:
F
You respond: a =
m
Done !! !
6.002 Fall 2000
Lecture 1
Instead, there is an Easy Way
First, let us build some insight:

Analogy
F
a?
In doing so, you ignored
the objects shape
its temperature
its color
point of force application
Point-mass discretization
6.002 Fall 2000
Lecture 1
The Easy Way
Consider the filament of the light bulb.

A
B
We do not care about
how current flows inside the filament
its temperature, shape, orientation, etc.
Then, we can replace the bulb with a
discrete resistor
for the purpose of calculating the current.
6.002 Fall 2000
Lecture 1
10
The Easy Way
A
B
Replace the bulb with a
discrete resistor
for the purpose of calculating the current.

A
+
V
I
R
and
V
I=
R
In EE, we do things
the easy way
R represents the only property of interest!

Like with point-mass: replace objects
F
with their mass m to find a =
m
6.002 Fall 2000
Lecture 1
11
The Easy Way
A
+
V
and
I=
In EE, we do things
the easy way
R represents the only property of interest!
R relates element v and i
I=
R
called element v-i relationship
6.002 Fall 2000
Lecture 1
12
R is a lumped element abstraction

for the bulb.
6.002 Fall 2000
Lecture 1
13
R is a lumped element abstraction

for the bulb.
Not so fast, though
I
A
+ S
A
V
B
SB
black box
Although we will take the easy way
using lumped abstractions for the rest
of this course, we must make sure (at
least the first time) that our
abstraction is reasonable. In this case,
ensuring that
V I
are defined
for the element
6.002 Fall 2000
Lecture 1
14
I
SA
V
B
must be defined
for the element
SB
black box
6.002 Fall 2000
Lecture 1
15
must be defined. True when
=
I out of S B
q
True only when
= 0 in the filament!
t
I into S A
J dS
SA
J dS
SB
q
J dS J dS = t
SA
SB
from ell
w
x
a
M
IA
IB
q
=0
I A = I B only if
t
So lets assume this
6.002 Fall 2000
Lecture 1
16
Must also be defined.
see
A&L
So lets assume this too
B
=0
t
outside elements
VAB defined when
So
VAB = AB E dl
6.002 Fall 2000
Lecture 1
17
Lumped Matter Discipline (LMD)

Or self imposed constraints:
More in
Chapter 1
of A & L
B
= 0 outside
t
q
= 0 inside elements
t
bulb, wire, battery
Lumped circuit abstraction applies when

elements adhere to the lumped matter
discipline.
6.002 Fall 2000
Lecture 1
18
Demo
only for the
sorts of
questions we
as EEs would
like to ask!
Demo
6.002 Fall 2000
Lumped element examples

whose behavior is completely
captured by their VI
relationship.
Exploding resistor demo

cant predict that!
Pickle demo
cant predict light, smell
Lecture 1
19
So, what does this buy us?
Replace the differential equations

with simple algebra using lumped
circuit abstraction (LCA).
For example
V
+
a
b
R1
R2
R3
R4
d
R5
What can we say about voltages in a loop

under the lumped matter discipline?
6.002 Fall 2000
Lecture 1
20
What can we say about voltages in a loop

under LMD?
a
b
V
+
R1
R3
R4
R2
R5
c
B
under DMD
E dl = t
0
E dl + E dl + E dl = 0
ca
ab
bc
+ Vca + Vab + Vbc
= 0
Kirchhoffs Voltage Law (KVL):

The sum of the voltages in a loop is 0.
6.002 Fall 2000
Lecture 1
21
What can we say about currents?
Consider
I ca
S
a
I da
I ba
6.002 Fall 2000
Lecture 1
22
What can we say about currents?
I ca
S
a
I
da
I ba
q
S J dS = t
under LMD
0
I ca + I da + I ba = 0
Kirchhoffs Current Law (KCL):
The sum of the currents into a node is 0.
simply conservation of charge
6.002 Fall 2000
Lecture 1
23
KVL and KCL Summary
KVL:
j j = 0
loop
KCL:
jij = 0
node
6.002 Fall 2000
Lecture 1
24
6.002
CIRCUITS AND
ELECTRONICS
Basic Circuit Analysis Method

(KVL and KCL method)
6.002 Fall 2000
Lecture 2
Review
Lumped Matter Discipline LMD:
Constraints we impose on ourselves to simplify

our analysis
B
=0
t
q
=0
t
Outside elements
Inside elements
wires resistors sources
Allows us to create the lumped circuit

abstraction
6.002 Fall 2000
Lecture 2
Review
LMD allows us to create the

lumped circuit abstraction
i
Lumped circuit element
power consumed by element = vi
6.002 Fall 2000
Lecture 2
Review
Review
Maxwells equations simplify to
algebraic KVL and KCL under LMD!
KVL:
j j = 0
loop
KCL:
jij = 0
node
6.002 Fall 2000
Lecture 2
Review
a
R1
R4
R3
R2
d
R5
DEMO
6.002 Fall 2000
vca + vab + vbc = 0
KVL
ica + ida + iba = 0
KCL
Lecture 2
Method 1: Basic KVL, KCL method of

Circuit analysis
Goal: Find all element vs and is
1. write element v-i relationships
(from lumped circuit abstraction)
2. write KCL for all nodes
3. write KVL for all loops
lots of unknowns
lots of equations
lots of fun
solve
6.002 Fall 2000
Lecture 2
Method 1: Basic KVL, KCL method of

Circuit analysis
Element Relationships
For R,
V = IR
For voltage source, V = V0
R
+
V0
For current source, I = I 0
J
Io
3 lumped circuit elements
6.002 Fall 2000
Lecture 2
KVL, KCL Example

a
+
1
+
0 = V0
R1
R3
+ 3
R2
R4
d
+
R5
c
The Demo Circuit
6.002 Fall 2000
Lecture 2
Associated variables discipline

i
Element e
Current is taken to be positive going

into the positive voltage terminal
Then power consumed

by element e
6.002 Fall 2000
Lecture 2
= i is positive
KVL, KCL Example

a
+
0 = V0
i0
L1
i4
i1 L 2
+
R1
4 R4
R3
b i3
d
+ 3
i2
i5
+
R2
5 R5
L3
c
The Demo Circuit
6.002 Fall 2000
Lecture 2
L4
10
Analyze
0 5 ,0 5
1. Element relationships (v, i )
given v3 = i3 R3
v0 = V0
v4 = i4 R4
v1 = i1 R1
v5 = i5 R5
v2 = i2 R2
12 unknowns
6 equations
2. KCL at the nodes

a: i0 + i1 + i4 = 0
3 independent
b: i2 + i3 i1 = 0
equations
d: i5 i3 i4 = 0
e: i0 i2 i5 = 0 redundant
3. KVL for loops
L1: v0 + v1 + v2 = 0
3 independent
equations
L2: v1 + v3 v4 = 0
L3: v3 + v5 v2 = 0
s
L4: v0 + v4 + v5 = 0 redundant
n
o
i
t
ns
a
w
u
o
n
k
eq
n
u
1 2 12
ugh @#!
6.002 Fall 2000
Lecture 2
11
Other Analysis Methods

Method 2 Apply element combination rules
A
B
R1
R2 R3
G1
G2
V1
V2
GN
R1 + R2 +
G1 + G2
1
Gi =
Ri
+ RN
+ GN
V1 + V2
+
I2
I1
RN
I1 + I 2
Surprisingly, these rules (along with superposition, which

you will learn about later) can solve the circuit on page 8
6.002 Fall 2000
Lecture 2
12
Other Analysis Methods

Method 2 Apply element combination rules
I =?
Example
R1
V +
R3
R2
I
V +
R1
R2 R3
R2 + R3
V +
R = R1 +
R
R2 R3
R2 + R3
V
I=
R
6.002 Fall 2000
Lecture 2
13
Method 3Node analysis

Particular application of KVL, KCL method
1. Select reference node ( ground)
from which voltages are measured.
2. Label voltages of remaining nodes
with respect to ground.
These are the primary unknowns.
3. Write KCL for all but the ground
node, substituting device laws and
KVL.
4. Solve for node voltages.
5. Back solve for branch voltages and
currents (i.e., the secondary unknowns)
6.002 Fall 2000
Lecture 2
14
Example: Old Faithful

plus current source
V0
Step 1
6.002 Fall 2000
e2
R2
R5
+ V e1
0
R4
R1 R
3
I1
Step 2
Lecture 2
15

plus current source
V0
R2
R4
e2
R5
+ V e1
0
R1 R
3
for
I1 convenience,
write
1
Gi =
Ri
KCL at e1
(e1 V0 )G1 + (e1 e2 )G3 + (e1 )G2 = 0
KCL at e2
(e2 e1 )G3 + (e2 V0 )G4 + (e2 )G5 I1 = 0
Step 3
6.002 Fall 2000
Lecture 2
16

plus current source
V0
e2
R2
R5
+ V e1
0
R4
R1 R
3
I1
Gi =
KCL at e1
(e1 V0 )G1 + (e1 e2 )G3 + (e1 )G2 = 0
1
Ri
KCL at l2
(e2 e1 )G3 + (e2 V0 )G4 + (e2 )G5 I1 = 0
move constant terms to RHS & collect unknowns
e1 (G1 + G2 + G3 ) + e2 (G3 ) = V0 (G1 )

e1 (G3 ) + e2 (G3 + G4 + G5 ) = V0 (G4 ) + I1
2 equations, 2 unknowns
(compare units)
6.002 Fall 2000
Lecture 2
Solve for es
Step 4
17
In matrix form:
G1 + G2 + G3
G3
G3
e1
G1V0
=
G V + I
G3 + G4 + G5 e2
4 0 1
conductivity
matrix
sources
unknown
node
voltages
Solve
G3
G3 + G4 + G5
G1V0
G3
G1 + G2 + G3 G4V0 + I1
e1
e =
(G1 + G2 + G3 )(G3 + G4 + G5 ) G3 2
2
)(
) ( )(
G +G +G G V + G G V + I
3
4
5 1 0
3 4 0 1
e =
1 G G +G G +G G +G G +G G +G G +G 2 +G G +G G
1 3
1 4
1 5
2 3
2 4
2 5
3
3 4
3 5
e2 =
(G3 )(G1V0 ) + (G1 + G2 + G3 )(G4V0 + I 1 )

2
G1G3 + G1G4 + G1G5 + G2G3 + G2G4 + G2 G5 + G3 + G3G4 + G3G5
(same denominator)
Notice: linear in V0 , I1 , no negatives

in denominator
6.002 Fall 2000
Lecture 2
18
Solve, given
G1
1
=
G5 8.2 K
G2
1
=
G4 3.9 K
1
G3 =
1.5 K
I1 = 0
)(
G G V + G +G +G G V + I
e = 3 10 1 2 3 40 1
2 G + G + G + G + G + G G 2
1 2 3
3 4 5 3
1
1
1
G +G +G =
+
+
=1
1
2
3 8.2 3.9 1.5
G3 + G4 + G5 =
)(
1
1
1
+
+
=1
1.5 3.9 8.2
1
1
1
+ 1
3.9 V
e2 = 8.2 1.5
0
1
1 2
1.5
Check out the

DEMO
e2 = 0.6V0
If V0 = 3V , then e2 = 1.8V0
6.002 Fall 2000
Lecture 2
19
6.002
CIRCUITS AND
ELECTRONICS
Superposition, Thvenin and Norton
6.002 Fall 2000
Lecture 3
Review
Circuit Analysis Methods
z KVL:
Vi = 0
loop
KCL:
Ii = 0
VI
node
z Circuit composition rules

z Node method the workhorse of 6.002
KCL at nodes using V s referenced

from ground
(KVL implicit in (ei e j ) G )
6.002 Fall 2000
Lecture 3
Linearity
R2
e
J
R1
Consider
Write node equations
e V e
+ I =0
R1
R2
Notice:
linear in e,V , I
No eV ,VI
terms
6.002 Fall 2000
Lecture 3
Linearity
R1
Consider
+
R2
Write node equations -e V e

+ I =0
R1
R2
Rearrange -1
1
R + R e
1
2
conductance
matrix
6.002 Fall 2000
linear in e,V , I
V
+ I
R1
node
linear sum
voltages of sources
Lecture 3
Linearity
Write node equations -e V e
+ I =0
R1
R2
Rearrange -1
1
R + R e
1
2
conductance
matrix
G
or
e=
linear in e,V , I
V
+ I
R1
node
linear sum
voltages of sources
R2
RR
V+ 1 2 I
R1 + R2
R1 + R2
e = a1V1 + a2V2 + + b1 I1 + b2 I 2 +
Linear!
6.002 Fall 2000
Lecture 3
Linearity
6.002 Fall 2000
Homogeneity
Superposition
Lecture 3
Linearity
Homogeneity
Superposition
Homogeneity
x1
x2 .
.
x1
x2 ..
.
6.002 Fall 2000
Lecture 3
Linearity
Homogeneity
Superposition
Superposition
x1a
x2 a .
..
ya
x1b
x2 b .
..
yb
x1a + x1b
x2 a + x2 b .
..
6.002 Fall 2000
y a + yb
Lecture 3
Linearity
Homogeneity
Superposition
Specific superposition example:

V1
0
0
V2
y1
y2
V1 + 0
0 + V2
6.002 Fall 2000
y1 + y2
Lecture 3
Method 4: Superposition method

The output of a circuit is
determined by summing the
responses to each source
acting alone.
s
e
c
r
u
so
t
n
e
nd
e
p
e
ind
only
6.002 Fall 2000
Lecture 3
10
V =0 +
i
+
v
+
v
short
I =0
i
+
v
+
v
open
6.002 Fall 2000
Lecture 3
11
Back to the example

Use superposition method
6.002 Fall 2000
R2
Lecture 3
R1
12
Back to the example

Use superposition method
V acting alone
R1
I = 0 eV =
R2
I acting alone
V =0
sum
R1
R2
R2
V
R1 + R2
R1 R2
eI =
I
R1 + R2
superposition
R2
R1 R2
e = eV + eI =
V+
I
R1 + R2
R1 + R2
6.002 Fall 2000
Lecture 3
Voil !
13
Demo
salt
water
constant
+
output shows
superposition
sinusoid
6.002 Fall 2000
Lecture 3
14
Yet another method
Consider
By superposition
v =
mVm + n I n + Ri
m
no
resistance
units
units
By setting
n I n = 0, mVm = 0,
i = 0
i = 0
+
v
-
y network
r
a
r
t
i
N
Arb
resistors
Vm
In
+
also
independent
of external
excitement &
behaves like
a resistor
All
n I n = 0,
mVm = 0
independent of external
excitation and behaves like a
voltage vTH
6.002 Fall 2000
Lecture 3
15
Or
v = vTH + RTH i
As far as the external world is concerned

(for the purpose of I-V relation),
Arbitrary network N is indistinguishable
from:
RTH
Thvenin
equivalent
network
vTH
RTH
+ vTH
+
v
open circuit voltage

at terminal pair (a.k.a. port)
resistance of network seen
from port
( Vm s, I n s set to 0)
6.002 Fall 2000
Lecture 3
16
Method 4:
The Thvenin Method
J
+
v
-
Thvenin equivalent
RTH
+ vTH
i
+
v
Replace network N with its Thvenin

equivalent, then solve external network E.
6.002 Fall 2000
Lecture 3
17
Example:
+
V
R2
i1 R1
i1 R1
RTH
+
V
VTH
i1 =
6.002 Fall 2000
+ I
V VTH
R1 + RTH
Lecture 3
18
VTH :
VTH = IR2
RTH :
RTH = R2
6.002 Fall 2000
+
VTH
-
R2
+
RTH
-
R2
Lecture 3
Example:
19
Graphically,
v = vTH + RTH i
i
1
RTH
v
vTH
V
OC
I SC
Open circuit
(i 0)
v = vTH
Short circuit
(v 0)
vTH
i =
RTH
6.002 Fall 2000
Lecture 3
VOC
I SC
20
in recitation,
see text
Method 5:
The Norton Method
J
+
+
v
-
IN
RTH = RN
Norton
equivalent
IN =
6.002 Fall 2000
Lecture 3
VTH
RTH
21
Summary
Discretize matter
LMD
Physics
LCA
EE
R, I, V
Linear networks
Analysis methods (linear)

KVL, KCL, I V
Combination rules
Node method
Superposition
Thvenin
Norton
Next
Nonlinear analysis
Discretize voltage
6.002 Fall 2000
Lecture 3
101100
22
6.002
CIRCUITS AND
ELECTRONICS
The Digital Abstraction
6.002 Fall 2000
Lecture 4
Review
z Discretize matter by agreeing to
observe the lumped matter discipline
Lumped Circuit Abstraction

zAnalysis tool kit: KVL/KCL, node method,
superposition, Thvenin, Norton
(remember superposition, Thvenin,
Norton apply only for linear circuits)
6.002 Fall 2000
Lecture 4
Today
Discretize value
Digital abstraction
Interestingly, we will see shortly that the

tools learned in the previous three
lectures are sufficient to analyze simple
digital circuits
Reading: Chapter 5 of Agarwal & Lang
6.002 Fall 2000
Lecture 4
But first, why digital?

In the past
Analog signal processing
R1
V0
R2
V1 +
V1
and V2
might represent the
outputs of two
sensors, for example.
V2
By superposition,
V0 =
R2
R1
V1 +
V2
R1 + R2
R1 + R2
If R1 = R 2 ,
V0 =
V1 + V2
2
The above is an adder circuit.

6.002 Fall 2000
Lecture 4
Noise Problem
t
add noise on
this wire
Receiver:
huh?
noise hampers our ability to distinguish

between small differences in value
e.g. between 3.1V and 3.2V.
6.002 Fall 2000
Lecture 4
Value Discretization
Restrict values to be one of two
HIGH
LOW
5V
0V
TRUE
FALSE
like two digits
0 and 1
Why is this discretization useful?

(Remember, numbers larger than 1 can be
represented using multiple binary digits and
coding, much like using multiple decimal digits to
represent numbers greater than 9. E.g., the
binary number 101 has decimal value 5.)
6.002 Fall 2000
Lecture 4
Digital System
sender
noise
VN
VS
VR
VN = 0V
receiver
VS
VR
5V 0 1 0 HIGH
0 1 0
5V
2.5V
0V
LOW
0V
2.5V
With noise
VS
VN = 0.2V
0 1 0
5V
0 1 0
0.2V
2.5V
VS
2.5V
0V
6.002 Fall 2000
Lecture 4
Digital System
Better noise immunity

Lots of noise margin
For 1: noise margin 5V to 2.5V = 2.5V
For 0: noise margin 0V to 2.5V = 2.5V
6.002 Fall 2000
Lecture 4
Voltage Thresholds
and Logic Values
5V
sender
0
1
2.5V receiver
0
0V
6.002 Fall 2000
Lecture 4
But, but, but

What about 2.5V?
Hmmm create no mans land
or forbidden region
For example,
5V
1
sender
3V
2V
VH
forbidden
region
receiver
VL
0V
0V
6.002 Fall 2000
Lecture 4
5V
V
L
10
But, but, but
Wheres the noise margin?

What if the sender sent 1:
VH ?
Hold the sender to tougher standards!

5V
1
V
0H
1
V
IH
sender
V
IL
receiver
0
V
0L
0V
6.002 Fall 2000
Lecture 4
11
But, but, but
Wheres the noise margin?

What if the sender sent 1:
VH ?
Hold the sender to tougher standards!

5V
1
V
0H
sender
Noise margins
V
IH
receiver
V
IL
V
0L
0V
1 noise margin: V
- V
0 noise margin:
6.002 Fall 2000
Lecture 4
IH
V
IL
0H
V
0L
12
5V
V
0H
V
IH
V
IL
V
0L
0V
5V
V
0H
V
IH
V
IL
V
0L
0V
sender
receiver
Digital systems follow static discipline: if

inputs to the digital system meet valid input
thresholds, then the system guarantees its
outputs will meet valid output thresholds.
6.002 Fall 2000
Lecture 4
13
Processing digital signals

Recall, we have only two values
1,0
Map naturally to logic: T, F

Can also represent numbers
6.002 Fall 2000
Lecture 4
14
Processing digital signals

Boolean Logic
If X is true and Y is true
Then Z is true else Z is false.
Z = X AND Y
X, Y, Z
are digital signals
0 , 1
Z = X Y
Boolean equation
X
Y
AND gate
Truth table representation:

X Y Z
0
0
1
1
0
1
0
1
0
0
0
1
Enumerate all input combinations

6.002 Fall 2000
Lecture 4
15
Combinational gate
abstraction
Adheres to static discipline
Outputs are a function of
inputs alone.
Digital logic designers do not

have to care about what is
inside a gate.
6.002 Fall 2000
Lecture 4
16
Demo
Z
Noise
X
Y
Z = X Y
6.002 Fall 2000
Lecture 4
17
Examples for recitation

X
t
Y
t
Z
t
Z = X Y
6.002 Fall 2000
Lecture 4
18
In recitation
Another example of a gate
If (A is true) OR (B is true)
then C is true
else C is false
C = A + B
A
B
Boolean equation
OR
C
OR gate
More gates
B
B
Inverter
X
Y
Z
NAND
Z = X Y
6.002 Fall 2000
Lecture 4
19
Boolean Identities
X
X
X
X
1 = X
0 = X
+ 1 = 1
+0 = X
1 = 0
0 = 1
AB + AC = A (B + C)
Digital Circuits
Implement:
B
C
output = A + B C
BC
output
6.002 Fall 2000
Lecture 4
20
6.002
CIRCUITS AND
ELECTRONICS
Inside the Digital Gate
6.002 Fall 2000
Lecture 5
Review
The Digital Abstraction
z Discretize value 0, 1
z Static discipline
meet voltage thresholds

sender
VOH
VOL
receiver
VIH
VIL
forbidden
region
Specifies how gates must be designed
6.002 Fall 2000
Lecture 5
Review
Combinational gate abstraction
outputs function of input alone
satisfies static discipline
A
B
C
NAND
6.002 Fall 2000
Lecture 5
A
0
0
1
1
B
0
1
0
1
C
1
1
1
0
For example:
a digital circuit
A
B
Demo
A B
D
C
D = (C (A B ))
3 gates here
A Pentium III class microprocessor

is a circuit with over 4 million gates !!
The RAW chip
being built at the
Lab for Computer Science at MIT
has about 3 million gates.
6.002 Fall 2000
Lecture 5
How to build a digital gate

Analogy
l ik e
power
supply
(li
taps
s)
e
h
c
t
i
ke sw
B
C
if A=ON AND B=ON

C has H20
else
C has no H20
Use this insight to build an AND gate.
6.002 Fall 2000
Lecture 5
How to build a digital gate
OR gate
A
C
B
6.002 Fall 2000
Lecture 5
Electrical Analogy
B
V +
Bulb C is ON if A AND B are ON,

else C is off
Key: switch device
6.002 Fall 2000
Lecture 5
Electrical Analogy
equivalent ckt
Key: switch device
in
control
C =0
in
out
in
out
C=1
3-Terminal device
if C = 0
else
out
short circuit between in and out

open circuit between in and out
For mechanical switch,

control
mechanical pressure
6.002 Fall 2000
Lecture 5
Consider
RL
VOUT
IN
+ VS
VS =
OUT
VS
RL
VOUT
C
VS
VOUT
C =0
Truth table for

C VOUT
0 1
1 0
VS
VOUT
C =1
6.002 Fall 2000
Lecture 5
What about?
VS
Truth table for

c1 c2 VO
0 0 1
0 1 1
1 0 1
1 1 0
VOUT
c1
c2
Truth table for
VS
VOUT
c1
6.002 Fall 2000
c2
Lecture 5
c1 c2 VO
0 0 1
0 1 0
1 0 0
1 1 0
10
What about?
can also build compound gates
VS
D
A
D = (A B) + C
6.002 Fall 2000
Lecture 5
11
The MOSFET Device

Metal-Oxide
Semiconductor
Field-Effect
Transistor
drain
D
G
gate
S
source
3 terminal lumped element

behaves like a switch
G : control terminal
D, S : behave in a symmetric
manner (for our needs)
6.002 Fall 2000
Lecture 5
12
The MOSFET Device

Understand its operation by viewing it
as a two-port element
out k
k
c
e
Ch extboo l
the t s interna
for it ture.
iG
c
u
r
t
s
+
vGS
iDS
vDS
S
D
off
G
vGS < VT
G
vGS VT
D
iDS
on
S
VT 1V typically
Switch model (S model) of the MOSFET
6.002 Fall 2000
Lecture 5
13
Demo
Check the MOS device

on a scope.
i
DS
+
vDS
+
vGS
iDS
vGS VT
vGS < VT
iDS vs vDS
6.002 Fall 2000
Lecture 5
vDS
14
A MOSFET Inverter
VS = 5V
RL
vOUT
IN
Note the power of abstraction.

The abstract inverter gate representation
hides the internal details such as power
supply connections, RL, GND, etc.
(When we build digital circuits, the
and
are common across all gates!)
6.002 Fall 2000
Lecture 5
15
Example
vOUT
5V
vOUT
vIN
0V V
T =1V
5V
v IN
The T1000 model laptop desires gates that satisfy

the static discipline with voltage thresholds. Does
out inverter qualify?
1:
0:
VOL = 0.5V
VIL = 0.9V
VOH = 4.5V
VIH = 4.1V
sender
5
4.5 V
OH
0.5
0
VOL
receiver
5
4.1
0.9
0
Our inverter satisfies this.
6.002 Fall 2000
Lecture 5
1
VIH
VIL
16
E.g.:
Does our inverter satisfy the static
discipline for these thresholds:
VOL = 0.2V
VIL = 0.5V
VOH = 4.8V
VIH = 4.5V
yes
x
VOL = 0.5V
VIL = 1.5V
VOH = 4.5V
VIH = 3.5V
6.002 Fall 2000
Lecture 5
no
17
Switch resistor (SR) model

of MOSFET
more accurate MOS model
D
D
G
G
S
vGS < VT
RON
vGS VT S
e.g. RON = 5 K
6.002 Fall 2000
Lecture 5
18
SR Model of MOSFET
D
D
G
G
S
vGS < VT
MOSFET
S model
iDS
vGS VT
RON
vGS VT S
MOSFET
SR model
vGS VT
iDS
vGS < VT
1
RON
vGS < VT
vDS
6.002 Fall 2000
vDS
Lecture 5
19
Using the SR model

RL
vOUT
IN
+ VS
VS =
OUT
VS
RL
vOUT
C
Truth table for
VS
RL
vOUT
C VOUT
0 1
1 0
RON
C =0
VS
RL
C =1
vGS VT
vOUT
RON
6.002 Fall 2000
Choose RL, RON, VS such that:

V R
v
= S ON V
OL
OUT R
+R
L
ON
Lecture 5
20
6.002
CIRCUITS AND
ELECTRONICS
Nonlinear Analysis
6.002 Fall 2000
Lecture 6
Review
Discretize matter t LCA
m1 X KVL, KCL, i-v
m2 X Composition rules
m3 X Node method
m4 X Superposition
m5 X Thvenin, Norton
6.002 Fall 2000
Lecture 6
any
circuit
linear
circuits
Review
Discretize value t Digital abstraction
X Subcircuits for given switch
setting are linear! So, all 5
methods (m1 m5) can be
applied
VS
VS
A =1
B =1
RL
RL
C
A
C
RON
RON
SR MOSFET Model
6.002 Fall 2000
Lecture 6
Today
Nonlinear Analysis
X Analytical method
based on m1, m2, m3
X Graphical method
X Introduction to incremental analysis
6.002 Fall 2000
Lecture 6
How do we analyze nonlinear

circuits, for example:
+
vD
-
Hypothetical
nonlinear
D
device
(Expo Dweeb )
iD
+ vD -
iD
iD
iD = aebvD
a
vD
0,0
(Curiously, the device supplies power when vD is negative)
6.002 Fall 2000
Lecture 6
Method 1: Analytical Method

Using the node method,
(remember the node method applies for linear or

nonlinear circuits)
vD V
+ iD = 0
R
iD = aebvD
2 unknowns
1
2
2 equations
Solve the equation by

trial and error
numerical methods
6.002 Fall 2000
Lecture 6
Method 2: Graphical Method

Notice: the solution satisfies equations
1 and 2
iD
iD = aebvD
a
vD
iD
V vD
1 iD =
R R
V
R
1
slope =
R
V
6.002 Fall 2000
Lecture 6
vD
Combine the two constraints

iD
V
1
R
~ 0 .4
a
called loadline
for reasons you
will see later
~ 0.5
e.g.
V =1
R =1
V
1
vD
vD = 0.5V
iD = 0.4 A
1
4
b =1
a=
6.002 Fall 2000
Lecture 6
Method 3: Incremental Analysis

Motivation: music over a light beam
Can we pull this off?
iD
+
vD LED
light
intensity
I D iD
vI music signal
vI (t ) +
iR
vI (t )
iD (t )
light
AMP
iR I R
light intensity IR
in photoreceiver
LED: Light
Emitting
expoDweep
iR (t )
sound
nonlinear
linear
problem! will result in distortion
6.002 Fall 2000
Lecture 6
Problem:
The LED is nonlinear
distortion
iD
iD
vD
vD = vI
t
vD
t
iD
6.002 Fall 2000
vD
Lecture 6
10
If only it were linear

iD
iD
vD
vD
t
it wouldve been ok.
What do we do?
Zen is the answer
next lecture!
6.002 Fall 2000
Lecture 6
11
6.002
CIRCUITS AND
ELECTRONICS
Incremental Analysis
6.002 Fall 2000
Lecture 7
Review
Nonlinear Analysis
X Analytical method
X Graphical method
Today
X Incremental analysis
Reading: Section 4.5
6.002 Fall 2000
Lecture 7
Method 3: Incremental Analysis

Motivation: music over a light beam
Can we pull this off?
iD
+
vD LED
light
intensity
I D iD
vI music signal
vI (t ) +
iR
vI (t )
iD (t )
light
AMP
iR I R
light intensity IR
in photoreceiver
LED: Light
Emitting
expoDweep
iR (t )
sound
nonlinear
linear
problem! will result in distortion
6.002 Fall 2000
Lecture 7
Problem:
The LED is nonlinear
distortion
iD
iD
vD
vD = vI
t
vD
t
iD
6.002 Fall 2000
vD
Lecture 7
Insight:
iD
small region
looks linear
(about VD , ID)
ID
VD
vD
DC offset
or DC bias
Trick:
vI
vi (t ) +
VI
iD = I D + id
+
vD LED
vD = VD + vd
VI
6.002 Fall 2000
Lecture 7
vi
5
Result
iD
id
ID
vD
VD
6.002 Fall 2000
Lecture 7
vd
very small
Result
vD = vI
vd
vD
VD
iD
id
iD
~linear!
ID
Demo
6.002 Fall 2000
Lecture 7
The incremental method:

(or small signal method)
1. Operate at some DC offset

or bias point VD, ID .
2. Superimpose small signal vd
(music) on top of VD .
3. Response id to small signal vd
is approximately linear.
Notation:
iD = I D + id
total
DC
small
variable offset superimposed
signal
6.002 Fall 2000
Lecture 7
What does this mean

mathematically?
Or, why is the small signal response
linear?
nonlinear
iD = f (vD )
We replaced
vD = VD + vD
large DC
vd
increment
about VD
using Taylors Expansion to expand

f(vD) near vD=VD :
iD = f (VD ) +
+
df (vD )
vD
dvD vD =VD
1 d 2 f (v D )
2! dvD 2 v
vD + "
D =VD
neglect higher order terms

because vD is small
6.002 Fall 2000
Lecture 7
iD f (VD ) +
constant
w.r.t. vD
d f (v D )
vD
d vD vD =VD
constant w.r.t. vD
slope at VD, ID
We can write
X : I D + iD f (VD ) +
d f (v D )
vD
d vD vD =VD
equating DC and time-varying parts,

I D = f (VD )
operating point
d f (v D )
iD =
vD
d vD vD =VD
constant w.r.t. vD
so, iD vD
6.002 Fall 2000
Lecture 7
By notation,
iD = id
v D = vd
10
In our example,
iD = a e
bv D
From X : I D + id a e bVD + a e bVD b vd

Equate DC and incremental terms,
I D = a ebVD
operating point
aka bias pt.
aka DC offset
id = a ebVD b vd
id = I D b vd
constant
6.002 Fall 2000
Lecture 7
small signal
behavior
linear!
11
Graphical interpretation
operating point
I D = a ebVD
id = I D b vd
A
slope at
VD, ID
iD
ID
id
VD
operating
point
vd
vD
we are
approximating
A with B
6.002 Fall 2000
Lecture 7
12
graphically
mathematically
now, circuit
We saw the small signal

Large signal circuit:
VI
ID
+
LED VD
-
I D = a ebVD
Small signal response: id = I D b vd

+ vd -
behaves like:
id
R=
small signal circuit:
vi
+
vd
-
1
ID b
id
1
I Db
Linear!
6.002 Fall 2000
Lecture 7
13
6.002
CIRCUITS AND
ELECTRONICS
Dependent Sources
and Amplifiers
6.002 Fall 2002: Lecture 8
Review
Nonlinear circuits can use the

node method
Small signal trick resulted in linear

response
Today
Dependent sources
Amplifiers
Reading: Chapter 7.1, 7.2
Dependent sources
Seen previously
Resistor
Independent
Current source
+
i
+
i
R
v
I
v
i=
R
i=I
2-terminal 1-port devices

New type of device: Dependent source
iI
i
O
+
control
port
f ( vI )
vI
vO
output
port
2-port device
E.g., Voltage Controlled Current Source
Current at output port is a function of voltage
at the input port
Dependent Sources: Examples
Example 1: Find V
+
R V
independent
current
source
I = I0
V = I0R

Example 2: Find V
+
R V
voltage
controled
current
source
+
R V
K
I = f (V ) =
V
iI
+
f (vI ) =
K
vI
iO
+
vI
vO

Example 2: Find V
voltage
controled
current
source
+
R V
K
I = f (V ) =
V
e.g. K = 10-3 AmpVolt
R = 1k
K
V = IR = R
V
or V 2 = KR
or V = KR
= 10 3 10 3
= 1 Volt
Another dependent source example
RL
iIN
vI +
iD
vIN
vO
e.g.
VS +
iD = f (vIN )
iD = f (vIN )
K
2
= (vIN 1) for vIN 1
2
iD = 0
otherwise
Find vO as a function of vI .

VS
RL
iIN
vI +
iD
vIN
vO
iD = f (vIN )
e.g.
iD = f (vIN )
K
2
= (vIN 1) for vIN 1
2
iD = 0
otherwise

VS
RL
vI
vI
vO
K
2
iD = (vIN 1) for vIN 1
2
iD = 0
otherwise

VS
RL
vI
vI
vO
K
2
2
iD = 0
otherwise
KVL
VS + iD RL + vO = 0
vO = VS iD RL
K
2
vO = VS (vI 1) RL
2
vO = VS
for vI 1
for vI < 1
Hold that thought
10
Next, Amplifiers
11
Why amplify?
Signal amplification key to both analog
and digital processing.
Analog:
AMP
IN
Input
Port
OUT
Output
Port
Besides the obvious advantages of being

heard farther away, amplification is key
to noise tolerance during communication
12
Why amplify?
Amplification is key to noise tolerance
during communication
No amplification
useful
signal
1 mV
e
nois
10 mV
huh?
13
Try amplification
e
nois
AMP
not bad!
14
Why amplify?
Digital:
Valid region
5V
5V
VIH IN
VIL
0V
5V
OUT
Digital System
IN
5V
VOL
OUT
V OH
VIH
VIL
0V
0V
VOH
V OL
0V
15
Why amplify?
Digital:
Static discipline requires amplification!

Minimum amplification needed:
VIH
VIL
VOH
VOL
VOH VOL
VIH VIL
16
An amplifier is a 3-ported device, actually

Power port
Input
port
iO
iI
+v
I
Amplifier
+ v Output
O port
We often dont show the power port.

Also, for convenience we commonly observe
the common ground discipline.
In other words, all ports often share a
common reference point called ground.
POWER
IN
OUT
How do we build one?

17
Remember?
VS
RL
vI
vI
vO
K
2
2
iD = 0
otherwise
KVL
VS + iD RL + vO = 0
vO = VS iD RL
K
2
vO = VS (vI 1) RL
2
vO = VS
for vI 1
for vI < 1
Claim: This is an amplifier
18
So, wheres the amplification?

Lets look at the vO versus vI curve.
mA
e.g. VS = 10V , K = 2 2 , RL = 5 k
V
K
2
vO = VS RL (vI 1)
2
2
2
= 10 10 3 5 103 (vI 1)
2
vO = 10 5 (vI 1)
vO
VS
vO
vO
>1
v I
vI
vI
amplification
19
Plot vO versus vI
vO = 10 5 (vI 1)
0.1 change
in vI
Demo
vI
vO
0.0
1.0
1.5
2.0
2.1
2.2
2.3
2.4
10.00
10.00
8.75
5.00
4.00
2.80
1.50
~ 0.00
1V change
in vO
Gain!
Measure vO .
20
One nit
vO
What
happens
here?
1
vI
Mathematically,
K
2
vO = VS RL (vI 1)
2
So
is mathematically predicted behavior
21
One nit
vO
K
2
vO = VS RL (vI 1)
2
What
happens
here?
vI
1
However, from
iD =
K
(vI 1)2
2
VS
for vI 1
RL
vO
VCCS
iD
For vO>0, VCCS consumes power: vO iD

For vO<0, VCCS must supply power!
22
If VCCS is a device that can source

power, then the mathematically
predicted behavior will be observed
vO
K
2
i.e. vO = VS RL (vI 1)
2
vI
where vO goes -ve
23
If VCCS is a passive device,

then it cannot source power,
so vO cannot go -ve.
So, something must give!
Turns out, our model breaks down.
K
2
iD = (vI 1)
2
will no longer be valid when vO 0 .
e.g. iD saturates (stops increasing)
and we observe:
Commonly
vO
vI
24
6.002
CIRCUITS AND
ELECTRONICS
MOSFET Amplifier
Large Signal Analysis
6.002 Fall 2000
Lecture 9
Review
Amp constructed using dependent source

control a
a
port
DS
b output
b port
Dependent source in a circuit

+
a +
i = f (v )
Superposition with dependent sources:

one way tleave all dependent sources in;
solve for one independent source at a
time [section 3.5.1 of the text]
Next, quick review of amp
Reading: Chapter 7.37.7

6.002 Fall 2000
Lecture 9
Amp review
VS
RL
vO
VCCS
vI
K
2
iD = (vI 1)
2
for vI 1V
= 0 otherwise
vO = VS iD RL
K
(vI 1)2
2
6.002 Fall 2000
Lecture 9
Key device Needed:

v
A
B
i = f (v )
voltage controlled
current source
Lets look at our old friend, the MOSFET
6.002 Fall 2000
Lecture 9
Key device Needed:

Our old friend, the MOSFET
First, we sort of lied. The on-state behavior of the
MOSFET is quite a bit more complex than either the
ideal switch or the resistor model would have you believe.
D
G
vGS < VT
G
vGS VT
6.002 Fall 2000
Lecture 9
Graphically
Demo
+
vGS
iDS
egio
n
iDS
vGS VT
vGS < VT
vGS < VT
vDS
S MODEL
vDS
SR MODEL
6.002 Fall 2000
vDS = vGS VT
vGS 1
Saturation
region
vGS 2
vGS3
...
vGS VT
T ri o
de r
iDS
v+DS
iDS
Lecture 9
vGS < VT Cutoff
vDS
region
Graphically
+
vGS
iDS
iDS
egio
n
S MODEL
vDS
SR MODEL
6.002 Fall 2000
vGS 2
vGS3
...
vGS < VT
Saturation
region
T ri o
de r
vGS VT
vDS
vDS = vGS VT
vGS 1
iDS
vGS VT
vGS < VT
v+DS
iDS
vGS < VT
Lecture 9
vDS
when
vDS vGS VT
Notice that
MOSFET
behaves like a
current source
7
MOSFET SCS Model

When
vDS vGS VT
the MOSFET is in its saturation region, and the

switch current source (SCS) model of the MOSFET is
more accurate than the S or SR model
D
G
vGS < VT
S
G
S
vGS
G
VT
iDS = f (vGS )
K
2
= (vGS VT )
2
S
6.002 Fall 2000
Lecture 9
when
vDS vGS VT
Reconciling the models

iDS
iDS
vGS VT
vGS < VT
vDS
S MODEL
for fun!
vGS < VT
Saturation
region
vGS 2
vGS3
...
vGS VT
T ri o
de r
egio
n
iDS
vDS = vGS VT
vGS 1
vDS
SR MODEL
for digital
designs
vGS < VT
vDS
SCS MODEL
for analog
designs
When to use each model in 6.002?

Note: alternatively (in more advanced courses)
vDS vGS VT
vDS < vGS VT
use SCS model

use SR model
or, use SU Model (Section 7.8 of A&L)
6.002 Fall 2000
Lecture 9
Back to Amplifier
VS
vI
AMP
vO
VS
RL
vI
D
S
vO
K
2
iDS = (vI VT )
2
in saturation
region
To ensure the MOSFET operates as a VCCS,

we must operate it in its saturation region
only. To do so, we promise to adhere to the
saturation discipline
6.002 Fall 2000
Lecture 9
10
MOSFET Amplifier
VS
RL
vI
D
S
vO
K
2
iDS = (vI VT )
2
in saturation
region
To ensure the MOSFET operates as a VCCS,

we must operate it in its saturation region
only. We promise to adhere to the
saturation discipline.
In other words, we will operate the amp
circuit such that
vGS VT and vDS vGS VT
vO vI vT
6.002 Fall 2000
Lecture 9
at all times.
11
Lets analyze the circuit

First, replace the MOSFET with its
SCS model.
VS
RL
vO
G
vGS = vI
+
vI
6.002 Fall 2000
iDS
Lecture 9
K
2
= (vI VT )
2
for vO vI VT
12
Lets analyze the circuit

VS
RL
vO
G
vGS = vI
+
vI
iDS =
K
(vI VT )2
2
for vO vI VT
(vO = vDS in our example)
Analytical method: vO vs vI
vO = VS iDS RL
B
K
2
or vO = VS (vI VT ) RL for vI VT
2
vO vI VT
vO = VS
6.002 Fall 2000
vI < VT
(MOSFET turns off)
for
Lecture 9
13
Graphical method vO vs vI
K
2
From A : iDS = (vI VT ) ,
2
vO vI VT
2
for
2iDS
vO
K
K 2
iDS vO
2
B : iDS
6.002 Fall 2000
VS v0
=
RL RL
Lecture 9
14
K 2
K
2
A : iDS = (vI VT ) , for iDS vO
2
2
VS vO
=
i
B : DS
RL RL
iDS
VS
RL
iDS
B
Lo
ad
K 2
vO
2
A
li n
e
vI
= vGS
VS
Constraints
6.002 Fall 2000
and
Lecture 9
vO
must be met
15
iDS
VS
RL
iDS
K 2
vO
2
A
vI
VI
I DS
VO
VS
vO
Constraints A and B must be met.

Then, given VI, we can find VO, IDS .
6.002 Fall 2000
Lecture 9
16

of Amplifier
(under saturation discipline)
1
vO versus vI
Valid input operating range and

valid output operating range
6.002 Fall 2000
Lecture 9
17

vO versus vI
vO
K
2
VS (vI VT ) RL
2
VS
VT
6.002 Fall 2000
vO = vI VT
gets into
triode region
vI
Lecture 9
18

What are valid operating ranges
under the saturation discipline?
Our
Constraints
vI VT
iDS
vO vI VT
iDS
VS
RL
iDS
K 2
vO
2
K 2
vO
2
K
2
iDS = (vI VT )
2
vI
v
V
iDS = S O
RL RL
VS
?
6.002 Fall 2000
vO
vI = VT
vO = VS and iDS = 0
Lecture 9
19

2
What are valid operating ranges

under the saturation discipline?
iDS
iDS
K 2
vO
2
K
2
iDS = (vI VT )
2
vI
VS vO
iDS =
RL RL
vO
1 + 1 + 2 KRLVS
vI = VT +
KRL
1 + 1 + 2 KRLVS
vO =
KRL
VS vO
iDS =
RL RL
6.002 Fall 2000
Lecture 9
vI = VT
vO = VS and iDS = 0
20

Summary
1
vO versus vI
vO = VS
K
(vI VT )2 RL
2
Valid operating ranges under the

saturation discipline?
Valid input range:
vI : VT
to
1 + 1 + 2 KRLVS
VT +
KRL
corresponding output range:
vO : VS to
6.002 Fall 2000
1 + 1 + 2 KRLVS
KRL
Lecture 9
21
6.002
CIRCUITS AND
ELECTRONICS
Amplifiers -Small Signal Model
6.002 Fall 2000
Lecture 10
Review
MOSFET amp
VS
RL
vO
vI
iDS
Saturation discipline operate

MOSFET only in saturation region
Large signal analysis

1. Find vO vs vI under saturation discipline.
2. Valid vI , vO ranges under saturation discipline.
Reading: Small signal model -- Chapter 8
6.002 Fall 2000
Lecture 10
Large Signal Review

1
vO vs vI
K
(vI 1)2 RL
valid for vI VT
and
vO vI VT
K 2
(same as iDS vO )
2
vO = VS
6.002 Fall 2000
Lecture 10
Large Signal Review
Valid operating ranges
V
S
v
O
5V
corresponding
interesting
region for vO
vO > vI VT
vO = vI VT
vO < vI VT
1V
vI
VT
1V
2V
interesting region
for vI . Saturation
discipline satisfied.
6.002 Fall 2000
Lecture 10
But
VS
5V
vO
vO = vI VT
vO
1V
vI
VT
1V
Demo
vI
2V
Amplifies alright,
but distorts
vI
vO
Amp is nonlinear /
6.002 Fall 2000
Lecture 10
Small Signal Model

vO
~ 5V VS
Focus on this line segment
(VI , VO )
~ 1V
vI
VT
1V
~ 2V
2
K (vI VT )
vO = VS
RL
2
Amp all right, but nonlinear!
Hmmm So what about our linear amplifier ???
Insight:
But, observe vI vs vO about some
point (VI , VO) looks quite linear !
6.002 Fall 2000
Lecture 10
Trick
vO
vo
VO
vi
(VI ,VO )
looks
linear
VI
vI
Operate amp at VI , VO
DC bias (good choice: midpoint
of input operating range)
Superimpose small signal on top of VI
Response to small signal seems to be

approximately linear
6.002 Fall 2000
Lecture 10
Trick
vO
vo
VO
vi
(VI ,VO )
looks
linear
VI
vI
Operate amp at VI , VO
DC bias (good choice: midpoint
of input operating range)
Superimpose small signal on top of VI

Response to small signal seems to be
approximately linear
Lets look at this in more detail
I graphically
II mathematically
III from a circuit viewpoint
6.002 Fall 2000
Lecture 10
next
week
8
I Graphically
We use a DC bias VI to boost interesting input

signal above VT, and in fact, well above VT .
VS
RL
interesting
input signal
vI +
VI
+
vO
Offset voltage or bias
6.002 Fall 2000
Lecture 10
Graphically
VS
RL
interesting
input signal
vO
vI +
VI
+
VS
vO
operating
point
VO
VI , VO
VT
Good choice for operating point:
midpoint of input operating range
6.002 Fall 2000
vO = vI VT
vI
Lecture 10
VI
10
Small Signal Model
aka incremental model

aka linearized model
Notation
Input:
vI = VI + vi
total
DC small
variable bias signal (like vI)
bias voltage aka operating point voltage
Output: vO = VO + vo
Graphically,
vI
vO
vi
vo
VI
VO
6.002 Fall 2000
Lecture 10
11
II Mathematically
( watch my fingers)
RL K
2
vO = VS
(vI VT ) VO = VS RL K (VI VT )2
substituting vI = VI + vi
vi << VI
RL K
vO = VS
2
( [VI + vi ] vT )2
RL K
2
( [VI VT ] + vi )2
= VS
RL K
[VI VT ]2 + 2 [VI vT ]vi + vi 2
= VS
2
RL K
VO + vo = VS
(VI VT )2 RL K (VI VT ) vi
2
From ,
vo = RL K (VI VT ) vi
gm
6.002 Fall 2000
related to
Lecture 10
VI
12
Mathematically
gm
related to
VI
vo = g m RL vi
For a given DC operating point voltage VI,
VI VT is constant. So,
vo = A vi
constant w.r.t. vi
In other words, our circuit behaves like a linear amplifier

for small signals
6.002 Fall 2000
Lecture 10
13
Another way
RL K
vO = VS
(vI VT )2
R K
2
L
v V
VS
I
T
2
d
vo =
dv
I
vi
v = V
I
I
slope at VI
g m = K (VI VT )
A = g m RL
amp gain
Also, see Figure 8.9 in the course notes

for a graphical interpretation of this result
6.002 Fall 2000
Lecture 10
14
More next lecture

Demo
iDS
load line
input signal response

operating point
VI
VO
vO
How to choose the bias point:

1. Gain component g m VI
2. vi gets big distortion.
So bias carefully
3. Input valid operating range.
Bias at midpoint of input operating
range for maximum swing.
6.002 Fall 2000
Lecture 10
15
6.002
CIRCUITS AND
ELECTRONICS
Small Signal Circuits
6.002 Fall 2000
Lecture 11
Review:
Small signal notation

vA = VA + va
total operating
point
small
signal
vOUT = f (vI )
d
f (vI )
vi
vout =
dv I
v I =VI
VS
vI = VI + vi
vi
VI
RL
vO = VO + vo
6.002 Fall 2000
Lecture 11
Review:
I Graphical view
(using transfer function)
vO
behaves linear
for small
perturbations
vI
6.002 Fall 2000
Lecture 11
Review:
II Mathematical view
K (vI VT )
vO = VS
RL
2
2
V K (v V )2 R
T
L
d S 2 I
vo =
dv I
vi
v I =VI
vo = K (VI VT ) RL vi
gm
6.002 Fall 2000
related to VI
constant for fixed
DC bias
Lecture 11
How to choose the bias point,

using yet another graphical view
based on the load line
i DS
i DS <
Demo
K 2
vO
2
V S vO
i
=
load line DS R R
L
L
input signal
response
VI
VO
1 + 1 + 2 KR LV S
v I = VT +
KR L
vO
v I = VT
Choosing a bias point:

1. Gain
g m RL VI
2. Input valid operating range for amp.

3. Bias to select gain and input swing.
6.002 Fall 2000
Lecture 11
III The Small Signal Circuit View

We can derive small circuit equivalent
models for our devices, and thereby conduct
small signal analysis directly on circuits
e.g. large signal
circuit model
for amp
vI +
VS
vOUT
K
2
iD = (vI VT )
2
We can replace large signal models with

small signal circuit models.
Foundations: Section 8.2.1 and also in the
last slide in this lecture.
6.002 Fall 2000
Lecture 11
Small Signal Circuit Analysis

1
Find operating point using DC bias

inputs using large signal model.
Develop small signal (linearized)

models for elements.
Replace original elements with small

signal models.
Analyze resulting linearized circuit

Key: Can use superposition and other
linear circuit tools with linearized
circuit!
6.002 Fall 2000
Lecture 11
Small Signal Models

A
MOSFET
large
signal
vGS
Small signal?
6.002 Fall 2000
D
iDS =
K
(vGS VT )2
2
Lecture 11
Small Signal Models

A
MOSFET
large
signal
vGS
iDS =
Small signal:
K
2
iDS = (vGS VT )
2
ids =
vGS
K
(vGS VT )2
2
K (v V )2
v gs
T
2 GS
vGS =VGS
ids = K (VGS VT ) v gs
ids is linear in vgs !
gm
small
signal
v gs
D
ids = K (VGS VT ) v gs
S
6.002 Fall 2000
ids = g m v gs
Lecture 11
DC Supply VS
large
signal
iS
+ vS = VS
Small signal
VS
vs =
iS
is +
vs
6.002 Fall 2000
vS = VS
is
iS = I S
vs = 0
DC source behaves
as short to small
signals.
Lecture 11
10
Similarly, R
large
signal
iR +
vR
R
v R = R iR
vr =
( RiR )
ir
iR iR = I R
vr = R ir
small
signal
6.002 Fall 2000
ir +
vr
R
Lecture 11
11
Amplifier example:
Large signal
RL
vO
+ v
I
iDS
Small signal
+ vi
iDS
K
2
= (vI VT )
2
vO = VS
RL
vo
+ V
S
ids
ids = K (VI VT ) vi
K
(vI VT )2 RL
2
ids RL + vo = 0
vo = ids RL
vo = K (VI VT )RL vi
= g m RL vi
Notice, first we need to find operating

point voltages/currents.
Get these from a large signal analysis.
6.002 Fall 2000
Lecture 11
12
III The Small Signal Circuit View
To find the relationship between the small signal parameters of

a circuit, we can replace large signal device models with
corresponding small signal device models, and then analyze the
resulting small signal circuit.
Foundations: (Also see section 8.2.1 of A&L)

KVL, KCL applied to some circuit C yields:
" + v A + " + vOUT + " + vB + "
Replace total variables with

operating point variables plus small signal variables
" + VA + v a " + VOUT + vout + VB + vb + "

Operating point variables themselves satisfy the
same KVL, KCL equations
" + VA
" + VOUT
+ VB
+"
so, we can cancel them out

Leaving
"
+ va "
+ vout
+ vb + "
But 2 is the same equation as 1 with small signal

variables replacing total variables, so 2 must reflect same
topology as in C, except that small signal models are used.
Since small signal models are linear, our linear tools will now
apply
6.002 Fall 2000
Lecture 11
13
6.002
CIRCUITS AND
ELECTRONICS
Capacitors
and First-Order Systems
6.002 Fall 2000
Lecture 12
Motivation
Demo
5V
5V
5V
0V
5
A
0
5
Expect this, right?

But observe this!
B
0
5
Expected
Observed
C
0
Delay!
6.002 Fall 2000
Lecture 12
Reading:
Chapters 9 & 10
2
The Capacitor
D
n-channel MOSFET
symbol
G
S
drain
gate
m+
e+
t +
a+
l +
+
o
x
i
d
e
source
s
i
l n-channel
p
i MOSFET
n-channel c
o
n
n
D
G
CGS
6.002 Fall 2000
Lecture 12
Ideal Linear Capacitor

+
+ A
++++
-----
d
EA
d
obeys DMD!
total charge on
capacitor
= +q q = 0
C=
i
C
+
v
q = C v
coulombs farads volts
6.002 Fall 2000
Lecture 12
Ideal Linear Capacitor

i
q
q = C v
+
v
dq
i=
dt
d (Cv )
=
dt
dv
=C
dt
E = 1 Cv 2
A capacitor is an energy storage device

memory device history matters!
6.002 Fall 2000
Lecture 12
Analyzing an RC circuit
Thvenin Equivalent:
vI (t ) +
+
vC (t )
Apply node method:

vC vI
dvC
+C
=0
R
dt
dvC
RC
+ vC = vI
dt
t t0
vC (t0 ) given
units
of time
6.002 Fall 2000
Lecture 12
Lets do an example:
+
v I (t )
vC (t )
vI (t ) = VI
vC (0 ) = V0 given
dvC
RC
+ vC = VI
dt
6.002 Fall 2000
Lecture 12
Example
vI (t ) = VI
vC (0 ) = V0 given
dvC
RC
+ vC = VI
dt
vC (t ) = vCH (t ) + vCP (t )
total homogeneous
particular
Method of homogeneous and particular

solutions:
1
Find the particular solution.
2 Find the homogeneous solution.

3 The total solution is the sum of
the particular and homogeneous
solutions.
Use the initial conditions to solve
for the remaining constants.
6.002 Fall 2000
Lecture 12
1 Particular solution
dvCP
+ vCP = VI
dt
RC
vCP = VI
RC
works
dVI
+ VI = VI
dt
0
In general, use trial and error.
vCP : any solution that satisfies the

original equation X
6.002 Fall 2000
Lecture 12
2 Homogeneous solution
dvCH
RC
+ vCH = 0
dt
vCH : solution to the homogeneous

equation Y
(set drive to zero)
vCH = A e st
assume solution
of this form. A,
s?
dA e st
RC
+ A e st = 0
dt
R CA s e st + A e st = 0
Discard trivial A = 0 solution,

Characteristic equation
R C s +1 = 0
s=
or
1
RC
vCH = Ae
6.002 Fall 2000
t
RC
RC
called time
constant
Lecture 12
10
3 Total solution
vC = vCP + vCH
vC = VI + A e
t
RC
Find remaining unknown from initial

conditions:
at t = 0
Given,
vC = V0
so,
V0 = VI + A
or
A = V0 VI
thus
vC = VI + (V0 VI ) e
also
6.002 Fall 2000
iC = C
t
RC
dvC
(V VI )
= 0
e
R
dt
Lecture 12
t
RC
11
vC = VI + (V0 VI ) e
t
RC
vC
VI
V0
0
RC
6.002 Fall 2000
Lecture 12
12
Examples
vC
vC
5V
5V
5 + 5e
t
RC
5e
0V
VO = 0V
VI = 5V
5
0
t
RC
0V
VO = 5V
VI = 0V
5
0
= RC
Remember
B
demo
6.002 Fall 2000
Lecture 12
13
6.002
CIRCUITS AND
ELECTRONICS
Digital Circuit
6.002 Fall 2000
Lecture
13
Review
vI
vI +
VI
+
vC
vC (0 ) = VO
vC = VI + (VO VI ) e
t
RC
vC
VI
VO
RC
6.002 Fall 2000
time constant RC
t
Lecture
13
Lets apply the result to

an inverter.
B
A
X
First, rising delay tr at B
VS
VS
A
vA
5V
0
1 0 at A
6.002 Fall 2000
B
CGS
X
t
Lecture
13

VS
VS
B
vA
5V
CGS
0
1 0 at A
vB
5V
ideal
observed
6.002 Fall 2000
Lecture
13

VS
A
vA
5V
VS
B
CGS
0
1 0 at A
t
5V
VOH
rising delay of X
6.002 Fall 2000
Lecture
vB
tr
13
Equivalent circuit for 01 at B
vI = VS
RL
vI = VS
vB (0 ) = 0
From
CGS
+
vB
for t 0
1
vB = VS + (0 VS ) e
t
RL CGS
Now, we need to find t for which

vB = VOH .
6.002 Fall 2000
Lecture
13
Or
vOH = VS VS e
Find tr :
VS e
t r
RL CGS
t
RL CGS
= VS VOH
VS VOH
tr
= ln
RL CGS
VS
VS VOH
t r = RL CGS ln
VS
6.002 Fall 2000
Lecture
13
Or
vOH = VS VS e
Find tr :
VS e
t r
RL CGS
t
RL CGS
= VS VOH
VS VOH
tr
= ln
RLCGS
VS
VS VOH
t r = RL CGS ln
VS
e.g.
RL = 1K
VS = 5V
CGS = 0.1 pF
VOH = 4V
t r = 1 10 0.1 10
3
= 0.16 ns
12
54
ln
5
RC = 0.1 ns !
6.002 Fall 2000
Lecture
13
Falling Delay tf
Falling delay tf is
the t for which vB falls to VOL
Equivalent circuit for 1 0 at B

vB (0 ) = VS
(5V )
RL
VS +
CGS
RON
+
vB
6.002 Fall 2000
Lecture
13
Falling Delay tf
Equivalent circuit for 1 0 at B

vB (0 ) = VS
(5V )
RL
VS +
RON
CGS
+
vB
CGS
+
vB
X
Thvenin replacement
RTH
VTH +
RTH = RL || RON
VTH
6.002 Fall 2000
RON
= VS
RON + RL
Lecture
13
10
From
1
vB = VTH + (VS VTH ) e
t
RTH CGS
Falling decay tf is
the t for which vB falls to VOL
t f
VOL = VTH + (VS VTH ) e RTH CGS

or
VOL VTH
t f = RTH CGS ln
VS VTH
6.002 Fall 2000
Lecture
13
11
t f = RTH CGS ln
e.g.
RL = 1K
VS = 5V
CGS = 0.1 pF
RTH 10,
VOL VTH
VS VTH
RON = 10
VOL = 1V
VTH 0V
t f = 10 0.1 10
= 1.6 ps
12
1
ln
5
RC = 1 ps !
6.002 Fall 2000
Lecture
13
12
For recitation: Slow may be better
Problem
chip
pin 2
pin 1
v
CL
v:
ideal
observed
slow!
So the engineers decided to speed it up
RL
RON
6.002 Fall 2000
made RL small
made RON small
Lecture
13
13
For recitation: Slow may be better
Problem
chip
pin 2
pin 1
v
CL
v:
ideal
observed
slow!
but, disaster!
v:
observed
expected
6.002 Fall 2000
VIL
Lecture
13
14
Why? Consider
Case
Demo
R1
pin1
R0
ok
6.002 Fall 2000
Lecture
13
15
Why? Consider
Case 2
Demo
CP
R1
pin1
pin2
R0
R2
crosstalk!
CP
R
model for crosstalk:
+
v
6.002 Fall 2000
Lecture
13
16
Case 3
6.002 expert saw the solution

R1
CP
R0
R2
slower transitions!
Detailed analysis in recitation.
6.002 Fall 2000
Lecture
13
17
6.002
CIRCUITS AND
ELECTRONICS
State and Memory
6.002 Fall 2000
Lecture 14
Review
Recall
vI
+
v I = VI
for
vC
vC (0)
t 0
t
vC = VI + (vC (0) VI ) e RC
Reading: Section 10.3 and Chapter 11
6.002 Fall 2000
Lecture 14
This lecture will dwell on the

memory property of capacitors.
For the RC circuit in the previous slide
vI
VI
t 0
vI
vC
VI
t
vC = VI + (vC (0) VI ) e RC
vC (0 )
0
Notice that the capacitor voltage for t 0 is

independent of the form of the input voltage
before t = 0 . Instead, it depends only on the
capacitor voltage at t = 0 , and the input voltage
for t 0 .
6.002 Fall 2000
Lecture 14
State
State : summary of past inputs relevant

to predicting the future
q = C V
for linear capacitors,
capacitor voltage V
is also state variable
state variable, actually
6.002 Fall 2000
Lecture 14
State
Back to our simple RC circuit 1
vC = f (vC (0 ), vI (t ))
vC = VI + (vC (0 ) VI ) e
t
RC
Summarizes the past input relevant

to predicting future behavior
6.002 Fall 2000
Lecture 14
State
We are often interested in circuit

response for
zero state
vC (0) = 0
zero input
vI (t) = 0
Correspondingly,
zero state response or ZSR
vC = VI VI e
t
RC
zero input response or ZIR

vC = vC (0 ) e
6.002 Fall 2000
t
RC
Lecture 14
One application of STATE
DIGITAL MEMORY
Why memory?
Or, why is combinational logic insufficient?
Examples

Consider adding 6 numbers on your

calculator
2+9+6+5+3+8
M+
Remembering transient inputs
6.002 Fall 2000
Lecture 14
Memory Abstraction
A 1-bit memory element
d IN
store M
d OUT
The
6.004
view
The
NEC
View
Remembers input when store goes high.

Like a camera that records input (dIN) when the
user presses the shutter release button.
The recorded value is visible at dOUT .
d IN
store
d OUT
6.002 Fall 2000
remembers the 1
Lecture 14
Building a memory element
A First attempt
dIN
dOUT
C
storage
node
store
6.002 Fall 2000
Lecture 14
vC d
OUT
dIN
store = 1
C
vC d
OUT
dIN
store = 0
C
vC
Stored value leaks away
vC = 5 e
t
RL C
T = RLC ln
VOH
RL
5V
VOH
from 2
store pulse width >> RON C

6.002 Fall 2000
Lecture 14
10
B Second attempt
dIN
buffer
dOUT
*
C
RIN
buffer
store
Input resistance RIN
VOH
T = RIN C ln
5
RIN >> RL
Better, but still not perfect.
Demo
6.002 Fall 2000
Lecture 14
11
C Third attempt
buffer + refresh
store
dIN
dOUT
*
store
C
Does this work?
No. External value can
influence storage node.
6.002 Fall 2000
Lecture 14
12
D Fourth attempt
buffer + decoupled
refresh
store
dIN
dOUT
*
store
C
Works!
6.002 Fall 2000
Lecture 14
13
A Memory Array
4-bit memory
Decoder
00
01
10
11
OUT
d IN
S M
d OUT
d IN
S M
d OUT
d IN
S M
d OUT
d IN
S M
d OUT
a0 a1
Address
IN
store
Address
IN store
D
6.002 Fall 2000
Lecture 14
OUT
14
Truth table for decoder
a0
0
0
1
1
a1
0
1
0
1
6.002 Fall 2000
A
1
0
0
0
B
0
1
0
0
Lecture 14
C
0
0
1
0
D
0
0
0
1
15
Agarwals top 10 list on memory

10
9
8
7
6
5
I have no recollection, Senator.

I forgot the homework was due today.
Adlibbing ZSR
I think, therefore I am.
I think that was right.
I forgot the rest
6.002 Fall 2000
Lecture 14
16
6.002
CIRCUITS AND
ELECTRONICS
Second-Order Systems
6.002 Fall 2000
Lecture
15
5V
5V
Demo
2K
50
2K
A
+
B
large
loop
CGS
Our old friend, the inverter, driving another.

The parasitic inductance of the wire and
the gate-to-source capacitance of the
MOSFET are shown
[Review complex algebra appendix for next class]

6.002 Fall 2000
Lecture
15
5V
5V
Demo
50
2K
2K
C
A
+
Relevant circuit:
B
large
loop
2K
CGS
5V +
6.002 Fall 2000
B
CGS
Lecture
15
Observed Output
2k
5
vA
0
vB
0
2k
vC
0
Now, lets try to speed up our inverter by

closing the switch S to lower the effective
resistance
6.002 Fall 2000
Lecture
15
Observed Output
~50
5
vA
0
vB
0
50
vC
0
t
Huh!
6.002 Fall 2000
Lecture
15
First, lets analyze the LC network
vI (t )
i (t )
+
v(t )
Node method:
i (t ) = C
dv
dt
Recall
vI v = L
dv
1
(vI v) dt = C
L
dt
1
(v I v )
L
di
dt
1 t
(vI v) dt = i
d 2v
=C 2
dt
d 2v
LC 2 + v = vI
dt
time2
6.002 Fall 2000
v, i state variables
Lecture
15
Solving
Recall, the method of homogeneous and
particular solutions:
1
Find the particular solution.
Find the homogeneous solution.

L
4 steps
The total solution is the sum of the

particular and homogeneous.
Use initial conditions to solve for the
remaining constants.
v = vP (t ) + vH (t )
6.002 Fall 2000
Lecture
15
Lets solve
d 2v
LC 2 + v = vI
dt
For input
V0
vI
0
And for initial conditions
v(0) = 0 i(0) = 0 [ZSR]
6.002 Fall 2000
Lecture
15
Particular solution
d 2 vP
LC 2 + vP = V0
dt
is a solution.
vP = V0
6.002 Fall 2000
Lecture
15
Homogeneous solution
Solution to
d 2 vH
LC 2 + vH = 0
dt
Recall, vH :
solution to homogeneous
equation (drive set to zero)
Four-step method:
A Assume solution of the form*

vH = Ae st
, A, s = ?
so,
LCAs 2 e st + Ae st = 0
1
s =
LC
characteristic
equation
1
s=j
LC
C Roots
j = 1
o =
s = j o
1
LC
General solution,
vH = A1e jot + A2 e jot
6.002 Fall 2000
Lecture
Differential equations are commonly

solved by guessing solutions
15
10
Total solution
v(t ) = vP (t ) + vH (t )
v( t ) = V0 + A1e jot + A2 e jot

Find unknowns from initial conditions.
v(0) = 0
0 = V0 + A1 + A2
i ( 0) = 0
dv
i (t ) = C
dt
i( t ) = CA1 jo e jot CA2 jo e jot

so,
0 = CA1 jo CA2 jo
or,
A1 = A2
V0 = 2 A
V0
A1 =
2
so,
V0 jot
v( t ) = V0 (e + e jot )
2
6.002 Fall 2000
Lecture
15
11
Total solution
Remember Euler relation

e jx = cos x + j sin x
(verify using Taylors

expansion)
e jx + e jx
= cos x
2
so,
v( t ) = V0 V0 cos ot
where
i( t ) = CV0o sin ot
1
o =
LC
The output looks sinusoidal
6.002 Fall 2000
Lecture
15
12
v(t )
Plotting the Total Solution
2V0
V0
3
2
2
CV0o
o t
i (t )
3
2
o t
CV0o
6.002 Fall 2000
Lecture
15
13
Summary of Method
1
Write DE for circuit by applying

node method.
Find particular solution vP by guessing

and trial & error.
Find homogeneous solution vH

A Assume solution of the form Aest .
B Obtain characteristic equation.
C Solve characteristic equation
for roots si .
D Form vH by summing Ai esit
terms.
Total solution is vP + vH ,
solve for remaining constants using
initial conditions.
6.002 Fall 2000
Lecture
15
14
Example
What if we have:
iC
+
C vC
vC (0) = V
iC (0) = 0
We can obtain the answer directly from

the homogeneous solution (V0 = 0).
6.002 Fall 2000
Lecture
15
15
Example
iC
+
C vC
vC (0) = V
iC (0) = 0
We can obtain the answer directly from

the homogeneous solution (V0 = 0).
vC ( t ) = A1e jot + A2 e jot

vC (0) = V
V = A1 + A2
iC (0) = 0
0 = CA1 jo CA2 jo
or A1 = A2 =
or
vC =
V
2
V j o t
(
e + e j o t )
2
vC = V cos ot
iC = CV o sin ot
6.002 Fall 2000
Lecture
15
16
Example
vC
o t
CVo iC
2
o t
CVo
6.002 Fall 2000
Lecture
15
17
Energy
EC
C:
1
CV 2
2
1
2
CvC
2
o t
EL
1
2
L : LiC
2
1
CV 2
2
2
Notice
o t
1
1
1
2
2
CvC + LiC = CV 2
2
2
2
Total energy in the system is a constant,

but it sloshes back and forth between the
Capacitor and the inductor
6.002 Fall 2000
Lecture
15
18
RLC Circuits
R
vI (t ) +
i (t )
C
+
v(t )
v(t )
no R
add R
t
Damped sinusoids with R remember demo!
See A&L Section 13.2

6.002 Fall 2000
Lecture
15
19
6.002
CIRCUITS AND
ELECTRONICS
Sinusoidal Steady State
6.002 Fall 2000
Lecture
16
Review
We now understand the why of:

5V
R
L
C
Today, look at response of networks

to sinusoidal drive.
Sinusoids important because signals can be
represented as a sum of sinusoids. Response to
sinusoids of various frequencies -- aka frequency
response -- tells us a lot about the system
6.002 Fall 2000
Lecture
16
Motivation
For motivation, consider our old friend,

the amplifier:
V
S
vi
VBIAS
vO
vC
Demo
CGS
Observe vo amplitude as the frequency of the

input vi changes. Notice it decreases with
frequency.
Also observe vo shift as frequency changes
(phase).
Need to study behavior of networks for
sinusoidal drive.
6.002 Fall 2000
Lecture
16
Sinusoidal Response of RC Network
Example:
vI +
iC
vI (t ) = Vi cos t
=0
vC (0) = 0
+
vC
for t 0 (Vi real)

for t < 0
for t = 0
vI
t
6.002 Fall 2000
Lecture
16
Our Approach
Example:
vI
+
iC
vC
Effort
Determine vC(t)
agony
Usual
approach
sneaky approach
very
sneaky
Th
is
lec
tu
re
11
:
0
0
11
:
2
0
1
2
N
:0
ex
0
t
le
ct
ur
e
easy
e
m
e
g
l
u
d
In
6.002 Fall 2000
Lecture
16
Lets use the usual approach
Set up DE.
Find vp.
Find vH.
vC = vP + vH,
6.002 Fall 2000
solve for unknowns

using initial conditions
Lecture
16
Usual approach
Set up DE
RC
dvC
+ vC = vI
dt
= Vi cos t
That was easy!
6.002 Fall 2000
Lecture
16
Find vp
dvP
+ vP = Vi cos t
RC
dt
First try:
nope
vP = A
Second try:
vP = A cos t
Third try:
vP = A cos(t + ) frequency
amplitude phase
nope
RCA sin(t + ) + A cos(t + ) = Vi cos t

RCA sin t cos RCA cos t sin +
A cos t cos A sin t sin
= Vi cos t
..
.
gasp !
works, but trig nightmare!
6.002 Fall 2000
Lecture
16
Lets get sneaky!

Find particular solution to another input
dvPS
+ vPS = vIS
RC
dt
= Vi e st
st
v
=
V
e
Try solution PS
p
RC
dV p e st
(S: sneaky :-))
+ V p e st = Vi e st
dt
sRCV p e st + V p e st = Vi e st
Nice
property
of
exponentials
( sRC + 1 )V p = Vi
Vi
Vp =
1 + sRC
Vi
e st
1 + sRC
is particular solution to Vi e st
Thus, vPS =
ly
Vi
e j t
1 + jRC
j t
V
e
solution for i
where we replace s = j
complex amplitude
Vp
6.002 Fall 2000
easy!
Lecture
16
Fourth try to find vP

using the sneaky approach
Fact 1: Finding the response to

Vi e j t
was easy.
Fact 2: vI = Vi cos t
= real[Vi e j t ] = real[vIS ]
from Euler relation,

e j t = cos t + j sin t
real
part
vI response vP
vIS response vPS
real
part
an inverse superposition argument,

assuming system is real, linear.
6.002 Fall 2000
Lecture
16
10
2 Fourth try to find vP

so,
complex
vP = Re[vPS ] = Re[V p e jt ]
Vi
= Re
e j t
1+ jRC
Vi (1 jRC ) j t
= Re
e
1 + 2 R 2C 2
Vi
j j t
= Re
e e , tan = RC
2 2 2
1+ R C
Vi
j( t + )
= Re
1 + 2 R 2C 2
vP =
Vi
1+ R C
2
cos( t + )
Recall, vP is particular response to Vi cos t .

6.002 Fall 2000
Lecture
16
11
Find vH
Recall,
6.002 Fall 2000
vH = Ae
t
RC
Lecture
16
12
Find total solution
vC = vP + vH
vC =
Vi
1+ R C
2
cos( t + ) + Ae
t
RC
where = tan 1 ( RC )
Given vC(0) = 0 for t = 0

so,
Vi
A=
cos( )
2 2 2
1+ R C
Done!
6.002 Fall 2000
Phew !
Lecture
16
13
We are usually interested only in the

particular solution for sinusoids,
i.e. after transients have died.
Notice when t , vC vP as e
vC =
Vi
1+ R C
2
t
RC
cos( t + ) + Ae
0
t
RC
where = tan 1 ( RC )
Vi
A=
cos( )
2 2 2
1+ R C
Vp
Vp
Described as
SSS: Sinusoidal Steady State
6.002 Fall 2000
Lecture
16
14
All information about SSS is contained

in Vp , the complex amplitude!
Steps 3 , 4
were a waste of
time!
Vi
Vp =
1 + jRC
Recall
Vp
1
=
Vi 1+ jRC
Vp
Vi
magnitude
Vp
phase :
Vi
Vp
Vi
6.002 Fall 2000
1
1 + 2 R 2C 2
e j where
= tan 1 RC
1
1 + 2 R 2C 2
= tan 1 RC
Lecture
16
15
Visualizing the process of finding the

particular solution vP
Vi cos t
drive
D.E.
+
nightmare
trig.
V p cos[t + V p ]
particular
solution
algebraic
take
equation
real
+
part
complex
algebra V p e j t
sneak
in
Vi e jt
drive
the sneaky path!

6.002 Fall 2000
Lecture
16
16
Magnitude Plot
transfer function
Vp
H ( j ) =
Vi
Vp
Vi
Vp
Vi
1
1 + 2 R 2C 2
log
scale
log
scale
1
=
RC
From demo: explains vo fall off

for high frequencies!
6.002 Fall 2000
Lecture
16
17
Phase Plot
= tan 1 RC
=
Vp
Vi
=
0
1
RC
log scale
6.002 Fall 2000
Lecture
16
18
6.002
CIRCUITS AND
ELECTRONICS
The Impedance Model
6.002 Fall 2000
Lecture 17
Review
Sinusoidal Steady State (SSS)

Reading 14.1, 14.2
vI = Vi cos t +
+
vO
Focus on steady state, only care

about vP as vH dies away.
Focus on sinusoids.
SSS
Sinusoidal Steady State (SSS)

Reading 14.1, 14.2
Reading: Section 14.3 from course notes.

6.002 Fall 2000
Lecture 17
Review
vP
Vi cos t
1
usual
circuit
model
sneak
in
Vi e jt
drive
set
up
DE
complex
algebra
V p cos[t + V p ]
nightmare
trig.
Vp
2
The Sneaky Path
3
vH
take 4
real total
part
V p e j t
Vi
1 + jRC
Vp contains all the information we need:
Vp
V p
6.002 Fall 2000
Amplitude of output cosine

phase
Lecture 17
Review
vO = V p cos(t + V p )
Vp
Vi
Vp
1
= H ( j ) transfer
function
1 + jRC
remember
demo
Vi
1
2
1
RC
1 + 2 R 2C 2
Bode plot
Vp
Vi
1
=
RC
break frequency
1
RC
RC
tan 1

1 4
The Frequency View

6.002 Fall 2000
Lecture 17
Is there an even simpler way

to get Vp ?
Vi
Vp =
1 + jRC
Divide numerator and denominator by jC.
1
V p = Vi
j C
1
+R
j C
Hmmm looks like a voltage divider

relationship.
ZC
V p = Vi
ZC + R
Lets explore further
6.002 Fall 2000
Lecture 17
The Impedance Model

Is there an even simpler way to get Vp ?
Consider:
+
vR
+
vC
iR
i R = I r e j t
vR = RiR
vR = Vr e j t
Vr e j t = RI r e j t
Resistor
iC
iC = I C e
j t
vC = VC e j t
Vr = RI r
dvC
iC = C
dt
I C e j t = CVC je j t
Capacitor
+
vL
VC =
diL
vL = L
dt
j t
iL
iL = I l e
vL = Vl e j t
Vl e j t = LI l je j t
Inductor
6.002 Fall 2000
1
IC
j C
ZC
Lecture 17
Vl = jL I l
ZL
The Impedance Model

In other words,
capacitor
Ic
+
Vc
ZC
Vc = Z C I c
1
ZC =
j C
impedance
inductor
resistor
Il
+
Vl
+
Vr
ZL
Ir
ZR
Vl = Z l I l
Z l = j L
Vr = Z r I r
Zr = R
For a drive of the form Vc e jt ,

complex amplitude Vc is related to the
complex amplitude Ic algebraically,
by a generalization of Ohms Law.
6.002 Fall 2000
Lecture 17
Back to RC example
R
+
C vC
vI +
Impedance model:
ZR = R
Ic
+
Vc
Vi +
1
ZC =
jC
1
ZC
jC
Vc =
Vi =
Vi
1
ZC + Z R
+R
jC
Vc =
1
Vi
1 + jRC
Done!
All our old friends apply!

KVL, KCL, superposition
6.002 Fall 2000
Lecture 17
Another example, recall series RLC:

Remember, we want only the steady-state
response to sinusoid
Ir
L
Vi e j t
Vi +
C
R
Vi cos t
Vr =
Vi Z R
Z L + ZC + Z R
+
Vr
Vr e j t
Vr cos(t + Vr )
Vi R
Vr =
1
j L +
+R
jC
Vr =
Vi jCR
2 LC + 1 + jCR
We will study this and other functions

in more detail in the next lecture.
6.002 Fall 2000
Lecture 17
The Big Picture

V p cos[t + V p ]
Vi cos t
usual
circuit
model
6.002 Fall 2000
set
up
DE
Lecture 17
nightmare
trig.
10
The Big Picture

V p cos[t + V p ]
Vi cos t
usual
circuit
model
Vi e jt
drive
6.002 Fall 2000
set
up
DE
nightmare
trig.
complex
algebra
Lecture 17
take
real
part
11
The Big Picture

V p cos[t + V p ]
Vi cos t
usual
circuit
model
Vi e jt
drive
set
up
DE
nightmare
trig.
complex
algebra
impedance-based
circuit model
take
real
part
complex
algebra
No D.E.s, no trig!
6.002 Fall 2000
Lecture 17
12
Back to
Ir
Vr
jRC
=
Vi 1 + jRC 2 LC
Vi
L
+
C
R
+
Vr
Lets study this transfer function

Vr
jRC
=
Vi 1 + jRC 2 LC
(
jRC
1 2 LC ) jRC
=
2
(1 LC ) + jRC (1 2 LC ) jRC
Vr
=
Vi
(1
RC
LC ) + (RC )
2
Observe
Low : RC
R
High :
L
LC = 1 : 1
6.002 Fall 2000
Lecture 17
13
Graphically
Vr
=
Vi
RC
(1
LC ) + (RC )
2
Low : RC
R
High :
L
LC = 1 : 1
Vr
Vi
Band Pass
R
L
RC
1
LC
Remember this trick to sketch the form of

transfer functions quickly.
More next week
6.002 Fall 2000
Lecture 17
14
6.002
CIRCUITS AND
ELECTRONICS
Filters
6.002 Fall 2000
Lecture
18
Review
R
vI
+
vC
ZR
Vi +
+
Vc
ZC
ZC
Vc =
Vi
ZC + Z R
1
Vc
1
j C
=
=
1
Vi
+ R 1 + jRC
j C
Reading: Section 14.5, 14.6, 15.3 from A & L.
6.002 Fall 2000
Lecture
18
A Filter
ZR
Vi +
+
Vc
ZC
ZC
1
Vi =
Vc =
ZC + Z R
1 + jRC
Vc
H ( ) =
Vi
Low Pass Filter
Demo
with audio
6.002 Fall 2000
Lecture
18
Quick Review of ImpedancesJust as
I ab
R1
Vab
RAB
Vab
=
= R1 + R2
I ab
Z AB
Vab
=
= R1 + jL
I ab
R2
I ab
R1
Vab
j L
B
6.002 Fall 2000
Lecture
18
Quick Review of Impedances

Similarly
Z AB = R1 + Z C || R2 + Z L
R1
R2
C
L
= R1 +
Z C R2
+ ZL
Z C + R2
= R1 +
R2
+ jL
1 + jCR2
6.002 Fall 2000
Lecture
18
We can build other filters by

combining impedances
Z ( )
L
Z
R
C
6.002 Fall 2000
Lecture
18
We can build other filters by

combining impedances
Z ()
L
Z
R
C
H ( )
HPF
High Pass Filter
H ( )
LPF
Low Pass Filter
H ( )
HPF
6.002 Fall 2000
Lecture
18
Check out:
+
R Vr
Vi +
Intuitively:
Vr
1
Vi
L
k
bloc
q
fre
w
s lo
C bloc
o =
(1
6.002 Fall 2000
RC
freq
LC
R
Vr
=
1
Vi
j L +
+R
j C
j RC
=
1 2 LC + j RC
Vr
=
Vi
ks hig
h
LC ) + ( RC )
2
Lecture
18
At resonance,
= o
and
ZL + ZC = 0,
so Vi sees
only R!
More later
8
What about:
Vi +
Vlc
Vi
1
Vlc
Band Stop Filter
C open
L open
Check out Vl and Vc in the lab.
6.002 Fall 2000
Lecture
18
Another example:
R
+
Vi +
Vo
Vo
Vi
ort
h
s
L
BPF
Cs
ho
rt
Application: see AM radio coming up shortly
6.002 Fall 2000
Lecture
18
10
AM Radio Receiver
antenna
R
Vi +
demodulator
amplifier
Thvenin
antenna
model
crystal radio demo
6.002 Fall 2000
Lecture
18
11
AM Receiver
R
Vi +
signal
strength
demodulator
amplifier
filter
10 KHz
WBZ
News
Radio
f
540 1000 1010 1020 1030 1600 KHz
Selectivity important
relates to a parameter Q for the filter. Next
6.002 Fall 2000
Lecture
18
12
Selectivity:
Look at series RLC in more detail
C
Vi +
Recall,
Vr
Vi
+
Vr
R
Vr
R
=
Vi R + j L + 1
j C
higher Q
1
2
bandwidth
o
o
Define Q =
quality factor
high Q more selective

6.002 Fall 2000
Lecture
18
13
Quality Factor Q
Q=
:
Vr
R
=
Vi R + j L +
1
=
1
L
1
1 + j
j C
R
CR
at =0
1
o =
LC
?
6.002 Fall 2000
Lecture
18
14
Quality Factor Q
o
Q=
:
Note that abs magnitude is
when
Vr
=
Vi
i.e. when
1
2
1
1
=
L
1 1 j1
1 + j
R CR
L
1
= 1
R CR
R
L
1
=0
LC
Looking at the roots of both equations,

R 1 R2
4
1 =
+
+
2 L 2 L2 LC
R 1
2 =
+
2L 2
R2
4
+
L2 LC
R
= 1 2 =
L
6.002 Fall 2000
Lecture
18
15
Quality Factor Q
o
Q=
Q=
o
R
L
o L
1
o =
LC
The lower the R (for series R),

the sharper the peak
6.002 Fall 2000
Lecture
18
16
Quality Factor Q
Another way of looking at Q :
energy stored
Q = 2
energy lost per cycle
= 2
1
L Ir
2
1 2 2
Ir R
0
2
o L
Q=
R
6.002 Fall 2000
Lecture
18
17
6.002
CIRCUITS AND
ELECTRONICS
The Operational Amplifier

Abstraction
6.002 Fall 2000
Lecture 19
Review
MOSFET amplifier 3 ports

+
+
vO output
port
+
input
vI
port
VS
power
port
Amplifier abstraction
VS
+
vI
6.002 Fall 2000
+
v
O
vI
Lecture 19
vO
Function of vI
Review
vI
vO
Function of vI
Can use as an abstract building block for

more complex circuits (of course, need
to be careful about input and output).
Today
Introduce a more powerful amplifier
abstraction and use it to build more
complex circuits.
Reading: Chapter 16 from A & L.
6.002 Fall 2000
Lecture 19
Operational Amplifier
Op Amp
VS
input
port
power
port
output
port
VS
More abstract representation:
+
vIN
6.002 Fall 2000
Lecture 19
vOUT
Circuit model (ideal):

vO
+
i=0
v+
+
v
i=0
Av
A
i.e. input resistance

0 output resistance
A virtually
No saturation
6.002 Fall 2000
Lecture 19
Using it
12V
VS = 12V
vO
vIN
12V
RL
VS = 12V
Demo
12V
10 V
vO active region
saturation
10V
12V
vIN
A ~ 106
but unreliable,
temp. dependent
(Note: possible confusion with MOSFET saturation!)

6.002 Fall 2000
Lecture 19
Let us build a circuit

Circuit: noninverting amplifier
v+
v
vIN +
vO
R1
R2
Equivalent circuit model

+
i=0
vIN +
op amp
v+
v
vO
+ A(v + v )
R1
i=0
R2
6.002 Fall 2000
Lecture 19
Let us analyze the circuit:

Find vO in terms of vIN, etc.
vO = A(v + v )
R2
= A vIN vO
R1 + R2
AR2
vO 1 +
= AvIN
R1 + R2
AvIN
vO =
AR2
1+
R1 + R2
What happens when A is very large?
6.002 Fall 2000
Lecture 19
Lets see When A is large

AvIN
AvIN
vO =
AR2
AR2
1+
R1 + R2 R1 + R2
vIN
Suppose
(R1 + R2 )
A = 10 6
R1 = 9 R
R2 = R
R2
gain
10 6 vIN
vO =
10 6 R
1+
9R + R
10 6 vIN
=
1
6
1 + 10
10
vO vIN 10
Demo
Gain:
determined by resistor ratio
insensitive to A, temperature, fab variations
6.002 Fall 2000
Lecture 19
Why did this happen?

Insight:
5V
v+
vIN +
5V
10V
A
6V
6V
negative
feedback
i =0
12V
vO = 2vIN
R
vO
2
R
e.g. vIN = 5V
Suppose I perturb the circuit
(e.g., force vO momentarily to 12V somehow).

Stable point is when v+ v- .
Key: negative feedback portion of

output fed to ve input.
e.g. Car antilock brakes
small corrections.
6.002 Fall 2000
Lecture 19
10
Question: How to control a

high-strung device?
Antilock brakes
is it
turning?
no
di
s
yes
release apply
Michelin
its
all about
control
yes/no
k
c
a
db
e
e
f
v. v. powerful brakes
6.002 Fall 2000
Lecture 19
11
More op amp insights:

Observe, under negative feedback,
R1 + R2
vIN
R1
v
v+ v = O =
0
A
A
v+ v
We also know
i+ 0
i - 0
yields an easier analysis method
(under negative feedback).
6.002 Fall 2000
Lecture 19
12
Insightful analysis method

under negative feedback
v+ v
i+ 0
i 0
a vIN
vIN +
g vO = vIN
+
vO
b vIN
c vIN
R1 f
e i=0
vIN
d
R2
6.002 Fall 2000
R1 + R2
R2
Lecture 19
vIN
R2
R2
13
Question:
a vIN v +
vIN +
b vIN
c vIN
vO
vO vIN
or
R1 + R2
vO = vIN
R2
with R1 = 0
R2 =
6.002 Fall 2000
Lecture 19
14
Why is this circuit useful?

+
vIN +
vO
vO vIN
Buffer
voltage gain = 1
input impedance =
output impedance = 0
current gain =
power gain =
6.002 Fall 2000
Lecture 19
15
6.002
CIRCUITS AND
ELECTRONICS
Operational Amplifier Circuits
6.002 Fall 2000
Lecture 20
Review
Operational amplifier abstraction

+
input resistance
0 output resistance
Gain A very large
Building block for analog systems
We will see these examples:

Digital-to-analog converters
Filters
Clock generators
Amplifiers
Adders
Integrators & Differentiators
Reading: Chapter 16.5 & 16.6 of A & L.
6.002 Fall 2000
Lecture 20
Consider this circuit:

i
i
R1
v2 +
v1 +
R2
v = v1
R1 + R2
v
+
v2 v
i=
R1
R1
R2
v
v+ +
+
vOUT
R2
vOUT = v iR2
v
= v 2
R2
R1
R
R
= v 1 + 2 v2 2
R1
R1
= v1
R2
R + R2
R
1
v2 2
R1 + R2
R1
R1
R2
= (v1 v2 )
R1
6.002 Fall 2000
subtracts!
Lecture 20
Another way of solving

use superposition
v1 0
v2 0
R1
R2
R1
v2 +
v1 +
v+ +
R2
vOUT2
vOUT2
vOUT1
R1 + R2
=v
R1
+
v1 R2 R1 + R2
=
R1 + R2
R1
= v1
vOUT = vOUT1 + vOUT2

R2
= (v1 v2 )
R1
6.002 Fall 2000
R2
R1
R1 || R2
R2
= v2
R1
vOUT1
Lecture 20
R2
R1
Still subtracts!
4
Lets build an intergrator

vI +
+
vO
dt
Lets start with the following insight:

i
+
i +
vO
1
vO = i dt
C
vO is related to i dt
But we need to somehow convert
voltage vI to current.
6.002 Fall 2000
Lecture 20
First try use resistor

+ vR
vI +
R
C
vO
vI
i
R
But, vO must be very small compared

to vR, or else
v
i I
R
When is vO small compared to vR ?
dv
larger the RC,
RC O + vO = vI
dt
smaller the vO
vR
dvO
when RC
>> vO
for good
dt
integrator
dvO
RC
vI
RC >> 1
dt
t
1
or
vO
vI dt
RC
Demo
6.002 Fall 2000
Lecture 20
Theres a better way

i
Notice
i
v 0V under negative feedback

vI
i
=
so,
R
R
vI +
vI
R
vC
vI
vO = vC
+
t
vO
1 vI
vO = dt
C R
We have our integrator.

6.002 Fall 2000
Lecture 20
Now, lets build a differentiator

+
vO
d
dt
vI +
Lets start with the following insights:

i
vI
dvI
i=C
dt
dvI
i is related to
dt
But we need to somehow convert current
to voltage.
6.002 Fall 2000
Lecture 20
Differentiator
Recall
i
i
+
R
+
vO
+
0V
C
vI +
+ vC
Demo
6.002 Fall 2000
vO = iR
current
to
voltage
vO
vI = vC
dvI
i=C
dt
dvI
vO = RC
dt
Lecture 20
6.002
CIRCUITS AND
ELECTRONICS
Op Amps Positive Feedback
6.002 Fall 2000
Lecture
21
Negative vs Positive Feedback

Consider this circuit negative feedback
vIN
R1
R2
R1
vIN +
+
R
+
vOUT = 2 vIN
R1
is
s
e
y
l
g
a a
an t p
e ex
e
s n
on
+
R2
vOUT = vIN
R1
and this positive feedback
vIN +
R1
R2
Whats the difference?

Consider what happens when there is a pertubation
Positive feedback drives op amp into saturation:
vOUT VS
6.002 Fall 2000
Lecture
21
Static Analysis of Positive Feedback Ckt

v IN
v IN +
R1
R2
vOUT
v + R2
R1
vOUT
A(v + v )
vOUT = A(v + v )
= Av +
v vIN
= A OUT
R1 + vIN
R1 + R2
AR1vIN
AR1
vOUT
+ AvIN
R1 + R2
R1 + R2
AR1
R1
vOUT 1
v
A
1
=
IN R + R
R1 + R2
1
2
vOUT
6.002 Fall 2000
1 R1
R +R
R2
1
2
Av
vIN
IN
AR
R1
1
R1 + R2
Lecture
21
Representing dynamics of op amp
v+
+
6.002 Fall 2000
+
v*
C
(v + v )
Lecture
vo
+
Av*
21
Representing dynamics of op amp

Consider this circuit and lets analyze its
dynamics to build insight.
R2
R1
+
vo
R4
R3
Circuit model
R1
v+
v
R3
vo
A
R2
C
(v + v )
+
v*
+
vo
R4
Lets develop equation representing time

behavior of vo .
6.002 Fall 2000
Lecture
21
Dynamics of op amp
vo = Av
vo
or v =
A
*
dv* *
RC
+ v = v+ v_
dt
vo R1
+
= vo
R1 + R2
vo R3
v =
=
vo
R3 + R4
v+ =
RC dvo vo
+ = v+ v_
A dt A
+
= ( ) vo
neglect
or
dvo 1
A +
+
+
( ) vo = 0
dt RC RC
dvo
A +
+
( ) vo = 0
dt RC
time 1
or
dvo vo
RC
+ = 0 where T = +
A( )
dt T
vo ( 0 ) = 0
6.002 Fall 2000
Lecture
21
Consider a small disturbance to vo

(noise).
+
if >
T is positive
vo = K e
if
+
>
+
=
vo
stable
T is negative
vo = K e
if
t
T
t
T
unstable
T is very large
vo = K
neutral
unstable
neutral
stable
disturbance
Now, lets build some useful circuits with

positive feedback.
6.002 Fall 2000
Lecture 21
One use for instability: Build on the

basic op amp as a comparator
+ VS
v+
vo
VS
+ VS
vo
v+ v
VS
vo
v 0
6.002 Fall 2000
t
Lecture
21
Now, use positive feedback

vi
vo
R2
vo R1
v =
R1 + R2
+
v = 7.5
R1
vo = 15
vi
( vi = v ) > 7.5
v < v+
v < 7.5
v > 7.5
vo = 15
6.002 Fall 2000
e.g. R1 = R2
VS = 15
Lecture
v = 7.5
21
Now, use positive feedback

vi
vo
R2
vo R1
v =
R1 + R2
+
VS R1
v =
R1 + R2
+
R1
vo = +VS
15
vi
( vi = v ) > v +
e.g. R1 = R2
VS = 15
v < v+
v < 7.5
v > 7.5
vo = VS 15 v =
6.002 Fall 2000
Lecture
21
VS R1
R1 + R2
10
vo
15
VS
hysteresis
7 .5
Demo
vi
7 .5
15
VS
Why is hysteresis useful?

vi
v
o
e.g., analog
to digital
7.5
t
7.5
Demo
6.002 Fall 2000
Lecture
21
11
Without hysteresis
vi
7.5
analog
to digital
vo
vi
t
7.5
6.002 Fall 2000
Lecture
21
12
Oscillator can create a clock

R
vC
vo
R1
vo
2
R1
vo
VS
VS
2
v+
v
vC
VS
2
VS
Demo
6.002 Fall 2000
v+
Assume
Lecture
vo = VS
vC = 0
21
at t = 0
13
Clocks in Digital Systems

We built an oscillator using an op amp.
t
can use as a clock
Why do we use a clock in a digital system?
(See page 735 of A & L)
sender
receiver
clock
a
1,1,0?
When is the signal valid?

common timebase -- when to look at a signal
(e.g. whenever the clock is high)
Discretization of time
one bit of information associated with
an interval of time (cycle)
6.002 Fall 2000
Lecture
21
14
6.002
CIRCUITS AND
ELECTRONICS
Energy and Power
6.002 Fall 2000
Lecture
22
Why worry about energy?
small batteries
good
Today:
How long will the battery last?
in standby mode
in active use
Will the chip overheat and self-destruct?
6.002 Fall 2000
Lecture
22
Look at energy dissipation in

MOSFET gates
VS
R
+
+
vI
vO
C: wiring capacitance and

CGS of following gate
Let us determine
standby power
active use power
Lets work out a few related examples first.
6.002 Fall 2000
Lecture
22
Example 1:
V +
Power
+
V
V2
P = VI =
R
Energy dissipated in time T
E = VIT
6.002 Fall 2000
Lecture
22
Example 1:
for our gate
VS
VS
RL
RL
vO
vI high
vI low
RON
RON
VS
P=
RL + RON
6.002 Fall 2000
Lecture
vO
P=0
22
Example 2:
Consider
R1
S1
VS +
S2
R2
T
T1
T2
S1 closed S1 open
S 2 open
S 2 closed
t
Find energy dissipated in each cycle.

Find average power P.
6.002 Fall 2000
Lecture
22
T1 : S1 closed, S2 open
i
VS +
R1
+
vC
vC
VS
R1
VS
6.002 Fall 2000
assume
vC = 0 at t = 0
Lecture
VS
e
R1
t
R1C
22
Total energy provided by source during T1

T1
E = VS i dt
0
T1
VS
e
R1
0
t
R1C
dt
VS
R1C e
R1
t T1
R1C
0
T1
2
R
C
1
= C VS 1 e
C VS if T1 >> R1C
I.e., if we wait long enough
1
2
C VS stored on C ,
2
1
2
E1 = C VS dissipated in R1
2
6.002 Fall 2000
Lecture
22
Independent
of R!
T2 : S2 closed, S1 open
+
vC
R2
Initially, vC = VS
(recall T1 >> R1C)
So, initially,
1
2
energy stored in capacitor = CVS
2
Assume T2 >> R2C
So, capacitor discharges ~fully in T2
So, energy dissipated in R2 during T2
1
2
E2 = CVS
2
E1, E2 independent of R2 !
6.002 Fall 2000
Lecture
22
Putting the two together:

Energy dissipated in each cycle
E = E1 + E2
1
1
2
2
= CVS + CVS
2
2
E = CVS
energy dissipated in
charging & discharging C
Assumes C charges and discharges fully.

Average power
P=
E
T
CVS
=
T
= CVS f
frequency f =
6.002 Fall 2000
Lecture
22
1
T
10
Back to our inverter

VS
RL
vO
vIN
RON
What is P for the following input?
vIN
T
2
T
2
T
6.002 Fall 2000
t
1
T=
f
Lecture
22
11
Equivalent Circuit
RL
VS +
C
RON
What is P for the following input?

vIN
T
2
T
2
T
6.002 Fall 2000
t
1
T=
f
Lecture
22
12
What is P for gate?

We can show (see section 12.2 of A & L)
2
P=
VS
RL
2
+ CVS f
2( RL + RON )
(RL + RON )2
when RL >> RON

2
VS
2
P=
+ CVS f
2 RL
r
e
b
m
e
m
re
P STATIC
independent of f.
MOSFET ON half
the time.
6.002 Fall 2000
e
b
m
e
rem
P DYNAMIC
related to switching
capacitor
Lecture
22
13
What is P for gate?

when RL >> RON
2
VS
2
P=
+ CVS f
2 RL
In standby mode,
half the gates in a
chip can be
assumed to be on.
So P STATIC per
gate is still VS2 .
In standby mode,
f0,
so dynamic power
is 0
2RL
Relates to standby
power.
6.002 Fall 2000
Lecture
22
14
Some numbers
a chip with 106 gates clocking
C =1f F
at 100 MHZ
RL = 10 k
f = 100 10 6
VS = 5 V
25
15
6
P = 10 6
10
25
100
10
+
2 10
= 10 6 [1.25 milliwatts + 2.5 microwatts ]
problem !
1.25KW!
must get rid of this
VS 2
f
reduce VS
next
lecture
6.002 Fall 2000
2.5W
not bad
5 V 1V
2.5 W 150 mW
Lecture
22
15
6.002
CIRCUITS AND
ELECTRONICS
Energy, CMOS
6.002 Fall 2000
Lecture
23
Review
VS
RL
VS
P=
RL + RON
vO
vI
RON
T1: closed
T2: open R
open
closed
VS +
S1
S2
R2
1
T = T1 + T2 =
f
2
P = CVS f
Reading: Section 12.5 of A & L.

6.002 Fall 2000
Lecture
23
Review
VS
RL
Inverter
vO
vI
RON
1
Square wave input
T=
f
2
VS
2
P=
+ CVS f
2 RL
Demo
P STATIC
independent of f.
MOSFET ON half
the time.
P DYNAMIC
RL >> RON
T
>>" RC"
2
time constant
related to switching
capacitor.
In standby mode,
f0,
so dynamic power is 0
In standby mode, half

the gates in a chip can
be assumed to be on.
So P STATIC per gate is
still VS2 .
2RL
6.002 Fall 2000
Lecture
23
Review
P=
VS
2
+ CVS f
2 RL
Chip with 106 gates clocking at 100 MHz
C = 1 f F, RL = 10 K , f = 100 10 6 , VS = 5 V
2
5
6
15
2
6
P = 10
+ 10 5 100 10
3
gates 2 10 10
= 10 6 [1.25 milliwatts + 2.5 watts ]
1.25KWatts
problem !
independent of f
also standby power
(assume MOSFETs
ON if f 0)
must get rid of this!
6.002 Fall 2000
Lecture
2.5Watts
not bad
f
VS2
reduce VS
5V1V
2.5V150mW
23
How to get rid of static power

Intuition:
VS
i
VS
RL
RL
vO low
vI high
vI low
RON
vO high
MOSFET
off
idea !
VS
vI high
6.002 Fall 2000
vO low
Lecture
23
New Device PFET

N-channel MOSFET (NFET)
D
G
S
on when vGS VTN

off when vGS < VTN
e.g. VTN = 1V
P-channel MOSFET (PFET)

S
G
on when vGS VTP

off when vGS > VTP
e.g. VTP = -1V
5V
ON when
less than 4V
6.002 Fall 2000
Lecture
23

VS
vI
S
D
D
S
PU = pull up
vO
PD = pull down
works like an inverter!
IN
6.002 Fall 2000
OUT
Lecture
23

works like an inverter!
OUT
IN
vI = 5V (input high)
vI = 0V (input low)
VS = 5V
VS = 5V
RON p
+
vI = 5V
vO
RON n
= 0V
+
vI = 0V
vO
= 5V
Complementary
MOS
(our previous logic was called NMOS)
Called CMOS logic
6.002 Fall 2000
Lecture
23
Key: no path from VS to GND!

no static power!
Lets compute P DYNAMIC
VS
vI
T
vI
vO
closed for
vI high
closed for
vI low
RON p
VS +
From
6.002 Fall 2000
1
f =
T
RON n
P = CVS f
Lecture
23
For our previous example

C = 1 f F, VS = 5 V , f = 100 MHz , 1
2
P = CV S f
= 10
15
5 2 100 10 6
= 2 . 5 watts per gate

P = 2 . 5 watts for 10 6 gate chip
Gates
106
100 ~2.5
MHz watts
Pentium?
2x106
300
~15
MHz watts
PII?
2x106
600
~30
MHz watts
PII?
8x106
~240
1.2 GHz watts
25x106
~1875
3 GHz watts
6.002 Fall 2000
Lecture
PIII?
keep
all
else
same
!
p
s
ga
PIV?
23
10
How to reduce power

A VS
5V 3V 1.8V 1.5V
~PIV 170 watts better, but high
and use big heatsink

B Turn off clock when not in use.
C Change VS depending on need.
next time:
power supply
6.002 Fall 2000
Lecture
23
11
CMOS Logic
NAND:
VS
A
A B
0 0
0 1
1 0
1 1
Z
1
1
1
0
Z
A
B
5V
0V
G
6.002 Fall 2000
S
on
D
Lecture
5V
5V
G
23
S
off
D
12
In general, if we want to implement F

e.g. F = A B = A + B
VS
short when
A = 0 or B = 0,
open otherwise
short
when F
is true,
else open
A
B
Z
short
when F
is true,
else open
short when
A B is true,
else open
r
e
b
m
reme gans law
r
o
M
e
D
6.002 Fall 2000
Lecture
23
13
6.002
CIRCUITS AND
ELECTRONICS
Power Conversion Circuits

and Diodes
6.002 Fall 2000
Lecture 24
Power Conversion Circuits (PCC)

PCC
+
5V DC
PCC
+
5V DC
110V
60Hz
solar cells,
battery
3V
DC
DC-to-DC UP converter
Power efficiency of converter important,
so use lots of devices:
MOSFET switches, clock circuits,
inductors, capacitors, op amps, diodes
Reading: Chapter 17 of A & L.

6.002 Fall 2000
Lecture 24
First, lets look at the diode
VvD
iD = I S e 1
I S = 10 12 A
iD
+
vD
VT = 0.025V
Boltzmanns constant
temperature in Kelvins
charge of an electron
kT
VT =
q
iD
iD
vD
IS
vD
V
mV
Can use this exponential model with

analysis methods learned earlier
analytical
graphical
incremental
(Our fake expodweeb was modeled after this device!)
6.002 Fall 2000
Lecture 24
Another analysis method:

piecewiselinear analysis
PL diode models:
iD
iD 0 vD = 0
short
or
on
vD < 0 iD = 0
vD
open
or
off
Ideal diode model
6.002 Fall 2000
Lecture 24

Practical diode model
ideal with offset
0.6V
iD
Short segment
Open segment
iD = 0
6.002 Fall 2000
vD = 0
0.6V
Lecture 24
vD

Piecewiselinear analysis method
Replace nonlinear characteristic with

linear segments.
Perform linear analysis within each
segment.
6.002 Fall 2000
Lecture 24
Example
(We will build up towards an AC-to-DC converter)
0.6V
+
Consider
+
vI +
vO
vI
is a sine wave
6.002 Fall 2000
Lecture 24
Example
0 .6 V
+
Equivalent
circuit
vI +
vO
Short segment:
iD = (vI 0.6 ) / R
vI 0.6
0.6V
+ vI
vO = vI 0.6
Open segment:
iD = 0
vI < 0.6
+ vI
+
0.6V
vO = 0
6.002 Fall 2000
Lecture 24
Example
vI
vO
0.6
t
6.002 Fall 2000
Lecture 24
Now consider a half-wave rectifier

0.6V
+
vI +
+
R
vO
6.002 Fall 2000
Lecture 24
10
A half-wave rectifier
vI
diode on
diode off
vO
Demo
C
current
pulses
charging
capacitor
MITs supply shows

snipping at the peaks
(because current drawn
at the peaks)
6.002 Fall 2000
Lecture 24
11
se
Do not u
resistive
s!
el em en t
DC-to-DC UP Converter
i
+
VI +
DC
vS
C vO
switch
load
vS
S
closed
open
t
Tp
The circuit has 3 states:

I.
II.
III.
S is on, diode is off

i increases linearly
S turns off, diode turns on
C charges up, vO increases
S is off, diode turns off
C holds vO (discharges into load)
6.002 Fall 2000
Lecture 24
12
More detailed analysis

I. Assume i(0) = 0, vO(0) > 0
S on at t = 0, diode off
L
i
VI +
VI T
i (T ) =
L
vO
C
di
VI = L
dt
VI
slope =
L
i is a ramp
1
E = energy stored at t = T : Li( T )2
2
2
VI T 2
E =
2L
6.002 Fall 2000
Lecture 24
13
II. S turns off at t = T
diode turns on (ignore diode voltage drop)

L
vO
VI +
State III starts here
VI T
L
0
T T
TP
1
O =
LC
Diode turns off at T when i tries to go negative.
6.002 Fall 2000
Lecture 24
14
II. S turns off at t = T, diode turns on

Lets look at the voltage profile
VI T
L
0
T T
1
O =
LC
Capacitor voltage
ignore
diode
drop
O =
TP
vO
III.
vO (T )
1
LC
vO
0
T T
TP
Diode turns off at T when I tries to go negative.

6.002 Fall 2000
Lecture 24
15
II. S turns off at t = T, diode turns on

Lets look at the voltage profile
VI T
L
0
T T
1
O =
LC
Capacitor voltage
ignore
diode
drop
O =
TP
vO
III.
vO (T )
1
LC
vO
0
T T
TP
Diode turns off at T when I tries to go negative.

6.002 Fall 2000
Lecture 24
16
III. S is off, diode turns off

Eg, no load
+
VI +
C vO
C holds vO after T
i is zero
Capacitor voltage
vO
6.002 Fall 2000
Lecture 24
TP
17
III. S is off, diode turns off

Eg, no load
+
VI +
C vO
C holds vO after T
i is zero
until S turns ON at TP, and cycle repeats
I II III I II III
Thus, vO increases each cycle, if there is no load.
vO
vO (n)
TP 2TP 3TP
6.002 Fall 2000
Lecture 24
t
18
What is vO after n cycles vO(n) ?

Use energy argument (KVL tedious!)
Each cycle deposits E in capacitor.
1
2
E
=
L
i
(
t
=
T
)
2
2
1 VI T 2
E =
2
1 VI T
2 L
= L
2 L
After n cycles, energy on capacitor
2
nVI T 2
nE =
2L
1
This energy must equal CvO ( n )2
2
so,
or
2
1
nV
T
2
CvO ( n ) = I
2
2L
2
nVI T 2
vO ( n ) =
LC
1
O =
LC
vO ( n ) = VI T O n
6.002 Fall 2000
Lecture 24
19
How to maintain vO at a given value?

+
VI
vO
load
vO
pwm
control
change T
Tp
recall
compare
+ vref
VI T 2
E =
2L
Another example of negative feedback:

if
if
(v
(v
O
O
vref )
vref )
6.002 Fall 2000
then T
then T
Lecture 24
20
6.002
CIRCUITS AND
ELECTRONICS
Violating the Abstraction Barrier
6.002 Fall 2000
Lecture 25
Case 1: The Double Take
Problem
VO
0 1 Vi
expected
observed
VO 1
VO 1
huh?
6.002 Fall 2000
t
0
in forbidden region!
Lecture 25
(a) DC case
R
VO
V1
Vi
Vi = 5V DC
VO = 5V DC V1 = 5V DC
6.002 Fall 2000
Lecture 25
very high
impedance,
like open
circuit
OK
(b)
Step
R
VO
V1
Vi
very high
impedance,
like open
circuit
5V Vi
b.1
0V
b.3
5V
t=0
VO
not ok!
VO = 2.5V
t=0
b.2
2T
5V V1
looks ok!
t=0 T
6.002 Fall 2000
Lecture 25
t
4
2.5
....
Vi
characteristic
impedance
instantaneous R divider
finite propagation speed
of signals
5V
5V
5V
2T
6.002 Fall 2000
Lecture 25
0 T
Question: So why did our circuits work?
5V V1
rce
u
o
S
tion
a
n
i
Term
1. Look only at V1
O
DEM
2. Keep wires short

O
M
ire
E
w
D
l
l
ma
s
e
us
3. Termination
O
DEM at the
R
add
end
5V VO
0
le l
Paral ation
in
term
5V VO
2.5V
More in 6.014
6.002 Fall 2000
Lecture 25
Case 2: The Double Dip
Problem strange spikes on supply
OK
driving a 50
resistor!
0
V
driving a 50
resistor!
6.002 Fall 2000
input
Why?
Lecture 25
Drop across inductor

Ldi
dt
VS
V
Inverter current
v inductor
VS
solution
1. short wires
2. low inductance wires
3. avoid big current swings
6.002 Fall 2000
Lecture 25
Case 3: The Double Team, or,

Slower may be faster!
Problem
a given chip
worked,
but was slow.
ideal
actual
Lets try speeding it up by using stronger

drivers
ideal
actual
Disaster!
6.002 Fall 2000
Lecture 25
Why?
DEMO
Consider
ok
R1
R0
DEMO
R2
dV
dt
dV
C
dt
crosstalk!
6.002 Fall 2000
Lecture 25
10
How does this relate to chip?
Solution
DEMO
small
Load output!
6.002 Fall 2000
dV
dt
put cap on outputs of chip

jitter edges
slew edges
Lecture 25
11
Case 4: The Double Jump
Careful abstraction violation for the

better
Recall
Vo
Vi
expect
Vo
Vi
but, observe
Vo
Vi
6.002 Fall 2000
Lecture 25
12
Case 4: The Double Jump
Careful abstraction violation for the

better
5V
Vi
5V + 3V
5V
0V
6.002 Fall 2000
3V
Lecture 25
So, pullup has

stronger drive
as output rises
13

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6.

Introduction and Lumped Circuit Abstraction

6.002 Fall 2000

Lecturer: Prof. Anant Agarwal

Readings are important!

6.002 Fall 2000

Two homework assignments can

Chapter 1 of the book

6.002 Fall 2000

What is 6.002 about?

6.002 Fall 2000

Nature as observed in experiments

Physics laws or abstractions

Simple amplifier abstraction

Clocked digital abstraction

Mice, toasters, sonar, stereos, doom, space shuttle

6.002 Fall 2000

Lumped Circuit Abstraction

The Big Jump

Suppose we wish to answer this question:

6.002 Fall 2000

We could do it the Hard Way

6.002 Fall 2000

Instead, there is an Easy Way

First, let us build some insight:

I ask you: What is the acceleration?

6.002 Fall 2000

Instead, there is an Easy Way

First, let us build some insight:

6.002 Fall 2000

The Easy Way

Consider the filament of the light bulb.

how current flows inside the filament

its temperature, shape, orientation, etc.

Then, we can replace the bulb with a

for the purpose of calculating the current.

6.002 Fall 2000

The Easy Way

for the purpose of calculating the current.

R represents the only property of interest!

6.002 Fall 2000

The Easy Way

R represents the only property of interest!

R relates element v and i

called element v-i relationship

6.002 Fall 2000

R is a lumped element abstraction

6.002 Fall 2000

R is a lumped element abstraction

6.002 Fall 2000

must be defined. True when

6.002 Fall 2000

Must also be defined.

So lets assume this too

VAB defined when

6.002 Fall 2000

Lumped Matter Discipline (LMD)

Lumped circuit abstraction applies when

6.002 Fall 2000

6.002 Fall 2000

Lumped element examples

Exploding resistor demo