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PlaceandRoutewithSoCEncounter
PlaceandRoutewithSoCEncounter
Home| Labs

Version03
Datemodified:01/25/2004
Instructions(READCAREFULLY)
ImportantnoteforLab2experiments

1.PleasereadthroughthetutorialandworkwithSoCEncounterinparalleltoknowvariousknobsavailableinthetool.
2.AnSoCEncounterDesignFlowGuideandTutorialcanbefoundat/home/ostl/cs241w/software/SOC32/doc/soceflow/soceflow.pdf.Thiswill
provideyouwithalittleunderstandingofwhatthistoolisusedforandwhatitsfeaturesare.
3.Thetutorialmakesyouworkthroughastraight(floorplanplacerouteextractiontiminganalysis)flow(Flow1).SOCEallowsyoutoperform
incrementaloptimizationsateachofthesestepsandhenceinthelab,youwillbeworkingonanupdatedflowgivenatthebeginningoflab.This
flow,whileprincipallyidenticaltoFlow1,enhanceseachstepandperformsmoredetailedoptimizationsforimprovingtimingofthedesign.
4.Inthelabpart,youwillbeworkingontheenhancedflow(Flow2).YoucanchoosetoworkwiththeSOCEGUIortheSOCEcommandlineorboth
inparallel(asyoudidwithBuildGatesPKS).
Youcanperformexactlythesamesetofsteps(giveninFlow2)withboththeGUIandthecommandline.
5.Twoveryimportantreferencesare:
(a)TheSOCEuserguide,foundat/home/ostl/cs241w/software/SOC32/doc/encounter/encounter.pdf
(b)TheSOCEtextcommandreferencemanual,foundat/home/ostl/cs241w/software/SOC32/doc/fetxtcmdref/fetxtcmdref.pdf.Refertothese
documentsforhelp.
6.Duetocontinuousenhancementstoscripts,configfilesetc.,filenames/paths/defaultvaluesofitemsinthetutorialscreenshotsmay
differfromwhatyouwilluse.Donotpanic:).ThedirectorystructureusedforthislabisexactlythesameasyouusedinLab1.Youshould
beworkingfromthetopleveldirectory(thatcontainssrc/run/output/andcmd/directories)inorderfortheflowtoexecutesmoothly.
Youmightafacelittledifficultyinrunningthetutorialforthefirsttime,andthatisnotuncommon.
7. DownloadthetarpackageforLab2fromhere.Thispackageincludessynthesizednetlistinsrc/netlistdirectoryandtimingconstraintfileinsrc/sdc
directory.Youdonotneedtoperformsynthesisagaintoobtainthesefiles.
8. LinktoflashtutorialsonplaceandrouteusingSoCEnconter

ABSTRACT
ThislabwillstartwithanintroductiontutorialtotheplaceandrouteflowinSOCEncounter.CadenceSOCEncounterisaversatiletoolwhichtakesa
designfromtheRTLsignoffstagetotheGDSIIformat.Inthislab,wewillfirstfollowthetutorialtogetacquaintedwiththetoolsothatyougainan
understandingofthebasicplaceandrouteflow.Thelabsection(questions)arebasedonanenhancedflowthatperformsdetailedoptimizationsat
eachstage.Wewillrunthetoolwiththisflowtomeetspecifictiming/areaobjectives.
ForthistutorialweuseasynthesizedVerilogfile(.sv)oftheAEScorefromtheSynthesislab(providedinthetarpackageabove)alongwithArtisan
TSMC0.13umtimingandphysicallibraries.

1.Tutorial
Inthistutorial,weuseSOCEncounter(SOCE)3.2(v03.20p005_1)onx86serversrunningRedHatEnterpriseLinux.SOCEcanberuneitherfroma
commandlineorfromaGUI.Togetacquaintedwiththetool,wewillusetheGUIinitially.However,werecommendyourunthetoolfromthe
commandlineonceyouarefamiliarwithit.Thiswillhelpyouwritetclscriptsthatcanbeusedtoautomatetheflowandrunitinbatchmode,aswe
didinLab1.
Inthistutorial,wefollowthesectionoftheflowindicatedinorange.Startingwithinitializationandfileimport,weperformfloorplaning,placement
(withAmoebaPlace),andclocktreesynthesisandrouting(withNanoRoute).WethenperformRCextractionwiththeSOCEinbuiltextractorand
performtiminganalysiswiththeCommonTimingEngine.

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Initialization
Togetstarted,youneedtosetupyourenvironmentvariablesandorganizeyourdirectories.Forthistutorial,youareprovidedwitha.tar.gzpackage
containingallthefilesyouneed.FollowthesestepstoinitializeandrunSOCE.
Createdirectorystructure
[cs241wzz@ostl10~]$pwd
/home/ostl/cs241w/cs241wzz
[cs241wzz@ostl10~]$tarzxfLab2.tar.gz
[cs241wzz@ostl10~]$cdLab2
[cs241wzz@ostl10~/Lab2]$ls
cmd/output/run/src/

SetupSOCEenvironment
//SetpathstoSOCE3.2andothertools
[cs241wzz@ostl10~/Lab2]$source~/../public/cshrc

TostartSOCE
[cs241wzz@ostl10~/Lab2]$encounter(1)
[cs241wzz@ostl10~/Lab2]$encounternowin(2)
Use(2)ifyouexplicitlywanttoinitializeEncounterwithouttheGUI.
Ifyouuse(1),youwillgettheSOCEGUIaswellastheencounter>shell
ontheterminalfromwhichyouinitializedSOCE.(shownbelow)

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Hereisthedirectorystructureforyourreference.Theaesdirectorymaydifferonyoursystem,dependingonwhatnameyou
decidedtouseforyourtoplevelLab2directory.

Afterinitialization,theSOCEGUIshowsup.Thefirststepistoimportdesign,tech,library,LEFandconstraintfiles.Toimportfiles,clickonthethe
"Design"menu.
Theloaddesignmenupopsupandyoucanentertherelevantfilesintheboxprovided.Wedescribeeachtypeoffilesbelow.

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Inthe"Design"tab,loadallinputfilespertainingtothedesign.Thesefilescanbefoundinsimilarlocationstowhereyoufoundthemintheprevious
lab.Thecommandlineequivalentstothisstepcanbefoundincmd/encounter/aes_cipher_top.conf
EnterthesynthesizedVerilognetlistfileaes_cipher_top.svin"VerilogFiles".
TheILM(InterfaceLogicModeling)filesspecifytheinterfacenetlist(thisisoptional).Inourcase,youmayleavethisblank.
"Topcell"isthenameofthetoplevelVerilogmoduleinthesynthesizednetlist.
SpecifytheLEFfile(s)inthephysicallibrarysection.[LEFfile=tsmc13fsg_6lm.lef]
IntheFETechnologyfilessection,specifythetechnologyfile(.tech)thatcontainsgeometricandcapacitanceinformationofvariouslayersofthe
chosentechnology.[Techfile=tsmc13fsg_6lm.lef.tech]
IntheStd.CellLibrariessection,specifythelistoflibrarycelldumpfiles.[Celldumpfile=tsmc13fsg_6lm.lef.cdump]
FEtechfilesandStd.celllibraryfilesarecreatedfromLEFfilesusingtheutilityreadlef.Youcanfindmoreinformationabouttheutilityfromthe
SOCEmanual.
Loadtiminglibraries(.tlforSynopsys.lib)filesinthe"TimingLibraries"section.Thisspecifiesthetiminginformationofvariouscellsinthelibrary.
The"Footprints"sectionspecifiesthenamesofbuffer,delayelement,andinverternamesinthelibrary.Thissectionisoptional.
YoucanloadIOpinassignmentinformationinthe"IOinformation"section.Ifyoudonotspecifythis,IOassignmentwillbeperformedrandomly.We
stronglysuggestyoutosavetheIOassignmentaftertheinitialrunanduseitforeveryrunafterwards.
Thishelpsinstudyingtheimprovementinvariousstepsoftheflowstartingfromthesameinitialpoint.
The"CoreSpecDefaults"tabshowsthedefaultaspectratioandrowutilizationratioofthedesign.Thesearesetto1.0and0.6respectively.Youcan
changetheseparametersduringthefloorplanningstage.
Inthe"Timing"tab,youcanentertimingconstraintfiles,capacitancetablesforRCextraction,andotherrelatedparmeters.

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Forthistutorial,wewillonlyloadthetimingconstraintfile(whichweusedforsynthesis)andretainallthedefaultvalues.Formoreinformationon
changingthedefaultvalues,refertotheSOCEmanual.
Inthepowertab,youcanspecifynamesofthepowerandgroundnets(VDDandVSS)alongwiththetoggleratescalefactorforpoweranalysis.
ThisfactorsetsthescalingvaluethatisusedtomultiplythetogglerateinthePowerAnalysisformtoanewscaledvalue.Thedefaultvalueis1.0,
whichmeansthatnotogglescalingisdone.Youmayleavethisfieldblank.

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Underthe"misc"tab,thereareoptionsforenteringtheSignalStormdatabase,Fire'n'Ice(RCextractor)techfiles,CeltICdatabasefiles.

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However,wedonotusethesetoolsforcurrenttutorial,soyoucanleavetheseboxesempty.Clickon"OK"afteryouhaveenteredpathstoall
relevantfiles.IttakessometimeforSOCEtoloaddesignfiles,librariesandconstraints.Thesefilescanalsobeloadedfromthecommandline.You
canspecifyallinputfilesina.conffile(forexample,aes_cipher_top.conf)andusethefollowingcommandtoloadit.
encounter>loadConfigaes_cipher_top.conf
Thefileaes_cipher_top.confispresentincmd/encounter/directorywithallappropriatepathsset.Tosavetimeinfuturerunsyoucanwritethe
designimportprocesstoa.conffileusingthe"Save..."buttoninthebottomofdesignimportdialogbox.

Floor&Powerplanning
Inthisstep,weperformfloorplanningofthedesign.Toinitializethefloorplan,goto"Floorplan"andchoosethe"SpecifyFloorplan"option.

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Thefollowingmenupopsupandyoucanchoosevariousoptionstospecifyafeasiblefloorplan.Inthisstep,youwillspecifytheaspectratioofthe
die(usuallysetto1.0),therowutilizationratio,andthecoretoIOdistance,amongotheroptions.

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Theaspectratioisspecifiedusing"Ratio(H/W)".Thisratiois1.0bydefault.Thecoreutilizationcorrespondstotherowutilizationratioofthe
standardcells.Dependingonthetypeofdesign,thisnumberhastobespecifiedappropriately.Highutilizationratios(typically>0.75)resultinhigh
congestionduringroutingresultinginunroutabledesigns.
TheAEScoreisheavilyinterconnectdominated.Topreventcongestion,wechoosearowutilizationof0.6.Insubsequentruns,youcantry
increasingtherowutilizationandobserveitsaffectoncongestionandtiming.
Inthe"CoreMarginsby"section,youcanspecifythecoretoIOdistanceonallfoursidesofthecore.Thisnumberhastobechosenbasedonthe
numberofIOsinthedesign.IfthenumberofIOsistoolarge,thenthecoretoIOdistanceshouldbelargeenoughtoreduceIOdensityatthe
boundary.Inourtutorial,weuse15umspacings.
RowtoRowspacingcanbespecifiedin"StandardCellRows"box.Thedefaultvalueissetto0.0um.Afterloadinginallvalues,clickApply.Allthe
valueswillbeadjustedslightlytocreateafeasiblefloorplan(observethattheaspectratioischangedto0.99990525andthecoremarginwidthsare
changed).ClickOKtoclosethedialogbox.
Thenextstepintheflowispowerplanning.Inthisstep,youwillcreateapowerringandpowerstripestocreateapowerdistributionnetworkfor
cellsinthedesign.Clickon"FloorplanPowerPlanningAddRings".

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Thefollowingwindowpopsupandyoucanspecifytheringtypeandconfiguration.
Youcanplanthepowerdistributionnetworkinvariousmodestofacilitatecreationofvariousdesignstyles.Inthistutorial,werestrictourselvesto
corerings.
The"ringconfiguration"optionsspecifywhichmetallayerstouseforeachsideoftheringaswellasthedesiredwidthsandspacings.Wechoose
METAL4fortopandbottomsidesandMETAL3forleftandrightsides.Thewidthsandthicknessesoftheseshouldcorrespondtowirewidthsand
thicknessesinLEFfile.

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Afteryoucreatearing,createpowerstripes.Choose"FloorplanPowerPlanningAddStripes"fromthemenu.Thefollowingwindowpopsup.

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Settosetdistancespecifiesthedistancebetweentwosetsofstripesconnectingpowerrings.Powerstripesshouldbespacedcorrectly.Toomany
powerstripescreateroutingblockagewhichmakesroutingdifficult.Toofewpowerstripesresultsinpoorpowerdistributiontothecellsandwastes
wiringresourcesonthelowermetallayers.
Forthistutorial,enterasettosetdistanceof50um.Topreventpowerstripesfrombeingplacedalongtheedgesofthedie,youcanspecifyastripe
offsetboundaryvalue.ClickOKafteryouenterallrelevantvalues.
AlthoughfloorplaningcanalsobeperformedusingcommandlineequivalentsofGUIoperations,itisrecommendedthatyourinitialfloorplanbe
performedusingtheGUIsothattheusergainsabetterunderstandingoftheprocess.Therearevarioustools(pointer,resizing,reshaping,cloning
etc)thatyoucanalsousetodofloorplanning.MoreinformationontheuseofthesetoolscanbefoundintheSOCEmanual.
Yetanotherfloorplanningmethodisusingtheblockplacer.ThisanalyzestheconnectivitybetweenblocksandIOsandperformsfloorplanning.To
initializeit,choose"FloorplanPlaceBlocks/ModulesPlace"fromthemenu.ChoosetheoptionspresentinthewindowandclickonOK.Thetool
performsblockplacementanddisplaysoneofthepossiblefloorplansolutions.Youcanviewothersolutionsbychoosing"FloorplanPlace
Blocks/ModulesViewPlacementSolutions"fromthemenu.ClickOKtoacceptasolution.Showninthefigurebelowisonesuchfloorplansolution.
REMEBER:Thefloorplansolutionshownhere(obtainedbyblockplacement)cannotbereplicatedexactly.Itdependsonyourchoiceof
parameters.Thisisshownasanexampleofwhatyoumightget.Forlargehierarchicaldesigns,partitioningandfloorplanningarevery
crucialsteps.Thequalityoftheplacement,routingandthereforetimingdepends,toalargeextent,onthefloorplan.

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Placement
Inthisstep,youwillperformtimingdrivenplacementusingAmoebaPlace.Choose"Place"fromthePlacemenuandthefollowingwindowpopsup.

Choosetheplacementeffortlevel:prototyping,low,mediumorhigh.Ifyouaretryingtoevaluatethequalityofthepartitioningorfloorplanning
step,chooseprototyping.Forourtutorial,choosemediumeffort.Timingdrivenplacementisenabledbyclickingonthecheckboxlabeled"Timing
Driven".Check"SaveNewNetlist"tosavethemodifiednetlistwhichmayhavewithbuffersinsertedbytheplacer.
Tominimizecongestion,theplacercanalsoberunwithcongestionoptimizationturnedon.Thisoptionisnotavailableinthewindowyouseeabove.
Todothis,runthefollowingcommandfromtheencountershell.
encounter>amoebaPlaceslowtimingdrivendoCongOpt
Ittakessometimeforthetooltoperformtimingdrivenplacementwithcongestionoptimization.Themodifiednetlistwillbesavedtothefile
aes_cipher_top.post_tdp.v.*YoucanviewtheplacementusingtheGUIafterthisstep.Youcandoubleclickonaparticularcelltoviewitsproperties
(location,size,name,#ofconnectionsetc.).

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Afterperformingplacement,addfillercellstomakethechipuniformlydense.Choose"PlaceFillerAddFiller"fromthemenu.Specifythe
namesoftypesfillercellsinthefollowingwindow.

AfteraddingFILL64cells,addFILL32,FILL16,FILL8,FILL4,FILL2andFILL1,inthatorder.

ClockTreeSynthesis
Toperformclocktreesynthesis(CTS),afilecontainingclockspecificationsneedstobeimportedtoSOCE.Thisfileisalreadyincludedtheinsrc/cts/
directory.Foryourreference,itisshownbelow
#ClockSynthesisFile
AutoCTSRootPinclk
NoGatingNO
MaxDelay2.5ns
MinDelay2ns
MaxSkew100ps
MaxDepth20
BufferCLKBUFX20CLKBUFX16CLKBUFX12CLKBUFX8CLKBUFX2
End
Thisfilespecifiestheclocksignalnames,maximumrequireddelay,minimumrequireddelay,maximumclockskewbetweenleafnodes,andtree
depth,amongotherparameters.FormoreinformationonallavailableoptionsrefertotheSOCEmanual.Importtheclocktreespecificationfileby
selecting"ClockSpecifyClockTree"fromthemenu.Synthesizetheclocktreebychoosingthe"SynthesizeClockTree"optionfromtheClock

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menu.Thefollowingwindowshows.

ClickOKtostartckSynthesis(theutilityequivalenttoCTGen).Ittakessometimetocompleteclocktreesynthesis.Thelogfileofthesynthesisrun
isproducedinhtmlformat.Youcanviewthereportfilesusinganywebbrowser.Ifthereportmentionsanyviolations,thentheclocktree
specificationshavetobemodifiedandckSynthesisshouldbererun.

Nanoroute
AfterCTS,starttheglobalanddetailroutingusingNanoroute.Choose"Nanoroute"fromtheRoutemenu.Thefollowingwindowpopsup.

Choosethetimingdrivenoption.ThisperformsseveraliterationsoftheroutingwithfastRCextractionandtiminganalysistoimprovetimingslack.
ClickonOKtostartNanoroute.Ittakessometimefortheroutingtocomplete.Thetoolperformsviolationchecks,DRC(DesignRuleChecking)and
reportserrorsandwarningsaftertheprocessiscomplete.Thefollowingfiguredisplaystherouteddesign.

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Youcanviewdesigninformationandnetstatisticsusingoptionsin"Tools"menu.Thereisanoptiontochooseindividualnetsandobtaintheir
statistics.

RCExtractionandTimingAnalysis
Toverifyifthechipmeetstimingornotandtostudytimingslacksofpathsinthedesign,weperformparasiticextractionandstatictiminganalysis.
Todothis,weusethesimple2.5DRCextractorbuiltintoSOCE.Amoreaccurate3DRCextractor(Fire'n'Ice)canbeusedtoperformsignoff
qualityextraction.Forourcurrentrun,westickwiththesimpleRCextractor.Toperformextraction,choose"TimingExtractRC".

SelecttheoptionsshownaboveandthenclickOKtoperformRCextraction.Dependingonthesizeofthedesign,thismaytakesometime.AfterRC
extractioniscomplete,doadelaycalculation.Tocalculatedelay,choose"TimingCalculateDelay".Storethedelayvaluestoaes_cipher_top.sdf.
ThisfilewillbeusedinStaticTimingAnalysis(STA).
Thenextstepinthedesignflowistiminganalysis.Beforeperformingtiminganalysis,settheoperatingconditions.Choose"TimingSpecify
AnalysisConditionSpecifyOperatingCondition".

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Choose"timinglibrary:slow"underthemaxtaband"timinglibrary:fast"formintabandclickOK.Thestatictimingtool(CommonTimingEngine)
performstiminganalysisundertheseoperatingconditions.Timinganalysiscanbeperformedbyexecutingfollowingcommandsattheencounter
shell.
encounter>buildTimingGraph
Reporttimingslacksandviolationsafterbuildingthetiminggraphbyusingthefollowingcommands
encounter>setCteReport
encounter>reportTAsummaryoutfileaes_cipher_top_TD.tarptnworst50
encounter>reportTAoutfileaes_cipher_top_TD.slacknworst50
Viewthetimingandviolationreportstoobservetimingslacksforvariouspathsandseeifthedesignmettiming.Youcanviewvarious"worstcase"
pathsbystartingtheslackbrowser.Choose"TimingReportTimingSlacks"firstandcreatea.slkfile.Then,youcangoto"TimingTiming
DebugSlackBrowser"toinitializetheslackbrowser.Apopupwindowopensaskingfortheslackreportgeneratedinthepreviousstep.Afterthis
fileisimported,youcanviewthevarioustimingpathsinthedesignbyhighlightingthepathsintheslackbrowser.
**************ENDOFTUTORIAL*******************

2.LAB
Inthispart,youwillrunSOCEonthesynthesizedAEScoretomeetvarioustimingandareaobjectiveswithanenhancedflow.Theflowandthe
associatedcommand(.tcl)filesareexplainedbelow.

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Note:Individualstepsareindicatedinorangeboxes.Yellowboxesrepresentdetailedproceduresofmainstepsoutlinedbytheredboxes.
1.Step1oftheflowperformsinitializationofenvironmentvariables,setspathstodirectories.Oneimportantfilethatisusedforinitializationis
aes_cipher_top.conf.Thisfileispresentinthecmd/encounterdirectoryandisusedtosetpathstolibraries,timingcostraintfiles,rowutilization
andotherparameters.Openthefileinatexteditortoviewallavailableitems.Youcanchangethisfiletosuityourexperiments.(file:
cmd/encounter/01_ini.tcl)
2.Step2oftheflowsetstiminganalysisparameters(referto"setCteReport"intextcommandmanual)(file:cmd/encounter/02_timing.tcl)
3.Step3performsblockplacementandfloorplanning.Youcanchoosetoperformthesestepsmanuallytohaveabetterviewofthefloorplanand
blockplacementsolutions.(file:cmd/encounter/03_floorplan.tcl)
4.Step4performspowerplanning.Itaddspowerringsandpowerstripesinthedesign.Again,youcanchoosetodothesemanually.(file:
cmd/encounter/04_power.tcl)
5.Step5(redbox)doesplacementwithamoebaPlaceinthetimingdriven,congestionoptimizationmode.Thisisfollowedbytrialrouteandparasitic
extraction.Thisisdoneinordertoevaluatethequalityofplacement.Timinganalysisisperformedwiththeextractedparasitics.(file:
cmd/encounter/05_place.tcl)
6.Step6performsIPO(Inplaceoptimization)oftheplaceddesigninordertoimprovedesigntiming.Inthisstep,theIPOmodeissetupandsetup
timeviolationsarefixed(withoperationssuchasbuffering,resizingandcloning).Toevaluatetheimprovementintiming,trialroute,RCextraction,
andthentiminganalysisareperformed.(filecmd/encounter/06_ipo1.tcl)
7.Step7performsclocktreesynthesis.ClocktreeanalysisisperformedafterCTStoevaluateitsquality.Sincetheclocktreenowexists,thedesign
istrialroutedwiththeclocktreeandtiminganalyzed.(file:cmd/encounter/07_cts.tcl)
8.Step8fixesofsetupandholdtimeviolationsafterclocktreesynthesis.(file:cmd/encounter/08_ipo2.tcl)

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9.Step9performsroutingofpowerandgroundwiresincellsandconnectsthemtopowerstripes.(file:cmd/encounter/09_routepower.tcl)
10.Toensurethecontinuousconnectionofpowerandgroundlinesthatrunonthetopsandbottomsofstandardcellrows,fillercellsareintroduced
incellgaps.Thisisperformedinstep10.(file:cmd/encounter/10_addfiller.tcl)
11.InStep11,youspecifyvariousroutingattributesandnanoRouteoptionstoperformwirerouting.Foradetaileddescriptionofoptionsand
attributes,refertotheSOCEmanualandtextcommandreference.(file:cmd/encounter/11_route.tcl)
12.Wiringconnectivityandcellgeometriesareverifiedinstep12.Violationsarereported.(file:cmd/encounter/12_verify.tcl)
13.Instep13,afinaltiminganalysisisperformedafterdetailedRCextraction.Aftertiminganalysis,theDEFfileandmodifiednetlistofthedesign
areexportedtooutputdirectories.(file:cmd/encounter/13_write.tcl)
RunningSOCEfromthecommandline(encountershell)
Eachoftheabovestepscanberunsequentiallybysourcingthetclfilescorrespondingtoeachstep
encounter>sourcecmd/encounter/01_ini.tcl
Thereisafilecalled"do_encounter.tcl"thatsourcesallthesefilesandrunsthedesignthroughtheflowmentionedabove.Youmightwanttoopen
theGUIsessioninparalleltoobservechangesinthedesignasitprogressesthroughvariousstages.Youcancontroltheflowbymodifyingoptionsin
thetclfiles.Formoreinformationonallavailableoptionsrefertothetextcommandreferencemanual.

Experiments
Foreachquestion,pleaseexplainnotonlyWHAThappened,butWHYyouthinkithappened.
Forexample,"Changingconstraintxcausedytohappen"onlyexplainswhat,butnotwhy."Changingconstraintxmeantthatthesynthesizerhadto
doa,b,andcbecauseifitdidnot,thegoaldwouldnothavebeenmet.Aswecansee,doinga,b,andctothedesigncausedustoobserveyinthe
results."ismorealongthelinesofwhatwe'relookingfor.
Youwillgetmorepointsforalogicalandwellthoughtoutobservation,evenifit'sincorrect,thanyouwillfornotprovidingoneatall.

Q1.Inthisexercise,youwillstudytheeffectofplacement(andplacementknobs)onthetimingandcongestionofthedesign.Runtheplaceandrouteflow
(specifiedabove)ontheaescorewithrowutilizationsetto50%andthefollowingoptionsforamoebaPlace
1.amoebaPlacetimingdrivenlowEffort
2.amoebaPlacetimingdrivenhighEffort
3.amoebaPlacetimingdrivenhighEffortdoCongOpt>theflagdoCongOptperformscongestionoptimization
4.amoebaPlacelowEffort
Foreachoftheseruns,dumpcongestioninformationusingthe
dumpCongestAreaallcongestionMap.txt
commandAFTERROUTING.Foreachoftheaboveruns,reporttiming,congestionandruntime(foramoebaPlace+NanoRouteonly)inatable.Youcan
getruntimesfromtheencounter.logfileproducedaftereachrun.Deliverable:(a)theencounter.logfileofeachofthefourruns(b)Areportofyour
observationsexplainingthereasonforthedegradation/improvementintimingdueuseofvariousknobsinplacement.
Q2.Inthisexercise,youwillstudytheeffectofrouting(andvariousknobs)usingNanoRouteontiming,congestionandsignalintegrityofthedesign.Run
theplaceandrouteflow(specifiedabove)withthefollowingoptionsforNanoRoute.YoucanspecifyattributesforNanoRouteusingeithertheGUIorthe
commandline
setNanoRouteMode
Formoreinformation,refertotheSOCEtextcommandreferencemanual.
1.FixantennaON+TimingDrivenON+TimingOptimizationOFF
2.FixantennaON+TimingDrivenOFF+TimingOptimizationON+SIDrivenON(LowEffort)
3.FixantennaON+TimingDrivenOFF+TimingOptimizationON+SIDrivenON(HighEffort)
4.FixantennaOFF+TimingDrivenOFF+TimingOptimizationOFF+SIDrivenON(HighEffort)
5.FixantennaOFF+TimingDrivenOFF+TimingOptimizationOFF+SIDrivenOFF(justplainglobalanddetailedroute)
Performatiminganalysisafterplaceandrouteineachoftheseruns.Verifyconnectivityandgeometryforeachoftheseusingthe"Verify"menuofSOCE.
Obtaindesignstatisticsfrom"Tools"menuofSOCE.Foreachoftheserunscollectthefollowinginformation.
Worsttimingslack,runtime(onlyforrouting),congestioninformation,#ofviolations,totalcellarea
Deliverable:(a)encounter.logfileofeachofthefiveruns(b)Areportofyourobservationsexplainingdegradation/improvementintiming,congestion,#
violationsandtotalcellareaofthedesign.Pleasetrytoprovideobservationsinatabularformforimprovedreadability.
Q3.IfyouhavesolvedQ1andQ2already,thenyouhavesomeideaof"goodpractices"formeetingtimingofadesign.Thisquestionattemptsto
letyouexplorevarioustooloptionstomeettiming.
Runplaceandroutewithrowutilizations=50%,60%,70%andperformtiminganalysis.Youshouldattempttomeettimingrequirementswitha
3.6nsclock.Youareprovidedwiththetimingconstraintstouseintimingdrivenplaceandroute.Toeasecongestion,performplacementinthe
congestionoptimizationmode.Youmayormaynotmeettiming,butyoushouldtrytominimizeveslackasmuchaspossible.
Iwasabletomeettimingwithasmall+veslackonlyforrowutilization=50%.Meetingtimingwith60%and70%rowutilizationisnontrivial.
Duetoarelativelyhighutilizationratio,therewillbeincreasedparasiticsduetowiresbeingclosetogether.whichresultsintimingdegradation.Try
toexperimentwithdifferentfloorplans(blockplacementsolutions),performcongestionoptimizationanditerativelyimproveplacementandthe
routingsolutiontoimproveparasitics.
Deliverable:(a)Commandfiles(encounter.cmd),scripts(whichyoumighthaveused)andencounter.logfilesforthebestrunyouhadforeach
valueofrowutilization.

http://vlsicad.ucsd.edu/courses/ece260bw05/Lab2/Lab2.php

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http://vlsicad.ucsd.edu/courses/ece260bw05/Lab2/Lab2.php

PlaceandRoutewithSoCEncounter

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