Ch1 Figs

Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE

Define circuit inputs
and outputs
(Circuit specifications)
Hand calculations
and schematics
Circuit simulations
Does the circuit

meet specs?
No
Yes
Layout
Re-simulate with parasitics
No
Does the circuit

meet specs?
Yes
Prototype fabrication
Test and evaluate
No, fab problem
Does the circuit

meet specs?
No, spec problem
Yes
Production
Figure 1.1 Flowchart for the CMOS IC design process.
A dice fabricated with other die on the silicon wafer
Enlarged
Wafer diameter is typically 100 to 300 mm.
Top (layout)
view
Side (cross-section)
view
200 mm wafer
(8 inches)
Figure 1.2 CMOS integrated circuits are fabricated on and in a silicon wafer.
(a)
Chip
(b)
Bond wire
Bonding pad
Epoxy to hold
chip in place
Figure 1.3 How a chip is packaged (a) and (b) a closer view.
Chips placed on a lead frame.
Chip
Detail
A plastic "puck"
melted to form
a package.
Packaged parts prior to bending the pins into place.
Final parts sent to customer.
Figure 1.4 Plastic packages are used (generally) when the chip is mass produced.
Cut pie here
(a) Layout view
(b) Cross-sectional view

Figure 1.5 Layout and cross sectional view of a pie (minus pie tin).
Figure 1.6 Starting LASI using the MOSIS setups.
Cell name and rank
Load or create a cell

(clicking on the word or
picture results in the same action)
The mouse can be toggled between a cross and

and crosshairs by pressing the tab button.
Reference marker (drawings origin)
Location of the mouse
Toggles display
of the reference
marker
Figure 1.7 Screen after making a cell called "test" with a rank of 1.
Figure 1.8 Navigating in LASI (see text).
Figure 1.9 Drawing a box using LASI.
Figure 1.10 Showing how the working and dot grids are set in LASI using the
Cnfg command.
Test cell outline (notice it's small)
Object indicates the test cell
Figure 1.11 Adding the test cell with a rank of 1 to the test2 cell with a rank of 2.
Figure 1.12 Adding several "test" cells with a rank of 1 to the "test2" cell with
a rank of 2.
Figure 1.13 Going back to the "test" cell and adding a additional n-well box.
Figure 1.14 How the change to the "test" cell propagates up through the hierarchy.
Vertices of the polygon
Notice
Figure 1.15 Drawing a polygon in LASI on the POL1 (polysilicon) layer.
Closing the polygon in Fig. 1.15
Vertices
Drawing a path with a

width of 4.
Figure 1.16 Closing the polygon in Fig. 1.15 and drawing a path object with a width of 4.
Text vertex
Figure 1.17 Adding text to a layout.
Figure 1.18 Setting up the Fkeys to speed up layout.
Boxes
Cells
Figure 1.19 Editing a cell in place.
Figure 1.20 The LASI System Screen.
Scale factor
Figure 1.21 Generating a GDS file from a TLC file.
Putting the file name with

extension (cir) in quotes
won't tack on the gratuitous
.txt to the end of the filename.
Figure 1.22 Saving a text file with a ".cir" extension.
Opening
a circuit
netlist.
Figure 1.23 Opening a file with WinSPICE.
Vin
Vin, 1 V
R1, 1k
Vout
R2, 2k
Figure 1.24 Simulating the operation of a resistive divider.
Vin
Vout
Figure 1.25 Simulating the circuit in Fig. 1.24.
Vin
Vin
1V (peak) at
1 MHz
R1, 1k
Vout
R2, 2k
Figure 1.26 Simulating the operation of a resistive divider with a sinewave input.
Vin
0 to 1 V
delay 6ns
time at 1 V = 3 ns
period = 10 ns
R1, 1k
Vout
C1,
1p
Figure 1.27 Simulating the step response of an RC circuit using a pulsed source voltage.
1k
An input pulse.
1p
1k
Figure 1.28 Circuit used in Problem 1.16
Figure 1.6 Discrete NMOS device from US Patent 3,356,858 [1]. Note the metal
gate and the connection to the MOSFET's body on the bottom of the
device. Also note that the source and body are tied together.
Figure 1.7 Discrete PMOS device from US Patent 3,356,858 [1].
Figure 1.8 Inverter schematic from US Patent 3,356,858 [1].
Putting the file name with

extension (cir) in quotes
won't tack on the gratuitous
.txt to the end of the filename.
Figure 1.9 Saving a text file with a ".cir" extension.
node 1
Vin, 1 V
R1, 1k
node 2
R2, 2k
Figure 1.10 Operation point simulation for a resistive divider.
Vin
Vin, 1 V
R1, 1k
Vout
R2, 2k
*** Figure 1.11 CMOS ***

*#destroy all
*#run
*#print all
.op
Vin Vin 0 DC 1
R1 Vin Vout 1k
R2 Vout 0 2k
.end
Figure 1.11 Operation point simulation for a resistive divider.
Vin
R1, 1k
R2, 2k
Vin, 1 V

*#destroy all
*#run
*#print all
.TF I(Vmeas) Vin
Vin Vin 0 DC 1
R1 Vin Vout 1k
R2 Vout Vmeas 2k
Vmeas Vmeas 0 DC 0
.end
Vout
I(Vmeas)
Vmeas, 0 V
Figure 1.12 Measuring the transfer function in a resistive divider when the output
variable is the current through R2 and the input is Vin.
1k
Vt
Vout
Vin
23
1V
Vb
2k
3k
Figure 1.13 Example using a voltage-controlled voltage source.
n3
n1
n2
G, gain
n4
Voltage-Controlled Current Source (VCCS)

G1 n3 n4 n1 n2 G
Figure 1.14 Voltage-controlled current source in SPICE.
Rf, 3k
Vout
Rin, 1k
1MEG
1 ohm
Vin, 1V
Ideal op-amp
Rf, 3k
Rin, 1k
Vout
Vin, 1V
Figure 1.15 An op-amp simulation example.
Vin
Vin, 1 V
R1, 1k
Vout
R2, 2k

*#destroy all
*#run
*#plot Vin Vout
.dc Vin 0 1 1m
Vin Vin 0 DC 1
R1 Vin Vout 1k
R2 Vout 0 2k
.end
Vin
Vout
Vin
Figure 1.16 DC analysis simulation for a resistive divider.
1k
Vin
Vin
Vd
Id
Vd

*#destroy all
*#run
*#let ID=-Vin#branch
*#plot ID
.dc Vin 0 1 1m
Vin Vin 0 DC 1
R1 Vin Vd 1k
D1 Vd 0 mydiode
.model mydiode D
.end
Id
Vd
Figure 1.17 Plotting the current-voltage curve for a diode.
Vce
Vb
Ib
Vce

*#destroy all
*#run
*#let Ic=-Vce#branch
*#plot Ic
.dc Vce 0 5 1m Ib 5u 25u 5u
Vce Vce 0 DC 0
Ib 0 Vb DC 0
Q1 Vce Vb 0 myNPN
.model myNPN NPN
.end
Ib=25u
Ib=20u
Ib=15u
Ib=10u
Ib=5u
Figure 1.18 Plotting the current-voltage curves for an NPN BJT.
Vin
Vout
Figure 1.19 Transient simulation for the circuit in Fig. 1.11.
Vin
Vin
1V (peak) at
1 MHz
R1, 1k
R2, 2k
Vout
*** Figure 1.20 ***

*#destroy all
*#run
*#plot vin vout
.tran 1n 3u
Vin Vin 0 DC 0 SIN 0 1 1MEG
R1 Vin Vout 1k
R2 Vout 0 2k
.end
Figure 1.20 Simulating a resistive divider with a sinusoidal input.
Vin
R, 1k
*** Figure 1.21 ***

*#destroy all
*#run
*#plot vin vout
.tran 10u 30m
Vin Vin 0 DC 0 SIN 0 1 200
R1 Vin Vout 1k
CL Vout 0 1u
.end
Vout
Vin
1V (peak) at
200 Hz
C, 1uF
Vin
Vout
Figure 1.21 Simulating the operation of an RC circuit using a .tran analysis.
Vin
Vin
1V (peak) at
200 Hz
C1, 2uF
R, 1k
Vout
C2, 1uF
*** Figure 1.22 ***

*#destroy all
*#run
*#plot vin vout
.tran 10u 30m
Vin Vin 0 DC 0 SIN 0 1 200
R1 Vin Vout 1k
C1 Vin Vout 2u
C2 Vout 0 1u
.end
Figure 1.22 Another RC circuit example.
20 log (0.623) = 4.11 dB
51.5 degrees
200 Hz
Figure 1.23 AC simulation for the RC circuit in Fig. 1.21.
Vin
0 to 1 V
delay 6ns
time at 1 V = 3 ns
period = 10 ns
R1, 1k
Vout
C1,
1p
Figure 1.24 Simulating the step response of an RC circuit using a pulsed source voltage.
Figure 1.25 Specifying a rise time in the pulse statement to avoid slow rise times
(rise times set by the maximum step size in the .tran statement.)
Figure 1.26 Step response of an RC circuit.
Figure 1.27 Another step response (negative going) of an RC circuit.
Vin
PWL 0 0.5 3n 1 5n 1 5.5n 0 7n 0
R1, 1k
C1,
1p
PWL
Vin
Vout
Vout
Figure 1.28 Using a PWL source to drive an RC circuit.
s1 node1 node2 controlp controlm switmod

node1
s1
ron
node2
The switch is closed when the node voltage controlp

is greater than the node voltage controlm
Figure 1.29 Modeling a switch in SPICE.
R1, 1k
Vin
C1,
1p
5V
*** Figure 1.30 ***
Vout
Initially at 2V
At t=2ns switch closes
*#destroy all
*#run
*#plot vout
.tran 100p 8n UIC
Vclk clk 0 pulse -1 1 2n
Vin Vin 0 DC 5
S1 Vin Vouts clk 0 switmodel
R1 Vouts Vout 1k
C1 Vout 0 1p IC=2
.model switmodel sw ron=0.1
.end
Figure 1.30 Using initial conditions and a switch in an RC circuit simulation.
Vin
R1, 1k
5V
Vout
10 uH
At t=2ns switch opens

(assume switch was
closed for a long time.)
1k
*** Figure 1.31 ***

*#destroy all
*#run
*#plot vout
.tran 100p 8n UIC
Vclk clk 0 pulse -1 1 2n
Vin Vin 0 DC 5
S1 Vin Vouts 0 clk switmodel
R1 Vouts Vout 1k
R2 Vout 0 1k
L1 Vout 0 10u IC=5m
.model switmodel sw ron=0.1
.end
Figure 1.31 Using initial conditions in an inductive circuit.
*** Figure 1.32 ***
Vout
AC 1
1k
10 nH
*#destroy all
*#run
*#plot db(vout)
10 pF
.AC lin 100 400MEG 600MEG

Iin Vout 0 DC 0 AC 1
R1 Vout 0 1k
L1 Vout 0 10n
C1 Vout 0 10p
.end
Figure 1.32 Determining the Q, or quality factor, of an LC tank.
1uF
Vin
*** Figure 1.33 ***
1k
Vout
*#destroy all
*#run
*#plot db(vout/vin)
*#set units=degrees
*#plot ph(vout/vin)
.ac dec 100 1 10k
Vin Vin 0 DC 1 AC 1
Rin Vin vm 1k
Cf Vout vm 1u
X1 Vout 0 vm Ideal_op_amp
.subckt Ideal_op_amp Vout Vp Vm
G1 Vout 0 Vm Vp 1MEG
RL Vout 0 1
.ends
.end
Figure 1.33 An integrator example.
1uF
Vin
*** Figure 1.34 ***
1k
Vout
*#destroy all
*#run
*#plot vout vin
.tran 10u 10m
.ic v(vout)=0
Vin Vin 0 DC 1
+ pulse -1 1 0 1u 1u 2m 4m
Rin Vin vm 1k
Cf Vout vm 1u
X1 Vout 0 vm Ideal_op_amp
.subckt Ideal_op_amp Vout Vp Vm
G1 Vout 0 Vm Vp 1MEG
RL Vout 0 1
.ends
.end
Figure 1.34 Time-domain integrator example.

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Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition

By R. Jacob Baker, Copyright Wiley-IEEE

Does the circuit

Does the circuit

Test and evaluate

No, fab problem

Does the circuit

No, spec problem

Wafer diameter is typically 100 to 300 mm.

Packaged parts prior to bending the pins into place.

Final parts sent to customer.

Cut pie here

(a) Layout view

(b) Cross-sectional view

Figure 1.6 Starting LASI using the MOSIS setups.

Cell name and rank

Load or create a cell

The mouse can be toggled between a cross and

Reference marker (drawings origin)

Location of the mouse

Figure 1.8 Navigating in LASI (see text).

Figure 1.9 Drawing a box using LASI.

Test cell outline (notice it's small)

Object indicates the test cell

Vertices of the polygon

Figure 1.15 Drawing a polygon in LASI on the POL1 (polysilicon) layer.

Closing the polygon in Fig. 1.15

Drawing a path with a

Figure 1.17 Adding text to a layout.

Figure 1.18 Setting up the Fkeys to speed up layout.

Figure 1.19 Editing a cell in place.

Figure 1.20 The LASI System Screen.

Figure 1.21 Generating a GDS file from a TLC file.

Putting the file name with

Figure 1.22 Saving a text file with a ".cir" extension.

Figure 1.23 Opening a file with WinSPICE.

Figure 1.24 Simulating the operation of a resistive divider.

Figure 1.25 Simulating the circuit in Fig. 1.24.

Figure 1.28 Circuit used in Problem 1.16

Figure 1.7 Discrete PMOS device from US Patent 3,356,858 [1].

Figure 1.8 Inverter schematic from US Patent 3,356,858 [1].

Putting the file name with

Figure 1.9 Saving a text file with a ".cir" extension.

Figure 1.10 Operation point simulation for a resistive divider.

*** Figure 1.11 CMOS ***

Figure 1.11 Operation point simulation for a resistive divider.

*** Figure 1.12 CMOS ***

Figure 1.13 Example using a voltage-controlled voltage source.

Voltage-Controlled Current Source (VCCS)

Figure 1.15 An op-amp simulation example.

*** Figure 1.16 CMOS ***

Figure 1.16 DC analysis simulation for a resistive divider.

*** Figure 1.17 CMOS ***

Figure 1.17 Plotting the current-voltage curve for a diode.

*** Figure 1.18 CMOS ***

Figure 1.18 Plotting the current-voltage curves for an NPN BJT.

Figure 1.19 Transient simulation for the circuit in Fig. 1.11.

*** Figure 1.20 ***

Figure 1.20 Simulating a resistive divider with a sinusoidal input.

*** Figure 1.21 ***

Figure 1.21 Simulating the operation of an RC circuit using a .tran analysis.

*** Figure 1.22 ***

Figure 1.22 Another RC circuit example.

* Figure 1.11 CMOS *

* Figure 1.12 CMOS *

* Figure 1.16 CMOS *

* Figure 1.17 CMOS *

* Figure 1.18 CMOS *

* Figure 1.20 *

* Figure 1.21 *

* Figure 1.22 *

* Figure 1.30 *

* Figure 1.31 *

* Figure 1.32 *

* Figure 1.33 *

* Figure 1.34 *