RECONFIGURABLE SEQUENCE DETECTOR IP CORE

Hitesh Prasad, Bhomesh Dewangan, Shekhar Dwivedi, Nandakumar.R

National Institute of Electronics and Information Technology (NIELIT), Calicut, Kerala, India
hitesh_bprasad@yahoo.co.in, bhomeshdwngn083@gmail.com, shekhardwivedi25@gmail.com, nanda24x7@gmail.com

Abstract: This paper presents FSM based design of a

Reconfigurable Sequence detector which detects the bit
sequence having any number of bits i.e. (from 2 to 8).
Also the bit pattern is Reconfigurable i.e. the bit pattern
is selected by user and whenever that particular bit
pattern is found in incoming bit stream the system will
detect that bit pattern. This paper provides a
synthesizable reconfigurable sequence detector ip core
which can be made available as COTS for a variety of
applications involving SoC integration. This design is
implemented in Verilog HDL and simulated in
ModelSim. The design is synthesized using Altera
Quartus II and functional hardware testing is done on
FPGA.

II.

Reconfigurable Sequence Detector

The Reconfigurable Sequence Detector allows us to

reconfigure a sequence detector for another bit pattern
which having number of bits from 2 to 8. The details
have been explained in subsequent sections.

i.

Input Output Block Diagram

Keywords: Pattern Detection, FSM, IP Core

I.

Introduction

In a computer network like Ethernet, digital data is sent

one bit at a time, at a very high rate. Such a movement of
data is commonly called a bit-stream. One characteristic
is unfortunate, particularly that any one bit in bit stream
looks identical to many other bits. Clearly it is important
that a receiver can identify important features in a bit
stream. As an example, it is important to identify the
beginning and ending of a message. This is the job of
special bit sequences called flags. A flag is simply a bit
sequence that serves as a marker in the bit stream. To
detect a flag in bit stream a sequence detector is used.
In this paper design of a Reconfigurable
Sequence Detector is discussed using which one can load
particular bit pattern and later can reconfigure that bit
pattern. The design is modeled Verilog HDL Hardware
Description Language. It was simulated using
ModelSim and then is tested for the validation of the
design on Altera Cyclone II FPGA.
Sequence Detector: A sequence detector is a special
kind of sequential circuit that looks for a special bit
pattern in some input. The detector circuit has only one
input, X. One bit of input is supplied on every clock
cycle. For example, it would take 20 cycles to scan a 20bit input. There is one output, Z, which is 1 when the
desired pattern is found.
Reconfigurable Sequence Detector: Reconfigurable
Sequence detector detects the bit sequence having any
number of bits i.e. (from 2 to 8). Also the bit pattern is
Reconfigurable i.e. the bit pattern is selected by user and
whenever that particular bit pattern is found in incoming
bit stream the system will detect that bit pattern.

Figure 1: Top level block diagram of Reconfigurable

sequence detector
Input Signal

Description

Enable(En)
Input sequence(Xi)
Sequence selection line
Bit selection lines
Load
Reset
Clock
OV(Over lapping)

For enabling the RSD

Input binary sequence
Input binary sequence to be
detected
Selection of bits
For loading binary sequence
Active low Reset input signal
System clock input signal
If OV=1 then perform overlapping

Output Signal
Output (Z)

Description
Sequence detected output

Table 1 Pin Description

ii.

Finite State Machine

The FSM (Finite State Machine) has been used to design

Reconfigurable Sequence Detector (RSD).

Figure 4: Simulation result for 0110 Sequence

Detector
III.

Modified RSD

The RSD can detect only one pattern at a time and gives
the output (Z).In some application it is desired to detect
two sequences at input stream Xi. The Modified
Reconfigurable Sequence Detector allows us to detect
two sequences coming at its input Xi and gives the
corresponding outputs Z1 and Z2.Here Z1 and Z2
represent two outputs for two sequences.
i.

Input Output Block Diagram

Figure 2: FSM Diagram

iii.

Simulation Results

The design is simulated in ModelSim. Figure 3 and 4

shows the timing waveform of the design obtained for a
5 and 4 bit sequence pattern respectively. Design is
implemented on Altera Cyclone II FPGA.

Figure5: Top level block diagram of Modified Reconfigurable

sequence detector

Figure 3: Simulation result for 10101

Detector

Sequence

Input Signal

Description

Enable(En)
Input sequence(Xi)
Sequence selection
line (Sq1)
Sequence selection
line (Sq2)
Bit selection lines
Load
Reset
Clock

For enabling the MRSD

Input binary sequence
Input binary sequence 1 to be
detected
Input binary sequence 2 to be
detected
Selection of bits
For loading binary sequence
Active low Reset input signal
System clock input signal

Output Signal
Output (Z)

Description
Sequence detected output

Table 2: Pin Description

ii.

Simulation Results

Simulation results for MRSD are shown in figure 6 and

figure 7.
In figure 6, MRSD was configured to detect 0110 and
1010 sequences. For these Sequences, Sequence
Selection lines Sq1 has been set to 0110 and Sequence
Selection lines Sq2 has been set to 1010.And also Bit
Selection lines has been set to 011. The corresponding
output Z1 and Z2 for 0110 and 1010 has been shown
in the figure 3.2.
To detect another pattern, the detector can be disabled
by making En = 0 and then load the new pattern on
Sequence Selection Lines (Sq1 and Sq2) and Bit
Selection Lines as shown in figure 7. In this example the
MRSD has been reconfigured to detect 01XX and
11XX sequences. For these Sequences, Sequence
Selection lines Sq1 has been set to 01XX and Sequence
Selection lines Sq2 has been set to 11XX.And also Bit
Selection lines has been set to 001. (Note that last 2 bits
are dont care).

Figure 6: Simulation of 0110 and 1010 Sequence Detector

Figure 7: Simulation result for 01 and 11 Sequence

Detector

CONCLUSION

Reconfigurable Sequence Detector and Modified

Reconfigurable Sequence Detector allow the facility to
reconfigure pattern detector. The paper discussed the
characteristics of a reconfigurable and reusable sequence
detector which can be made available as a component off
the shelf for SoC integration of a plethora of pattern
detection applications.
REFERENCES
1.

Jonathan Hill, Sequence Detection -- Introductory

Notes, (hartford.edu), [online] 2002,
http://uhaweb.hartford.edu/kmhill/suppnotes/sequenc
e/seqdet.htm, (Accessed Jan 2014).

2.

Chapter 7 Appendix Design of the 11011

Sequence Detector, (edwardbosworth.com),
[online],
http://edwardbosworth.com/My5155Textbook_HTM/
MyText5155_Ch07A_V06.htm, (Accessed Jan
2014).

3.

Sequence Detector, (smdp2vlsi.gov.in), [online],

http://www.smdp2vlsi.gov.in/smdp2vlsi/downloads/l
ab_manual_seq_detector.pdf, (Accessed Jan 2014).

4.

Lecture Notes - Introduction to Sequence Detectors

and CPLDs ,( ece.unm.edu), [online],