8051 Microcontroller

Course Outcomes
C501.1:
The student will get basic knowledge of memory structure, SFR
format, working of timer, counter, UART, interrupt in 8051 and ARM
7 microcontroller.
C501.2:
The student will be able to understand the working of different
instruction sets in 8051, ARM7 and interfacing of peripheral devices
such as ADC, DAC, 7segment Display, LCD, Stepper motor, DC
motor, relay to 8051 and ARM7 microcontroller.
C501.3:
The student will be able to apply knowledge of instruction set for
writing code for arithmetic operations, data transfer operation,
timer, counter, UART, interrupt and programming peripheral
devices.
C501.4:
The student will be able to analyze and select suitable instructions
and special function register of 8051 and ARM7 microcontroller for
writing efficient code.

Advantages of microprocessor
Designer can decide on amount RAM,ROM,I/O ports
needed to fit task at hand
Advantages of Microcontroller
Less space requirements
Low power consumption

Three criteria in Choosing a

Microcontroller
Speed

8051 Basic Component

4K bytes internal ROM

128 bytes internal RAM
Four 8-bit I/O ports (P0 - P3).
Two 16-bit timers/counters
One serial interface
Data Bus : 8bit
Address Bus : 16 bit

8051 MC
RAM

Other 8051 featurs

only 1 On chip oscillator (external crystal)
6 interrupt sources (2 external , 3 internal, Reset)
64K external code (program) memory(only
read)PSEN
64K external data memory(can be read and write)
by RD,WR
Code memory is selectable by EA (internal or
external)
We may have External memory as data and code

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

8051

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vcc
P0.0(AD0
)P0.1(AD1)
P0.2(AD2
)P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14
)P2.5(A13
)P2.4(A12
)P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)

I/O port

4 I/O port
Each of 8 bit
wide

P0
P1

P3
P2

Pin 1-8

Vcc

10 uF

9
8.2 K

RST

Pin 10

Pin 16

Using a quartz crystal

oscillator
We can observe the
frequency on the XTAL2 pin.
C2
XTAL2
30p
F
C1
XTAL1
30p
F
GND

Using a TTL oscillator

XTAL2 is unconnected.

N
C
EXTERNAL
OSCILLATOR
SIGNAL

XTAL2

XTAL1

GND

Pin 20

Pin 29

Pin 32-39

Minimum
connection for 8051
based system

CPU timing And Machine cycle

Oscillator Formed by crystal, capacitor and onchip inverter generates a pulse train at frequency
of crystal
Pulse time: clock frequency established smallest
interval of time within uc.
State : basic time interval for discrete operation
of uc such as fetching an opcode, decoding an
opcode, executing an opcode
Machine cycle: smallest interval of time to
accomplish any simple instruction or part of
complex instruction

1 MC= 6 State
1 State= 2 oscillator pulses
1MC= 12 clock period

C X 12

Time required to execute instruction

Crystal
=
frequency
Instruction

Machine cycle

ADD A, R0

MOV A, #23H

LJMP

XTAL = 11.0592 MHz

11.0592 MHz / 12 = 921.6 kHz;
machine cycle = 1 / 921.6 kHz = 1.085 s

Registers of 8051

B
R0
R1
R2

DPH

DPL
PC

R3
R4
R5
R6
R7

Some 8-bit
Registers of
the 8051

Some 8051 16-bit

Register

DPTR
PC

Accumulator Register (A)

Data pointer(16 bit)

Program Status Word (PSW) Register

Parity flag

Program Status Word (PSW) Register

Auxiliary carry flag AC

RS1 and RS0

RS1

RS0

0
0
1
1

0
1
0
1

Register
Bank
0
1
2
3

RAM=128 byte
Range=00 to
127
Range=00H to
7FH
7F=1
80
27
1F=3
Byte

7FH

Read/ Write
storage
Scratch pad

8051
Memory
Organizati 16
Byte
on
32
Byte

30H
2F
H
20
1F
H
H
00H

Bit addressable
read/ write
memory
Register Bank
and Stack

128
Byte

Register Bank and

Stack

1FH

8
Byte

18H
17H

8
Byte
8
Byte

10H
0FH
08H
07
H

8
Byte
00H

Register Bank
3
Register Bank
2
Register Bank
1
R7
R6
R5 Bank
Register
R4
0
R3
R2
R1
R0

32
Byte

ADDRES
S

REG

07 R7
H
R6
06
H
R5
05
R4
H
04
R3
H
R2
03
H
R1
02
R0
H
01
Register
H
Bank 0
00

ADDRES
S

REG

0F
H

R7

0E
H

R6

0D
H

R5

0C
H
0B
H
0A
H
09
H

R4
R3
R2
R1
R0

08
H
Register
Bank 1

ADDRES
S

REG

17 R7
H
R6
16
H
R5
15
R4
H
14
R3
H
R2
13
H
R1
12
R0
H
11
Register
H
Bank 2
10

ADDRES
S

REG

1F
H

R7

1E
H

R6

1D
H

R5

1C
H
1B
H
1A
H
19
H

R4
R3
R2
R1
R0

18
H
Register
Bank 3

How to switch
register bank?

RS1

RS0

0
0
1
1

0
1
0
1

Register
Bank
0
1
2
3

 Default register bank=

Register Bank 0
MOV A,R0H ; move data from R0 into reg. A
MOV A, 00H; move data from memory location 00h(R0)
into reg. A
Que. To move data from reg. R0 of
register bank 2

RS1
PSW.4

RS0
PSW.3

Registe
r Bank

CLR PSW.3

MOV A, R0H

SETB PSW.4

MOV A,10H

Stack in 8051
Stack is a section of RAM used by CPU to store information
7FH
temporary
This information could be data or an address
The register used to access stack is called SP(stack
8086
8051
pointer)
register.
SP=16
bit

SP=8
bit

Read/
Write
storage
Scratch
pad

30H
Default value in SP reg. is 07H
Bit
i.e RAM location 08H is the first location used for stack by addressabl
2F
e read/
8051

H
20
Register Bank 1= Default Stack memory
H
1F
Location 08H to 1FH in 8051 RAM can be used for stack.
H

00H
If in given program we need more than 24 bytes ( 08h to
1Fh)
of stack, we can change SP to point RAM location 30 7FH

write
memory

Register
Bank and
Stack

Difference between operation of PUSH and POP

instruction?
PUSH: storing the CPU register in the stack
POP: Pulling the contents off the stack back into a CPU
register

PUS
H

8086

8051

SP 16 bit reg.

SP 8 bit reg.

SP decremented by 2

SP incremented by 1

SP=SP-2

SP=SP+1

Syntax: PUSH register

Ex. PUSH AX

Syntax: PUSH address

Ex. PUSH 6

8086

POP

8051

SP 16 bit reg.

SP 8 bit reg.

SP incremented by 2

SP decremented by 1

SP=SP+2

SP=SP-1

Syntax: POP register

Ex. POP AX

Syntax: POP address

Ex. POP 6

ADDRES DAT
S
A

Register Bank 1= Default Stack

memory

0F H

How to store data to Stack memory?

MOV R6, #25H; R6=25H
MOV R1, #12H; R1= 12H
MOV R4, #0FEH; R4=0FEH
PUSH 6
PUSH 1
PUSH 4
Default position of stack
pointer

R7

0E H

SP=07H

S
P
S
P
S
P
S
P

REG

R6

0D H

R5

0C H

R4

0B H

R3

0A H

FEH

R2

09 H

12H

R1

08 H

25H

R0

07H

Register Bank 1= Default Stack

memory
SP=07H
How to restore data from Stack memory?

MOV R1, #12H; R1= 12H

MOV R4, #0FEH; R4=0FEH
PUSH 6
PUSH 1
POP 5;

Current status
S

POP 3;
POP 2;

R5=0
FEH
R3=1
2H
R2=2
5H

0F H

P
S
P
S
P
S
P

REG

R7

0E H

R6

0D H

MOV R6, #25H; R6=25H

PUSH 4

ADDRES DAT
S
A

R5

0C H

R4

0B H

R3

0A H

FEH

R2

09 H

12H

R1

08 H

25H

R0

07H

Bit addressable
read/ write
memory
16 byte
Range= 20H to
2FH
16 x 8 = 128
Byte
Bit addressable
bits

addressable

Register=8 bit
Byte has address

Register=8 bit
Bit has address

Access registers
in bytes

Access registers
in bits

Ex. SP

Ex. I/O port reg.

Bit addressable
read/ write
memory
MOV A, #03H; copy byte 03h to reg.
A

MOV 26H,A; copy data byte from reg.

A
to memory location 26H
16 byte

SETB
CLR

32H

32H

0 0 0 0 0 0
0 1 1
1

MOV P0,
instruction

#0FFH

BYTE addressable

SETB P0.0
instruction
P0
ADDRES
S

BIT addressable

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

87H

86H

85H

84H

83H

82H

81H

80H

Read/ Write
storage
Scratch pad
Use for read and write
storage
General purpose storing of
data
If we need more registers we
simply use RAM locations 307FH

Extra 128 byte on chip RAM in 8052

8052 is advanced version of 8051

8051

8052

Another 128 bytes of on chip RAM

128 byte of
RAM

256 byte of
RAM

with address 80-FFH are designated

as special function register(SFR) /
upper RAM

Two different
physical
memories,
but they have
same
addresses

SFR

Bit
addressable
registers

Special Function Register

8051 microcontrollers, has only 21 SRF registers

Rest of locations are intentionally left unoccupied in order

to enable the manufacturers to further develop
microcontrollers keeping them compatible with the
previous versions.

ROM in 8051
4K bytes on chip ROM
Use to store user code
ROM=code memory
Size of PC=16 bit
Therefore maximum size of on chip ROM can be
0000 to FFFFFH i.e 64 Kbytes
4 K bytes of ROM memory has addresses from
0000H to 0FFFH.

Tristate Buffer
Tristate buffer has single input,
single output and enable control pin.
By activating the enable, data at input
is transferred to output.

When receiver current requirements

exceeds the drivers capability,
we must use buffer/drivers.
Increase the fan out capacity of microcontroller
When connecting IC chip to microcontroller, we need to find
out how many input pins of IC chips can be driven by single
output pin of microcontroller.

Internal structure of ports of 8051

Since all ports of 8051 are bidirectional, they all have
following 3 components in their structure
1.D latch
2.Output driver
3.Input buffer

Internal structure of ports of 8051

Since all ports of 8051 are bidirectional, they all have
following 3 components in their structure
1.D latch
2.Output driver
3.Input buffer

P
1

PORT
1

Port-1 does not have any alternate function i.e. it is dedicated solely
for I/O interfacing. When used as output port, the pin is pulled up or
down through internal pull-up. To use port-1 as input port, '1' has to
be written to the latch. In this input mode when '1' is written to the
pin by the external device then it read fine. But when '0' is written to
the pin by the external device then the external source must sink
current due to internal pull-up. If the external device is not able to
sink the current the pin voltage may rise, leading to a possible wrong
reading.

How to write data to port pin?

0
0

0
1

How to write data to port pin?

1
1

1
0

How to read port pin?

MOV P1, #0FFH; to configured port as input
port, we
must write 1(logic high) to
that ports
MOV A, P1
1
1

1
0

Active
MOV

A,

P1

How to read latch?

MOV P1, #0FFH; to configured port as input port,
we
ports
ANL P1, A;

ANL P1, A;

must write 1(logic high) to that

P1 = A AND P1

Active

1
P1 = A AND
P1

P0

PORT
0

Port-0 can be configured as a normal bidirectional I/O port

or it can be used for address/data interfacing for accessing
external memory.
control =1 , the port is used for address/data interfacing.
control =0, the port can be used as a normal bidirectional
I/O port.
Let us assume that control is '0'. When the port is used as an input
port, '1' is written to the latch. In this situation both the output
MOSFETs are 'off'. Hence the output pin floats. This high impedance pin
can be pulled up or low by an external source. When the port is used
as an output port, a '1' written to the latch again turns 'off' both the
output MOSFETs and causes the output pin to float. An external pull-up
is required to output a '1'. But when '0' is written to the latch, the pin
is pulled down by the lower MOSFET. Hence the output becomes zero.
When the control is '1', address/data bus controls the output driver
MOSFETs. If the address/data bus (internal) is '0', the upper MOSFET is
'off' and the lower MOSFET is 'on'. The output becomes '0'. If the
address/data bus is '1', the upper transistor is 'on' and the lower
transistor is 'off'. Hence the output is '1'. Hence for normal
address/data interfacing (for external memory access) no pull-up
resistors are required

Port 0 =
Data/Address lines

Data/Address
Contr
ol

Read
Latch

VCC
0

P0.
x

1
Intern
al CPU
Bus
Write
Latch

Read
Pin

CLK

Hence for normal address/data interfacing

(for external memory access) no pull-up
resistors are required.

Port 0 =
Data/Address lines

Data/Address
Contr
ol

Read
Latch

VCC
1

P0.
x

0
Intern
al CPU
Bus
Write
Latch

Read
Pin

CLK

Hence for normal address/data interfacing

(for external memory access) no pull-up
resistors are required.

port

Data/Address
Contr
ol

Port 0 = I/O

VCC

Read
Latch
1
Intern
al CPU
Bus
Write
Latch

Read
Pin

P0.
x

CLK

Floati
ng

Hence the output pin floats. This high

impedance pin can be pulled up or low by an
external source. Hence pull up register
required

PORT
2
P
2

Port-2 is used for higher external address byte or a

normal input/output port. The I/O operation is similar to
Port-1. Port-2 latch remains stable when Port-2 pin are
used for external memory access. Here again due to
internal

pull-up

capability.

there

is

limited

current

driving

port

Data/Address
Contr
ol

Port 2 = I/O

VCC
Pull up
register

Read
Latch
1
Intern
al CPU
Bus
Write
Latch

Read
Pin

P2.
x

CLK

1
1
Data/Address
Contr
ol

Port 2 =
Address lines

VCC
Pull up
register

Read
Latch
1
Intern
al CPU
Bus
Write
Latch

Read
Pin

P2.
x

CLK

Data/Address
Contr
ol

Port 2 =
Address lines

VCC
Pull up
register

Read
Latch

Intern
al CPU
Bus
Write
Latch

Read
Pin

P2.
x
D

CLK

PORT
3

P
3

Each pin of Port-3 can be individually programmed for I/O

operation or for alternate function. The alternate function can be
activated only if the corresponding latch has been written to '1'.
To use the port as input port, '1' should be written to the latch.
This port also has internal pull-up and limited current driving
capability.

Alternate
output
Function
TXD, RD, WR

Port 3 = I/O /
Address lines
Read
Latch
1
Intern
al CPU
Bus
Write
Latch

Read
Pin

VCC

Pull up
register

P2.
x
1

CLK

The alternate function can be

activated only if the
Alternate
input Function
corresponding latch has been
written to '1'.
RXD, INT0, INT1,T0, T1

Timer in
8051

The 8051 has two timers/counters

Timer- to generate a time delay
Counter-to count events happening outside the microcontroller
Timer 0 and timer 1 are 16 bit

Timer
0

Timer
1

Every timer needs a clock pulse to

tick

TH TL
0
0
00 03
00
01
02
H H
XTAL
oscillato
r

12

Timer
operating
frequency

Timer frequency= Crystal frequency / 12

Crystal frequency= 11.0592 MHz
Then timer frequency= 1.085 us

TMOD: timer/Counter mode control

register
TMOD is a 8-bit register
Use to set the various timer operation modes
GAT
E

C/T

M1

M0

GAT
E

C/T

M1

M0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Timer 1

Timer 0

M
1

M
0

Mod
e

Operating mode

13-bit timer mode

8-bit timer/counter THx with TLx as 5-bit prescaler

16-bit timer mode

16-bit timer/counter THx and TLx are cascaded; there
is no prescaler

8-bit auto reload

8-bit auto reload timer/counter; THx holds a value
which is to be reloaded TLx each time it overfolws

Split timer mode

TMOD: timer/Counter mode control

register
GAT
E

C/T

M1

M0

GAT
E

C/T

M1

M0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit

Operating mode

C/T

C/T = 1, counter
C/T =0, timer

GAT
E

GATE=0, TRX=1, timer on

GATE=1, INTX=1, TRX=1, timer on

TCON: Timer/ Counter control

register
TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TF1

Timer 1 overflow flag

TR1

Timer 1 run control bit

TF0

Timer 0 overflow flag

TR0

Timer 0 run control bit

IE1

interrupt

IT1

interrupt

IE0

interrupt

IT0

interrupt

TMOD

TCON

GAT
E

C/T

M1

M0

GAT
E

C/T

M1

M0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TMOD reg. is not bit addressable

Ex. MOV TMOD, #02H
TCON reg. is bit addressable
Ex. SETB TR1
THx and TLx can be use like general purpose register
Ex. MOV TH0, #05H

Mode 1
16 bit timer
0000h to FFFFh
After the timer is started, it start to count up. It count up until it
reaches its limit of FFFFH.
When timer rolls over from FFFFH to 0000H , it sets high a flag bit
called TF(timer flag)

XTAL
oscillato
r

12

Timer
operating
frequency

Timer frequency= Crystal frequency / 12

Crystal frequency= 11.0592 MHz
Then timer frequency= 921.6 KHz
i.e each timer clock has period of (1/921.6
KHz)=1.085us

TH TL
0
0
00 03
00
01
02
H H

1 count =
1.085 us
No. of Count
Delay

1.085
us
1.085 us
x2
1.085 us
x3

Calculate a values of THx and TLx for generation of 5

ms delay ?

Timer generated Delay = ( 65536 NNNN ) x 1.085 us

NNNN = 65536 - (Timer generated Delay / 1.085
us)
XXXX= (NNNN)H
TH
x

TL
x

F
F

F
F

TH
x

TL
x

E
E

0
0

If timer is 16 bit, what will be the maximum delay the timer

can generate ?
TH
0

TL
0

F
F

F
F

TH TL 0 0
The number of counts0for rollover
0
0 is0FFFF-0000= FFFF(65535
decimal)
One extra clock needed when timer roll over from FFFF to 0 and
rises TF flag.
Maximumgenerated
delay= (65535+1)
x 1.085
=71.1 ms- xxxx
Timer
Delay
= us
( FFFF
+ 1 ) x 1.085 us

Calculate a values of THx and TLx for generation of 1

sec delay ?
NNNN = 65536 - (Timer generated Delay / 1.085
us)
XXXX= (NNNN)H
1 sec= 20 x 50 ms
NNNN=65536 - (50 ms/ 1.085 us)=19453=(4BFD)h

TH
x

TL
x

FF

F
F

TH
x

TL
x

4
B

F
D

X 20

Generation of square wave ?

Delay

F=1/T
Delay

T
Find the value of THx and TLx for generation a frequency
100 KHz ?
TH TL0
0
Square wave Frequency = 100 KHz

F
F

F
F

F
F

F
B

Square wave Time period = 10 us

TH
Delay
= (10- us
/ 2) =generated
5 us
NNNN
= 65536
(Timer
Delay / 1.085 us)
0
XXXX= (NNNN)H
= 65536-(5 us / 1.085 us)= 65531=(FFFB)h

TL0

In order to repeat the process the register THx and TLx

must be reloaded with orignal values,
TFx must be reset to 0

Minimum frequency that 8051 can generate ?

Delay

F=1/T
Delay

T
Minimum frequency means maximum time period
Maximum time period = 71 ms

TH TL0
0
Therefore minimum frequency = 1 / (2 x 71 ms) = 7 Hz
TH
0

TL0

F
F

F
F

0
0

0
0

Maximum frequency that 8051 can generate ?

Delay

F=1/T
Delay

T
Minimum frequency means maximum time period
minimum time period = 1.085 us

TH TL0
0
Therefore maximum frequency = 1/(2 x 1.085 us) = 461
KHz
TH
0

TL0

F
F

F
F

F
F

F
B

Mode 0
13 bit timer
0000h to 1FFFh
After the timer is started, it start to count up. It count up until it
reaches its limit of 1FFFH.
When timer rolls over from 1FFFH to 0000H , it sets high a flag bit
called TF(timer flag)
Mode 0 is exactly like mode1 except that it is a 13 bit timer instead
of 16 bit.

Mode 0
8 bit timer, auto reload mode
00h to FFh
After the timer is started, it start to count up. It count up until it
reaches its limit of FFH.
When timer rolls over from FFH to 00H , it sets high a flag bit called
TF(timer flag)
When TLx reg. roll from FFh to 00h and TFx set to 1, TL reloaded
automatically by original value kept by THx register.

1
0
0

TFx
05h
07h
06h
00h
FFh
05h

05h

TLx

THx

Calculate a maximum delay that can generate in mode

2?

Timer generated Delay = ( 256 - NN ) x

1.085 us
NN = 256 - (Timer generated Delay / 1.085 us)
XX= (NN)H
Max delay= 256 x 1.085 us= 0.277 ms
Minimum freq= 1/ (2 x 256 x 1.085 us) = 1.8 KHz
THx

FF

THx

00

Mode 3

Split timer mode

(Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard
Timer 0 control bits.TH0 is an 8-bit timer only controlled by Timer
1 control bits.
(Timer 1) Timer/Counter 1 stopped.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit
counters.
Timer

Timer
1=off

0=on
TF1

8 bit
timer

TH0
TR1

TF0
TL0
TR0

8 bit timer

Counter
Every thing is same as that of timer, the only difference is
clock source.
GAT C/T
M1
M0 GAT C/T
M1
M0
TMOD
E
E
1

In the Counter function, the register is incremented in

response to a 1-to-0 transition at its corresponding
external input pin, T0 or T1. In this function, the external
input is sampled once every machine cycle.

External clock
pulse

Counter 0
Counter 1

Mode
1

Mode
2

LED
blinkin
g

TMOD

GAT
E

C/T

M1

M0

GAT
E

C/T

M1

M0

MOV TMOD, #01H Timer 0, mode 1, 16 bit

mode

Main code

Subroutine

again1: MOV TL0,

#00H

TL0=00h

MOV TH0, #0EEH

TH0=EEh

MOV P1, #0FFH

Turn on Led

ACALL DELAY

Call delay

MOV P1, #00H

Turn off Led

ACALL DELAY

Call delay

SJMP again1

Short jump to L1

DELAY: SETB TR0

Turn on timer 0

again: JNB TF0 again Monitor TF0 flag until it rolls

over
CLR TR0

Stop timer

CLR TF0

Clear overflow flag

RET

Return from subroutine

TMOD

TCON

GAT
E

C/T

M1

M0

GAT
E

C/T

M1

M0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MOV TMOD, #01H

MOV TL0, #0F2H
MOV TH0, #0FFH

Timer 0, mode 1, 16
bit mode

Serial communication in
8051

Serial transfer
0 0 1 0 1 1 0 1

Transmitter

Receiver

Parallel transfer
1
0
1
1
Transmitter 0
1
0
0

Receiver

Asynchronous serial communication

In asynchronous method, each data is placed between start
and stop bits, this is called framing
The start bit is always 0 (low) and stop bit is 1(high)
LSB is sent out first
When there is no transfer, signal is 1 (high), which referred
to as mask

Data transfer rate

Bps: bit per second
Baud rate: number of signal changes per second
In case of 8051 bps=baud rate
RS232 is the most widely used I/O interfacing standard to allow
compatibility among data communication equipment.
RS232

Microcontroller (TTL)

Logic 0

Logic 1

Logic 0

Logic 1

3v to 25v

-3v to -25v

0 to 0.8 v

2v to 5v

MAX232 IC: voltage converter used to convert RS232 signals

to TTL voltage levels that will be acceptable to 8051 and vice
versa.

RXD
RS232
TXD

CPU

MAX23
2

TXD
(P3.1)
RXD
(P3.0)
microcontro
ller

To allow data transfer between PC and 8051

without any error, we must make sure that

110
150

baud rate of 8051 matches baud rate of PCs

300

COM port.
Some of the baud rate supported by
PC
Baud rate in 8051 is programmable with

600

the help of timer 1

In mode 2 (8 bit auto reload mode)

1200
2400
4800
9600
1920
0

SBUF register
Is 8 bit register
Byte of data to be transferred via TXD line, it must be placed in
SBUF register.
Similarly SBUF holds the byte of data when it received by the
8051s RXD line
The moment data is written into SBUF, it is framed with start bit
and stop bit and transferred serially via TXD pin
SBU
F

SCON
register

SM0 - Serial port mode bit 0 is used for serial port mode selection.
SM1 - Serial port mode bit 1.

SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit.
When set, it enables multiprocessor communication in mode 2 and 3, and
eventually mode 1. It should be cleared in mode 0.

Mode 0
serial data are transmitted and received through the RXD
pin, while the TXD pin output clocks. The bout rate is fixed
at 1/12 the oscillator frequency. On transmit, the least
significant bit (LSB bit) is sent/received first.

TRANSMIT

RECEIVE

Mode 1
In mode 1, 10 bits are transmitted through the TXD pin or
received through the RXD pin in the following manner: a
START bit (always 0), 8 data bits (LSB first) and a STOP bit
(always 1). The START bit is only used to initiate data
receive, while the STOP bit is automatically written to the
RB8 bit of the SCON register.

TRANSMIT

RECEIVE

Relation between crystal frequency and

baud rate

XTAL
oscillato
r

12

32

28,800 Hz
To timer 1
to set
baud rate

921.6KHz
Timer
operating
frequency

11.0592
MHz

TH1=

256

28,800
Baud rate
H

Mode 2
In mode 2, 11 bits are transmitted through the TXD pin or
received through the RXD pin: a START bit (always 0), 8 data
bits (LSB first), a programmable 9th data bit and a STOP bit
(always 1). On transmit, the 9th data bit is actually the TB8
bit of the SCON register. This bit usually has a function of
parity bit. On receive, the 9th data bit goes into the RB8 bit
of the same register (SCON).The baud rate is either 1/32 or
1/64 the oscillator frequency.

TRANSMIT

RECEIVE

Mode 3
Mode 3 is the same as Mode 2 in all respects except the baud
rate. The baud rate in Mode 3 is variable.

SCON
register

REN - Reception Enable bit enables serial reception when set. When cleared,
serial reception is disabled.
TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem
of transmitting the 9th bit in modes 2 and 3. It is set to transmit a logic 1 in the 9th bit.
RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by
hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.

SCON
register

TI - Transmit Interrupt flag is automatically set at the moment the last bit of one
byte is sent. It's a signal to the processor that the line is available for a new byte
transmitted. It must be cleared from within the software.
RI - Receive Interrupt flag is automatically set upon one byte receive.
it signals that byte is received and should be read quickly prior to being replaced
by a new data. This bit is also cleared from within the software.

Interrupts in 8051

Interrupt

Polling

Device 1 Device 1

8051
microcontroll
er

Device 1

Device 2
Device 2
Switch pressed: LED on
Switch released: LED off

ROM memory locations 00 to 30H locations are for Interrupt

vector table

Best way to write a code

is:
ORG 00H
LJMP MAIN
ORG 30H
MAIN:
.
.
END

Interrupt

8051 microcontroller
INT
0

Device 1

Addre Main
ss
code
0400h
0401h
0403h
0404h
0406h
Addre
ss

0003h
0004h

PC=040
3h

L1:SETB
P1.3
ACALL
Delay
CLR P1.3
ACALL
Interrupt
service
Delay
routine
SJMP L1
(ISR)

Square
P1. wave
3
P1.
4

0000h

Reset

0001h
0002h
INT0

0004h

LE
D

0005h

Interru
pt
vector
table

CPL P1.4
RETI

0006h
0007h
0008h
0009h

Stack
memor
y

Addre
ss
RAM

Stack
memor
y

0007h

00
03
00
04
00

0007h

00
03
00
04
00

0009h

Interrup
t

0003h

Addre
ss
RAM

0008h

Addre
ss

0008h
0009h

000Ah
000Bh
000Ch
000Dh
000Eh

TF0

Interrupt

8051 microcontroller
INT
0

Device 1

Addre Main
ss
code
0400h
0401h
0403h
0404h
0406h
Addre
ss

0003h
0004h

PC=040
3h

L1:SETB
P1.3
ACALL
Delay
CLR P1.3
ACALL
Interrupt
service
Delay
routine
SJMP L1
(ISR)

Square
P1. wave
3
P1.
4

0000h

Reset

0001h
0002h
INT0

0004h

LE
D

0005h
0006h

ROM

0007h
0008h

CPL P1.4
RETI

0009h

Stack
memor
y

Addre
ss
RAM

Stack
memor
y

0007h

00
03
00
04
00

0007h

00
03
00
04
00

0009h

Interrup
t

0003h

Addre
ss
RAM

0008h

Addre
ss

0008h
0009h

000Ah
000Bh
000Ch
000Dh
000Eh

TF0

Steps in executing an interrupt

It finishes the instruction it is executing and saves the address of
next instruction (PC) on stack
it jumps to fixed location in memory called interrupt vector table
that holds the address of interrupt service routine.
Microcontroller gets the address of ISR from interrupt vector table
and jumps to it. It start to execute ISR until it reaches the last
instruction of subroutine, which is RETI.
Upon execution of RETI instruction, the microcontroller returns to
place where it was interrupted. First it gets program counter (PC)
address from stack by popping the top two bytes of stack in to PC.
Then it starts to execute from address.

IE (Interrupt enable )
register:

There are two types of activation for

external hardware interrupt
1.Level triggered
2.Edge triggered

INT
0

INT
1

INT0 and INT1 pins are normally

high
Level triggered is default mode
upon reset of 8051
Level triggered
Interrupt

INT
0

INT
1

INT0 and INT1 pins are normally high

Level triggered is default mode upon
reset of 8051,

INT
0

to make them edge triggered

interrupts, we must programs bits of
TCON register

INT
1

Edge triggered
Interrupt

INT
0
INT
1

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Timer

Interrupt

IT0 = 0, INT0 level triggered interrupt

IT0 = 1, INT0 edge triggered interrupt
IT1 = 0, INT1 level triggered interrupt
IT1 = 1, INT1 edge triggered interrupt
IE0 and IE1 are use to keep track of edge triggered
interrupt, are used internally by 8051 to indicate
whether or not an interrupt is in use.
Upon edge triggered pulse on INT0 and INT1, 8051 set
IEx bit in TCON reg.
Only execution of RETI instruction at the end of ISR

Addressing mode
CPU can access data in various ways. The
data could be in register/ memory/ immediate
value
These various ways of accessing data are
called addressing modes
1.
2.
3.
4.
5.

Immediate
Register
Direct
Register indirect
indexed

Immediate addressing mode

In this mode, source operand is constant. Operand comes
immediately after opcode.
MOV A, #25H
MOV R4, #0F2H

A<=25h
R0<=F2h

Register addressing mode

Register addressing mode involves the use of registers to hold the
data to be manipulated.
MOV A, R0

A<= R0

MOV R4, R7

R4<=R7

MOV P2, P1

P2<=P1

Direct addressing mode

In this mode, operand is specified by 8 bit address field in
instruction.
MOV A, 25HA<= data at memory location 25h
MOV 0F2H,R4

memory location F2h<= data in R4

MOV 7H, 2H

memory location 7h<= data at memory location 2h

PUSH 06h
memory

Push the data at memory location 06 h into stack

POP 05H
location 05h

pop the content of stack memory into memory

register indirect addressing mode

In this mode, register is used as a pointer to the data. If data is
inside the CPU , only register R0 and R1 are used for this purpose.
When R0 and R1 are used as pointers, that is , when they hold the
addresses of RAM locations, they must be preceded by @ sign.
MOV A, @R0

A<= data at memory location held by R0

MOV @R1, A

memory location F2h<= data in R4

Indexed addressing mode

Indexed addressing mode is widely used in accessing
data elements of look-up table entries.
MOVC A, @A+DPTR get byte from internal ROM
memory
MOVX A, @DPTR

get byte from external memory

Instruction set in 8051

Arithmetic operations
Logical operations
Data transfer operations
Boolean variable operations
Program branching operations

Rn Register R7-R0 of the currently selected Register Bank.

Data 8-bit internal data locations address. This could be an
internal Data
RAM location (0-127) or a SFR [i.e. I/O port, control register, status
register, etc. (128-255)].
@Ri 8-bit Internal Data RAM location (0-255) addressed indirectly
through
register R1 or R0.
#data 8-bit constant included in instruction.
#data16 16-bit constant included in instruction.
addr16 16-bit destination address. Used by LCALL and LJMP. A
branch can be
anywhere within the 64k byte Program Memory address space.
addr11 11-bit destination address. Used by ACALL and AJMP. The
branch will
be within the same 2k byte page of Program Memory as the first byte of
the following instruction.
rel Signed (twos component) 8-bit offset byte. Used by SJMP and
all
conditional jumps. Range is 128 to +127 bytes relative to first byte of
the following instruction.
bit Direct Addressed bit in Internal Data RAM or Special Function
Register.

Arithmetic Instruction
set

Arithmetic Instruction
set

Arithmetic Instruction
set

Rotate Instruction set

RR

RRC

RL

RLC

Logical Instruction set

Bit manipulation Instruction set

8051 microcontroller

PC

0400h

MOV TMOD, #01H

0402h

again1: MOV TL0,

#00H

0404h

MOV TH0, #0EEH

CLR TR0

0406h

MOV P1, #0FFH

CLR TF0

0408h

ACALL DELAY

040Ah

MOV P1, #00H

040Ch

ACALL DELAY

040Eh

SJMP again1

PC

PC

DELAY: SETB TR0

again: JNB TF0 again

RET
Subroutine

Main
code

PC=040
Ah

Addre
ss
RAM

Stack
memor
y

Addre
ss
RAM

Stack
memor
y

0007h

00
0A
00
04
00

0007h

00
0A
00
04
00

0008h
0009h

0008h
0009h

Program and Machine control Instruction set

LCALL
Long call
3 byte instruction
Address: 16 bit
LCALL can be used to call subroutines located anywhere within
64 Kbyte address space of 8051
ACALL
Absolute call
2 byte instruction
Address: 11 bit
ACALL can be used to call subroutines located within 2 Kbyte
address space of 8051

LJMP
Long jump
3 byte instruction
Address: 16 bit
LJMP can be used to jump anywhere within 64 Kbyte address
space of 8051
SJMP
Short jump
2 byte instruction
1st byte: opcode
2nd byte: relative address
Address: 8 bit therefore relative address range= 00 to FFh
Is divided into forward and backward jump, that is within -128
to 127 bytes of memory relative to address of current PC.
AJMP
Long jump
2 byte instruction
Address: 11 bit
AJMP can be used to jump anywhere within 2 Kbyte address
space of 8051

PC

OPCODE

CODE

0002H

7455

MOV A,#55H

0004H

6003

JZ NEXT

0006H

08

INC R0

0007H

04

INC A

0008H

04

INC A

0009H
PC

2477
NEX ADD A, #77H
Relative
address=
target jump
T:
address- PC
OPCODE

CODE

0002H

7455

MOV A,#55H

0004H

04

0005H

08

INC R0

0006H

04

INC A

0007H

60FB

JZ NEXT

0009H

2477

ADD A, #77H

NEX
T:

INC A

Program and Machine control Instruction set

Program and Machine control Instruction set

Data transfer Instruction set

Data transfer Instruction set

16 x 2 LCD
display

 LCD is finding widespread use

replacing LEDs
The declining prices of LCD
The ability to display numbers,
characters,
and graphics
Incorporation of a refreshing
controller
into the LCD, thereby relieving the
CPU of
the task of refreshing the LCD
Ease of programming for characters
and
graphics

LCD interfacing
Instruction command
code register

VCC VS
S

VE
E

RS R/
W

Data register

D8 D7 D6 D5 D4 D3 D2 D1 D0

+5v

VE
E

RS
R/W

0
1

1
0

0
1

1
0

0
0

0
0

0
1

Data
Data register
register

code
command code
Instruction
Instruction command
register
register

VC
C
VSS

+5v

VCC

VEE

RS
R/W

0
1

1
0

0
1

1
0

0
0

0
0

0
1

Data
Data register
register

code
command code
Instruction
Instruction command
register
register

VSS

VCC VS
S

RS: Register select

Data
Data register
register

code
command code
Instruction
Instruction command
register
register

R
S1

R/
W

RS=1: data register is

selected

VE
E

RS=0: instruction command

code register is selected

R/W

1
0

0
1

0
0

0
0

0
1

Data
Data register
register

code
command code
Instruction
Instruction command
register
register

VE
E

Write
Read
0

RS

0
R/W= 0: write LCD

VCC VS
S

R/W= 1: read LCD

code
command code
Instruction
Instruction command
register
register

1
0
1
0
0
0
1

Data
Data register
register

To display letters
and numbers, we
send ASCII codes
for letter A-Z, a-z
and numbers 0-9
to data pins

RS R/
W

VE
E

480
ns

VCC VS
S

Enable pin used by LCD to latch

information present to its data pins.
When data is supplied to data pins, a
high to low pulse must be applied to
this pin in order for the LCD to latch
in data present in data lines

R
S
R/W

E
0
1

1
0

0
1

1
0

0
0

0
0

0
1

Data
register

Instruction
command code
register

VC
C
VS
S
VEE
R

+5v
+5v

LCD
Command
codes

Code (Hex)

Command to LCD Instruction Register

Clear display screen

Return home

Decrement curser (shift cursor to left)

Increment cursor (shift cursor to right)

Shift display right

Shift display left

Display off, cursor off

Display off, cursor on

Display on, cursor off

Display on, cursor blinking

Display on, cursor blinking

10

Shift cursor position to left

14

Shift cursor position to right

18

Shift the entire display to the left

1C

Shift the entire display to the right

80

Force cursor to beginning of first line

C0

Force cursor to beginning of second line

38

2 lines and 5x7 matrix

The first instruction we send must tell the LCD

whether we'll be communicating with it with an
8-bit or 4-bit data bus. We also select a 5x8 dot
character font. These two options are selected
by sending the command 38h to the LCD as a
command.
The command 0Eh is to turn the LCD on
The command 01h is to clear display screen

LCD interfacing
Instruction command
code register

VCC VS
S

VE
E

RS R/
W

Data register

D8 D7 D6 D5 D4 D3 D2 D1 D0

P1.
0
P1.
1
P1.
2
P1.
3
P1.
4
P1.
5
P1.
6
P1.
7

P2.
2
P2.
1
P2.
0

8051
microcontroller

Code for sending

command to LCD

RS BIT P2.0

To select command register

RS= 0

E BIT P2.2

To select write operation RW=0

High to low pulse must be
applied to E pin in order for the
LCD to latch in data present in
data lines.
This pulse must be minimum of
450 ns wide 480
ns

RW BIT P2.1

send_command: CLR RW
CLR RS
SETB E
ACALL DELAY
CLR E
RET

Code for sending data to

LCD

RS BIT P2.0

To select data register RS= 1

E BIT P2.2

To select write operation RW=0

High to low pulse must be
applied to E pin in order for the
LCD to latch in data present in
data lines.
This pulse must be minimum of
450 ns wide
480
ns

RW BIT P2.1

send_data: CLR RW
SETB RS
SETB E
ACALL DELAY
CLR E
RET

How to create delay ?

DELAY : MOV R0, #10
Here2 : MOV R1, #255
Here1 : DJNZ R1, here1
DJNZ R0, here2
RET

ORG 00H
RS BIT P2.0
RW BIT P2.1
E BIT P2.2
;LCD INITIALIZATION
here: MOV P1, #38H ;2 lines and 5x7 matrix
ACALL send_command
MOV P1, #0EH ;display on cursor blink
ACALL send_command
MOV P1, #01H ;clear display screen
ACALL send_command

;PRINTING A CHARACTER

Keyboard
interfacing

No key has been

pressed

Output port

VC
C

R
R

Input port

No key has been

pressed

Output port

VC
C

R
R

Input port

If key
pressed

Output port

VC
C

R
R

1
0

Input port

If key
pressed

Output port

VC
C

R
R

1
0

Input port

If input port is other than 1111 then key

is pressed

Before Key
pressed

after Key
pressed

CJNE
1

If key
pressed

Output port

VC
C

R
R

Input port

If key
pressed

Output port

VC
C

R
R

1
0

Input port

If key
pressed

R
R

Output port

VC
C

Input port

If key
pressed

R
R

Output port

VC
C

Input port

;keyboard subroutine. This program sends the ASCII

;code for pressed key to P0.1
;P1.0-P1.3 connected to rows, P2.0-P2.3 to column
MOV P2,#0FFH
;make P2 an input port
K1: MOV P1,#0
;ground all rows at once
MOV A,P2
;read all col ;(ensure keys open)
ANL A,00001111B
;masked unused bits
CJNE A,#00001111B,K1 ; till all keys release
K2: ACALL DELAY
;call 20 msec delay
MOV A,P2
;see if any key is pressed
ANL A,00001111B
;mask unused bits
CJNE A,#00001111B,OVER ;key pressed, find row
SJMP K2
;check till key pressed
OVER: ACALL DELAY
;wait 20 msec debounce time
MOV A,P2
;check key closure
ANL A,00001111B
;mask unused bits
CJNE A,#00001111B,OVER1
;key pressed, find row
SJMP K2
;if none, keep polling

OVER1: MOV P1, #11111110B ;ground row 0

MOV A,P2
;read all columns
ANL A,#00001111B
;mask unused bits
CJNE A,#00001111B,ROW_0
;key row 0, find col.
MOV P1,#11111101B
;ground row 1
MOV A,P2
;read all columns
ANL A,#00001111B
mask unused bits
CJNE A,#00001111B,ROW_1
;key row 1, find col.
MOV P1,#11111011B
;ground row 2
MOV A,P2
;read all columns
ANL A,#00001111B
;mask unused bits
CJNE A,#00001111B,ROW_2
key row 2, find col.
MOV P1,#11110111B
;ground row 3
MOV A,P2
;read all columns
ANL A,#00001111B
;mask unused bits
CJNE A,#00001111B,ROW_3
;key row 3, find col.
LJMP K2
;if none, false input,;repeat

ROW_0: MOV DPTR,#KCODE0

;set DPTR=start of row 0
SJMP FIND
;find col. Key belongs to
ROW_1: MOV DPTR,#KCODE1
;set DPTR=start of row
SJMP FIND
;find col. Key belongs to
ROW_2: MOV DPTR,#KCODE2
;set DPTR=start of row 2
SJMP FIND
;find col. Key belongs to
ROW_3: MOV DPTR,#KCODE3
;set DPTR=start of row 3
FIND: RRC A
;see if any CY bit low
JNC MATCH
;if zero, get ASCII code
INC DPTR
;point to next col. addr
SJMP FIND
;keep searching
MATCH: CLR A
;set A=0 (match is found)
MOVC A,@A+DPTR
;get ASCII from table
MOV P0,A
;display pressed key
LJMP K1
;ASCII LOOK-UP TABLE FOR EACH ROW
ORG 300H
KCODE0: DB 0,1,2,3 ;ROW 0
KCODE1: DB 4,5,6,7 ;ROW 1
KCODE2: DB 8,9,A,B ;ROW 2
KCODE3: DB C,D,E,F ;ROW 3
END

Relatively inexpensive
Ideal for open loop positioning
control
Can be implemented without
feedback
Minimizes sensing devices
Just count the steps!
Torque
Holds its position firmly when
not turning
Eliminates mechanical brakes
Produces better torque than DC
motors at lower speeds
Positioning applications

Bi-directional current flow

through entire winding

Unidirectional current flow

in each of winding

S
N

P1.
1

P1.
2

P1.
3

P1.
0

S
N

P1.
1

P1.
2

P1.
3

P1.
0

S
N

P1.
1

P1.
2

P1.
3

P1.
0

S
N

P1.
1

P1.
2

P1.
3

P1.
0

S
N

P1.
1

P1.
2

P1.
3

P1.
0

S
N

P1.
0

P1.
1

P1.
2

P1.
3

P1.
0

P1.
1

P1.
2

P1.
3

P1.
0

P1.
1

P1.
2

P1.
3

P1.
0

P1.
1

P1.
2

P1.
3

P1.
0

P1.
1

P1.
2

P1.
3

P1.
0

P1.
1

P1.
2

P1.
3

P1.
0

P1.
1

P1.
2

P1.
3

P1.
0

P1.
1

P1.
2

P1.
3

ADC interfacing

1V

111
110
101
100
011
010
001

0V

000

1V
0.875 V
0.75
V
0.625V
0.5
V
0.375
V
0.25 V
0.125
V
0V

Vref (+) - Vref

Step size =
=
n
(-) 2

n bit ADC
In this case,
n=8
No. of
quantization
levels
=

1-0
n
2

n
2

8 analog inputs

8 bit data output

End of
conversions

Reference voltage

Output enable

Start of conversions
3 address pins

ADC 0809/0808
8 bit ADC
If Vref (+)= 2.56 v and Vref (-)=0 v then

Vref (+) - Vref =

Step size =
n
(-)
2

2.56 - 0
8
2

Input to ADC

Output from
ADC

0 mv
10 mv
20 mv

2.56 v

00000000
00000001
00000010

11111111

= 10
mv

Vref (+) - Vref

tep size =
n
(-)
2

D
A
T
A

1
0

P2.4
ALE
P2.6
SC
P2.7
EOC
P2.5
OE