EC201

SolidStateDevices&Circuits
4.MOSTransistors

Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
jschutt@emlab.uiuc.edu
JoseE.SchuttAine ECE442

NMOS Transistor

NMOS Transistor

N-Channel MOSFET
Built on p-type substrate
MOS devices are smaller than BJTs
MOS devices consume less power than BJTs

JoseE.SchuttAine ECE442

NMOS Transistor - Layout

Top View

Cross Section

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MOS Regions of Operation

Resistive
VGS > VT
VDS small
Triode
Nonlinear
VGS > VT
VDS < (VGS VT )

Active

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Saturation
VGT > VT
VDS VGS VT
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MOS Transistor Operation

As VG increases from zero
Holes in the p substrate are repelled from the gate area
leaving negative ions behind
A depletion region is created
No current flows since no carriers are available

As VG increases
The width of the depletion region and the potential at the
oxide-silicon interface also increase
When the interface potential reaches a sufficiently
positive value, electrons flow in the channel. The
transistor is turned on

As VG rises further
The charge in the depletion region remains relatively
constant
The channel current continues to increase
JoseE.SchuttAine ECE442

MOS Triode Region - 1

ID =

W
Cox (VGS VT )VDS
L

VDS  (VGS VT )
Cox =

ox
tox

3.9 o
=
tox

Cox: gate oxide capacitance

: electron mobility
L: channel length
W: channel width
VT: threshold voltage

JoseE.SchuttAine ECE442

MOS Triode Region

FET is like a linear resistor with

rds =

1
W
nCox (VGS VT )
L

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MOS Triode Region - 2

VGS > VT
VDS < (VGS VT )

W
1 2
I D = nCox (VGS VT )VDS VDS
2
L

Charge distribution is nonuniform across channel

Less charge induced in proximity of drain

JoseE.SchuttAine ECE442

MOS Active Region

Saturation occurs at pinch off when

VDS = (VGS VT ) = VDSP

VGS > VT
VDS > (VGS VT )
(saturation)

W
2
I D = nCox
(VGS VT )
2L
JoseE.SchuttAine ECE442

MOS Threshold Voltage

The value of VG for which the channel is inverted is
called the threshold voltage VT.
Characteristics of the threshold voltage

Depends on equilibrium potential

Controlled by inversion in channel
Adjusted by implantation of dopants into the channel
Can be positive or negative
Influenced by the body effect

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MOS Active Region

Saturation

Channel is pinched off

Increase in VDS has little effect on iD
Square-law behavior wrt (VGS-VT)
Acts like a current source
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Example
An MOS process technology has Lmin= 0.4
m, tox= 8 nm, = 450 cm2/V.s, VT = 0.7V
(a) Find Cox and kn= nCox
(b) W/L = 8 m/0.8m. Calculate VGS, VDSmin for
operation in saturation with ID= 100 A
(c) Find VGS for the device in (b) to operate as
a 1 k resistor for small vDS

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Example - Solution
Cox =

ox
tox

3.45 1011
3
2
2
F
m
fF

m
=
=
4.32

10
/
=
4.32
/
8 109
Cox = 4.32 fF / m 2

kn' = nCox = 450 cm 2 / V .s 4.32 fF / m 2 = 194 A / V 2

For operation in saturation region
1 'W
2
iD = kn (VGS VT )
2 L
1
8
2
100 = 194
(VGS 0.7 ) VGS 0.7 = 0.32 V VGS = 1.02 V
2
0.8

VDS min = VGS VT = 0.32 V

JoseE.SchuttAine ECE442

VDS min = 0.32 V

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Example (cont)
Triode region with vDS very small

vDS
rDS =
iD

=
small vDS

1
'W

kn L (VGS VT )

1
100 =
194 106 10 (VGS 0.7 )

VGS 0.7 = 0.52 V

VGS = 1.22 V
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Gate Capacitance

VGT < 0

VGT > 0, VDS small

Capacitance
Depends on bias
Fringing fields are present
Account for overlap C

VGT > 0, VDS large

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Capacitance
Gate Capacitance
CG determines the amount of charge to switch gate
Several distributed components
Large discontinuity as device turns on
At saturation capacitance is entirely between gate
and source
VDS
Define X =
VGS VT

2
1 X
Cgs = C gso + WLCox 1

3
2 X

Cgd

1 2
2
= Cgdo + WLCox 1

3
2 X

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MOS Capacitances

Expect capacitance between every two of the

four terminals.
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Problem
A MOSFET has VT = 1 V with measure data:

Find

VGS(V)
2
2

VDS(V)
1
8

ID(A)
80
91

(a ) VGS > VT

VDS = VGS VT Pinchoff

(b) VGS > VT

VDS > VGS VT = 1 V Active region

Find iD at pinchoff VDSP = VGS-VT =1V

1 W
2
I D = kn' (VGS VT ) (1 + VDS )
2 L
1 W
2
I D1 = kn' (VGS 1 VT ) (1 + VDS 1 )
2 L
1 W
2
I D 2 = kn' (VGS 2 VT ) (1 + VDS 2 )
2 L

R=

1 + VDS 1 91
=
= 1.1375
1 + VDS 2 80

1 + VDS 2 = R + RVDS 1

(VDS 2 RVDS 1 ) = R 1
=

R 1
1.1375 1
=
= 0.0196 V 1
VDS 2 RVDS 1
8 1

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Body Effect
The body effect
VT varies with bias between source and body
Leads to modulation of VT
Potential on substrate affects threshold voltage
1/ 2

VT (VSB ) = VTo + ( 2 F + VSB ) ( 2 F

kT
F =
q

Na
ln n
i

2qN a s )
(
=
Cox

1/ 2

Fermi potential of material

1/ 2

Body bias coefficient

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Channel-Length Modulation

With depletion layer widening, the channel length is in effect reduced from
L to L-L Channel-length modulation
This leads to the following I-V relationship

1 'W
2
iD = kn ( vGS VT ) (1 + vDS )
2 L
Where is a process technology parameter
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Channel-Length Modulation

Channel-length modulation causes iD to increase with vDS in

saturation region

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NMOS IV Curves
NMOS
700
VGS=1.0
VGS=1.5
VGS=2.0
VGS=2.5

600

500

IDS

400

300

200

100

0
0

0.5

1.5

2.5

Vds

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nMOS Device Types

Enhancement Mode
Normally off & requires positive potential on gate
Good at passing low voltages
Cannot pass full VDD (pinch off)
Depletion Mode
Normally on (negative threshold voltage)
Channel is implanted with positive ions (VT )
Provides inverter with full output swings
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PMOS Transistor
PMOS
0

-100

VGS=-1.0

-200

-300

-400

-500
VGS=-1.0
VGS=-1.5
VGS=-2.0
VGS=-2.5

-600

-700
-2.5

-2

-1.5

-1

-0.5

Vds

- All polarities are reversed from nMOS

- Hole mobility is lower low transconductance
- nMOS favored over pMOS

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Complementary MOS

CMOS Characteristics
Combine nMOS and pMOS transistors
pMOS size is larger for electrical symmetry

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CMOS
Advantages
Virtually, no DC power consumed
No DC path between power and ground
Excellent noise margins (VOL=0, VOH=VDD)
Inverter has sharp transfer curve
Drawbacks
Requires more transistors
Process is more complicated
pMOS size larger to achieve electrical symmetry
Latch up
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MOS Parasitics

- Capacitance from gate to other 3 terminals

- Diodes to body
- Series resistance
- Wiring parasitics

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MOSFET Switch

NMOS

PMOS

Characteristics of MOS Switch

MOS approximates switch better than BJT in off state
Resistance in on state can vary from 100 to 1 k

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CMOS Switch

CMOS switch is called an inverter

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CMOS Switch Off State

OFF State (Vin: low)

nMOS transistor is off
Path from Vout to V1 is through PMOS Vout: high
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CMOS Switch On State

ON State (Vin: high)

pMOS transistor is off
Path from Vout to ground is through nMOS Vout: low
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CMOS Inverter
rdsn =

1
W
k N' (VDD VT )
L n

rdsp =

1
W
k P' (VDD VT )
L p

Short switching
transient current
low power
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BJT vs MOS
Matching
VBEon for bipolar is determined by bandgap
VT on MOS is determined by tox and implant
BJTs have superior current drive
BJTs switch faster than MOS
BJTs dissipate more power
BJTs have lower yield
BJTs are more costly
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CMOS vs Bipolar
Current
Collector current inversely proportional to Wb
Drain current inversely proportional to L
Topology
Base width is vertical defined by lithography
Channel length is horizontal defined by diffusion
Behavior
Bipolar current is exponential
MOS current obeys square law
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