Datasheet

DesignWare Cores
Ethernet MAC 10/100/1000 Universal

Overview
The DesignWare Ethernet MAC
10/100/1000 Universal intellectual
property (IP) core implements the link
layer of an OSI Ethernet system. The
silicon-proven core is configurable and
scalable to meet multiple Ethernet
application requirements.
``
Optimal architecture provides low

latency and low gate count

``
Configurable to include only

the features required for your

application
``
Configurable to accommodate
different system architectures
``
Supporting new Audio Video
and Energy Efficient Ethernet
applications
Synopsys offers a high-quality
IP solution that is in volume
production and has been successfully
implemented in a wide range of
applications.

Benefits
High-Performance Architecture
The DesignWare Ethernet MAC 10/100/1000 Universal core is designed to support
high-performance applications such as routers and network storage applications.
This is accomplished by removing any latency associated with configurable IP.
Typical design of configurable IP results in multiple layers that are bridged during
configuration. This results in many unnecessary latencies due to double buffering of
data as it crosses from one layer to another. The coreConsultant configuration tool
removes such latencies at configuration time, thus providing high-performance IP.
Fully Configurable Core
The DesignWare Ethernet MAC 10/100/1000 Universal core is highly configurable
and reduces integration time, gate count and power consumption. Features such as
data bus widths, FIFO depths, DMA integration or interface types are readily defined
during integration. Moreover, unused features do not result in any gate penalty thus
minimizing gate count and power consumption.
TxFC
(Mem)

AXI/
AHB
Master
Interface

DMA

TxFC

RxFC
(Mem)

RxFC
GMAC

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Switch/Router
``
Set-top Boxes

``
Network Processors
``
Network Storage

``
Network Appliances

``
Industrial Controllers

AXI/
AHB/
APB
Slave
Interface

DMA
CSR

OMR
Reg.

MAC
CSR

Optional
PHY
interfaces
RGMII/
RTBI/TBI/
SGMII/
SMII/
RMII
GMII/MII

Select

Figure 1: DesignWare Ethernet MAC 10/100/1000 Universal Block Diagram

General Features

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Preamble and start-of-frame data

``
Reduced GMII (RGMII)

``
Compliant with IEEE 802.3-2005 standard

(SFD) insertion in Transmit, and

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Serial GMII (SGMII)

``
Support for IEEE 1588-2002 and IEEE

deletion in Receive paths

``
Ten Bit Interface (TBI)

1588-2008 standards for precision

networked clock synchronization
``
Supports IEEE 802.1-AS, version D6.0
and IEEE 802.1-Qav, version D6.0 for
Audio Video (AV) traffic
yy Supports separate channels or
queues for AV data transfer in 100
Mbps and 1000 Mbps modes
yy Supports configuring up to two
additional channels (Channel 1 and

``
Automatic CRC and pad generation
controllable on a per-frame basis
``
Options for Automatic Pad/CRC
Stripping on receive frames
``
Programmable frame length to
support Standard or Jumbo Ethernet
frames with sizes up to 16 KB
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Programmable InterFrameGap (40-96
bit times in steps of 8)
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Supports a variety of flexible address

Channel 2) on transmit and receive

filtering modes:

paths for AV traffic

yy Up to 31 additional 48-bit perfect

yy Supports IEEE 802.1-Qav specified

credit-based shaper (CBS) algorithm
for additional transmit channels
yy Provides separate DMA, TxFIFO, and
RxFIFO (MTL) for each additional

(DA) address filters with masks for

each byte
yy Up to 31 48-bit SA address

``
Reduced MII (RMII)
``
Serial MII (SMII)
``
Reduced TBI (RTBI)
``
Reverse MII (RevMII)

Transaction Layer (MTL)

Features
``
32, 64, or 128-bit Transaction Layer
block providing a bridge between the
application and the GMAC-CORE
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Single-channel Transmit and Receive
engines
``
Data transfers executed using simple
FIFO-protocol
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Synchronization for all clocks in the

comparison check with masks for

design (Transmit, Receive and system

each byte

clocks)

channel while maintain the system-

yy 64-bit Hash filter (optional) for

``
Optimization for packet-oriented

side interface (AHB, AXI, or native)

multicast and uni-cast (DA)

transfers with frame delimiters

``
Supports IEEE 802.3-az, version D2.0
for Energy Efficient Ethernet (EEE)
``
Supports AMBA 2.0 for AHB Master/
Slave ports
``
Supports AMBA 3.0 for AXI Master/
Slave ports

MAC Features
``Configurable to support data transfer
rates of:
yy 10/100/100 Mbps
yy 10/100 Mbps only
yy 1000 Mbps only
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Supports both full-duplex and halfduplex operation
yy IEEE 802.3x flow control automatic
transmission of zero-quanta pause
frame on flow control input de-assertion.
yy Optional forwarding of received
pause control frames to the user
application
yy Supports CSMA/CD Protocol for
half-duplex operation
yy Supports packet bursting and frame
extension in 1000 Mbps half-duplex
operation
yy Back-pressure support for halfduplex operation

DesignWare Cores

addresses
yy Option to pass all multicast
addressed frames
yy Promiscuous mode support to pass

``
Four Separate ports for system-side
and GMAC-CORE-side transmission
and reception
``
Two 2-port RAM-based asynchronous

all frames without any filtering for

FIFOs with synchronous/asynchronous

network monitoring

Read and Write operation with respect

yy Passes all incoming packets (as per

filter) with a status report
``
Separate 32-bit status returned for
transmission and reception packets
``
Supports IEEE 802.1Q VLAN tag
detection for reception frames
``
Separate transmission, reception, and
control interfaces to the Application
``
Configurable big endian and little

to the Read and Write clocks (one for

transmission and one for reception)
``
FIFO instantiation outside the top-level
module to facilitate memory testing/
instantiation
``
Supports 128-, 256-, or 512-byte, or
1-, 2-, 4-, 8-, 16-, or 32-KB receive
FIFO depths on reception.
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Optional interface to indicate the

endian support for transmission and

length of a received frame at the top

reception data paths

of the MTL Rx FIFO in the GMAC-MTL

``
Supports 32/64/128-bit data transfer
interface on the system-side

configuration
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Programmable burst-length support
for starting a burst up to half the size

PHY Interfaces

of the MTL Rx and Tx FIFO in the

The GMAC-UNIV supports any one

GMAC-MTL configuration

or a combination of the following PHY

``
Receive Status vectors inserted

interfaces:

into the Receive FIFO after the EOF

``
Gigabit Media Independent Interface

transfer enables multiple-frame

(GMII)
``
Media Independent Interface (MII)

storage in the Receive FIFO without

requiring another FIFO to store those
frames Receive Status.

``
Configurable Receive FIFO threshold

DMA Block Features

(default fixed at 64 bytes) in Cut-

``
Supports 32/64/128-bit data transfers

Through mode

``
Supports single-channel Transmit and

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Option to filter all error frames on
reception and not forward them to

Receive engines
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Provides fully synchronous design

the application in Store-and- Forward

operating on a single system clock

mode

(except for CSR module, when a

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Option to forward under-sized good
frames
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Supports statistics by generating
pulses for frames dropped or
corrupted (due to overflow) in the
Receive FIFO
``
Supports 256- or 512-byte, or 1-,
2-, 4-, 8-, or 16-KB FIFO depth on
transmission
``
Supports Store and Forward

separate CSR clock is configured)

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Provides optimization for packetoriented DMA transfers with frame
delimiters
``
Supports byte-aligned addressing for
data buffer support
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Supports dual-buffer (ring) or linkedlist (chained) descriptor chaining
``
Supports descriptor architecture that
allows large blocks of data transfer

mechanism for transmission to the

with minimum CPU intervention; each

GMAC core

descriptor can transfer up to 8 KB of data

``
Supports threshold control for
transmit buffer management
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Supports configurable number of
frames to be stored in FIFO at any

``
Supports comprehensive status
reporting for normal operation and
transfers with errors.
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Supports individual programmable

time. The default is 2 frames (fixed)

burst size for Transmit and Receive

with internal DMA, and up to 8 frames

DMA Engines for optimal host bus

in GMAC-MTL configuration.

utilization.

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Automatic generation of PAUSE frame

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Supports programmable interrupt

control or backpressure signal to the

options for different operational

GMAC core based on Receive FIFO-fill

conditions. Provides per-frame

(threshold configurable) level.

Transmit/Receive complete interrupt

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Handles automatic retransmission of
Collision frames for transmission
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Discards frames on late collision,
excessive collisions, excessive
deferral and underrun conditions
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Software control to flush Tx FIFO
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Data FIFO RAM chip-select disabled

control
``
Supports round-robin or fixed-priority
arbitration between Receive and
Transmit engines.
``
Supports Start/Stop modes
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Provides separate ports for host CSR
access and host data interface.

when inactive, to reduce power

consumption
``
Optional module to calculate and
insert IPv4 header checksum and TCP,
UDP, or ICMP checksum in frames
transmitted in Store-and-Forward
mode

AHB Master Interface Features

``
Interfaces with the application through
AHB
``
Supports little-endian and big-endian
modes
``
Supports 32-bit, 64-bit, or 128-bit
data on the AHB Master port
``
Provides option to select addressaligned bursts from AHB Master port
``
Supports Split, Retry, and Error AHB

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Handles the AHB 1K boundary burst
splitting
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Does not generate wrap burst
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Software can select the type of AHB
burst (fixed burst, indefinite burst, or
mix of both)

AHB Slave Interface Features

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Interfaces with the application through
AHB
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Supports little-endian and big-endian
modes
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AHB Slave interface (32-bit, 64-bit,
or 128-bit) for CSR access, in which
only 32-bit or less (byte, half-word)
accesses are possible
``
Provides option for a 32-bit APB port
for CSR access instead of an AHB
Slave port
``
Supports all AHB burst types
``
Does not generate Split, Retry, or Error
responses

AMBA AXI Master Interface

Features
``
Interfaces with the application through
AXI
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Supports 32-bit address width
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Supports little-endian and byteinvariant big-endian modes
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Supports AXI low-power interface
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Supports 32-bit, 64-bit, or 128-bit data
``
Supports OKAY, SLVERR, and
DECERR responses
``
Software can select the type of AXI
burst (fixed and variable length burst)
in the AXI Master interface with an
option to select extended length fixed
bursts of 32, 64, 128, and 256.
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Provides an option to select addressaligned bursts
``
Handles the AXI 4K boundary burst
splitting
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Supports up to 16 read and write
outstanding transactions
``
Supports using posted writes from
the AXI Master interface to maximize
the bus utilization

responses

DesignWare Cores

AMBA AXI Slave Interface

Features

``
MAC layer with a FIFO layer (MAC-

``
Interfaces with the application through

``
MAC Layer with a FIFO layer and a

AXI
``
AXI Slave interface (32-bit, 64-bit, or
128-bit) for CSR access

MTL; GMAC-MTL)
DMA (MAC-DMA; GMAC-DMA)
``
MAC Layer with a FIFO layer and a
DMA with an AHB interface (MAC-

When configured for IEEE 1588-2008

mode automatically identifies received
PTP packets and provide time-stamps
for the valid PTP packets defined for
that node.

``
Supports 32-bit address width

AHB; GMAC-AHB)MAC Layer with

Verification Environment

``
Supports little-endian and byte-

a FIFO Layer and a DMA with AXI

The DesignWare Ethernet MAC

Interface (MAC AXI; GMAC AXI)

10/100/1000 Universal core is delivered

invariant big-endian modes

``
Provides option for a APB or AHB

In addition, the PHY interface can be

Slave port for CSR access instead of

configured to have one or more of the

AXI Slave port

supported PHY interfaces.

``
Supports narrow burst and FIXED/
INCR burst

Functional Description
The DesignWare Ethernet MAC
10/100/1000 Universal core simplifies
system-on-chips (SoC) implementation
efforts by providing designers with
a highly configurable IP with ample
features to fit different architectures.
The IP is configured using the Synopsys
coreConsultant configuration tool. The
coreConsultant tool enables designers
to choose types of interfaces, specify
different architectures and optimize
other variables.

Packet Handling
The DesignWare Ethernet MAC
10/100/1000 Universal core handles
preamble generation and removal.
32-bit CRC generation and checking
is performed automatically to verify
data integrity. Insertion and stripping
of padding bytes on transmission and
reception are also available. To minimize
system overhead, the flexible address
filter scheme enables data filtering in
the network that is not addressed to the
node in which it resides.

Industry-Standard Interfaces
Using the coreConsultant the
DesignWare Ethernet MAC 10/100/1000
Universal core may be configured to any
of the following:
``
MAC Layer Only ( MAC/GMAC)

DesignWare Cores

In the case of support for multiple PHY

interfaces, a MUX is instantiated as well.

Network Management Support

The DesignWare Ethernet MAC
10/100/1000 Universal core includes
configurable counters (16 or 32 bit)
for a number of network management
protocols, including Remote Monitoring
(RMON), Simple Network Management
Protocol (SNMP), and Ethernet-Like.
These counters track events such as the
number of CRC errors, the number of
network collisions, and the number of
Runt frames.

Checksum Offload Engine

The DesignWare Ethernet MAC
10/100/1000 Universal core detects
IPv4/IPv6 payload in received Ethernet
frames and verifies whether or not
the IPv4, TCP, UDP or ICMP header
checksums are correct. Similarly, it
can calculate and insert the IPv4, TCP,
UDP or ICMP header checksums in the
appropriate locations in the transmitted
frames.

IEEE 1588 Support

The DesignWare Ethernet MAC core
provides support for capturing the timestamp of frames transmitted or received
at the PHY interface. The time-stamps
for the frames are provided in the
corresponding frame-status at the end
of the frame transfer. The captured time-

with a test environment that verifies its

functionality in compliance with the IEEE
specifications. The test environment
includes a GMII bus functional model
and a GMII monitor to facilitate systemlevel testing. The GMII model drives
gigabit Ethernet traffic on the GMII bus,
while the GMII monitor reports protocol
violations.

Power Management
Supports advanced power management
including:
``Wake-on-LAN
``AMD Magic Packet
``IEEE 802.3az Energy Efficient
Ethernet
``
UPF

Monitoring, Testing, and

Debugging Support
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Supports internal loopback on the
GMII/MII for debugging
``
Provides DMA states (Tx and Rx) as
status bits
``
Provides Debug status register that
gives status of FSMs in Transmit and
Receive data-paths and FIFO fill-levels
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Application Abort status bits
``
MMC (RMON) module in the GMAC
core
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Current Tx/Rx Buffer pointer as status
registers
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Current Tx/Rx Descriptor pointer as
status registers
``
Statistical counters that help in
calculating the bandwidth served
by each transmit channel when AV
support is enabled

stamp can have a resolution up to 1 ns.

Targeting a Technology
The DesignWare Ethernet MAC
10/100/1000 Universal core is designed
to easily map to most modern ASIC
(0.18 micron or below) and FPGA
technologies. The design is based
on simple rising edge flops, and is
compatible with all standard synthesis,
test insertion, and physical design flows.
Users supply standard technologyspecific compiled static memories for
the retry buffer and receive queues.
Transmit and receive FIFO sizes and
datawidths are configurable. 2-port
memory (1 read and 1 write port) are
required for the FIFOs.

Synopsys offers SystemC transaction-

``
Examples
yy Linux demonstration software

level models to build virtual platforms

for rapid, pre-silicon development of

package
yy Scripts- Design Compiler , Scan,

ATPG, and Formality

software. With a robust IP development

methodology, extensive investment in

``
Licenses downloaded from Synopsys
yy DesignWare Ethernet MAC
10/100/1000 Universal core license
yy DesignWare Verification IP Licenses

quality and comprehensive technical

support, Synopsys enables designers to
accelerate time-to-market and reduce
integration risk.
For more information on

Tools Supported
``
Simulation: VCS , NC-Verilog, MTI

Verilog

DesignWare IP, visit:

www.synopsys.com/designware.

``
Synthesis: Design Compiler , Synplify

FPGA Synthesis

About DesignWare IP
Synopsys is a leading provider of

Deliverables
The following deliverables are provided
with a DesignWare Ethernet MAC
10/100/1000 Universal core license:
``
Synopsys Ethernet Core Kit:
yy Verilog RTL source code
``
Verification environment that includes:
yy DesignWare AMBA and DesignWare
Ethernet VIP models
yy Verilog BFM models for Ethernet
PHY and Ethernet monitor
yy Verilog testbench (VTB): Example
test vectors in Verilog

high-quality, silicon-proven interface

and analog IP solutions for systemon-chip designs. Synopsys broad IP
portfolio delivers complete connectivity
IP solutions consisting of controllers,
PHY and verification IP for widely used
protocols such as USB, PCI Express,
DDR, SATA, HDMI, MIPI and Ethernet.
The analog IP family includes Analogto-Digital Converters, Digital-to-Analog
Converters, Audio Codecs, Video
Analog Front Ends, Touch Screen
Controllers and more. In addition,

``
Documentation: Users Manual

Synopsys, Inc. 700 East Middlefield Road Mountain View, CA 94043 www.synopsys.com
2009 Synopsys, Inc. All rights reserved. Synopsys is a registered trademarks of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
available at http://www.synopsys.com/copyright.html. All other names mentioned herein are trademarks or registered trademarks of their respective owners.
10/09.TT.09-18001.