Trabajo colaborativo 2

Fase grupal

Presentado por:
Fernando Guerra
Alexander Ortiz

SISTEMAS DIGITALES BASICOS

Tutora:
Diana Gissela Victoria Duque

Programa: Ing. Electrnica

Barranquilla 30 de noviembre del 2013
Universidad Nacional A Distancia
UNAD

Introduccin

En el presente trabajo daremos solucin a los problemas planteados en el

circuito suministrado al inicio de la actividad, la solucin va enfocada a la
combinacin y al lenguaje VHDL, el cual se toman cada unas de las
expresiones booleanas y se expresan mediante el lenguaje VHDL para
simularlo en active hdl.

Contenido

pagina

ACTIVIDAD 1.................................................................................................................... 4, 5,6

ACTIVIDAD 2....................................................................................................................7, 8
ACTIVIDAD 4................................................................................................................... 9,10, 11
ACTIVIDAD 5....................................................................................................................12, 13, 14
CONCLUSION..15
PANTALLAZOS DE ACTIVE HDL.......................................................................................16,17
REFERENCIAS................................................................................................................. 18

Actividad 1:
Del siguiente circuito:

1)
2) La tabla de verdad
3) Realice la implementacin en laboratorio o en simulador
Solucin actividad 1
La expresin booleana:

(AB)(ABC)(A+C)
--------------------------------------------------------------------------------- Title

: ffff

-- Design

: ffff

-- Author

: fernando

-- Company

: Microsoft

---------------------------------------------------------------------------------- File

: ffff.vhd

-- Generated : Fri Nov 29 15:02:34 2013

-- From
-- By

: interface description file

: Itf2Vhdl ver. 1.22

---------------------------------------------------------------------------------- Description :
--------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained

-- and may be overwritten
--{entity {ffff} architecture {ffff}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ffff is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;

X : out STD_LOGIC
);
end ffff;

--}} End of automatically maintained section

architecture ffff of ffff is

begin

X<=
(NOT C)));

((A AND B) AND ((NOT A) AND (NOT B) AND(C)) AND ((NOT A) OR

-- enter your statements here --

end ffff;

Actividad 2:

expresin booleana con el menor nmero de compuertas

AB'C+ AB'C'+ A'BC+ A'BC'

--------------------------------------------------------------------------------- Title

: actividad2

-- Design

: actividad2

-- Author

: fernando

-- Company

: Microsoft

-------------------------------------------------------------------------------- File

: actividad2.vhd

-- Generated : Fri Nov 29 16:16:26 2013

-- From
-- By

: interface description file

: Itf2Vhdl ver. 1.22

---------------------------------------------------------------------------------- Description :

-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained

-- and may be overwritten
--{entity {actividad2} architecture {actividad2}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity actividad2 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Y : out STD_LOGIC
);
end actividad2;

--}} End of automatically maintained section

architecture actividad2 of actividad2 is

begin
Y<=(A AND B AND (NOT C))OR ( A AND (NOT B)AND (NOT C))OR ((NOT
A )AND B AND C )OR ((NOT A ) AND B AND (NOT C ));

-- enter your statements here --

end actividad2;

Actividad 4:

ABC+ ABC+ ABC+ ABC+ ABC+ ABC+ ABC

--------------------------------------------------------------------------------- Title

: actividad4

-- Design

: actividad4

-- Author

: fernando

-- Company

: Microsoft

---------------------------------------------------------------------------------- File

: actividad4.vhd

-- Generated : Sat Nov 30 13:00:45 2013

-- From

: interface description file

-- By

: Itf2Vhdl ver. 1.22

---------------------------------------------------------------------------------- Description;
--------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained

-- and may be overwritten
--{entity {actividad4} architecture {actividad4}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity actividad4 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Y : out STD_LOGIC
);

end actividad4;

--}} End of automatically maintained section

architecture actividad4 of actividad4 is

begin
Y<= ((NOT A )AND (NOT B ) AND (NOT C ) )OR ((NOT A) AND (NOT B)
AND C )OR ((NOT A )AND B AND (NOT C))OR ((NOT A )AND B AND C )OR (A
AND (NOT B)AND ( NOT C)) OR (A AND (NOT B ) AND C )OR (A AND B AND C);

-- enter your statements here --

end actividad4;

Actividad 5:
BCD+ACD+BD

------------------------------------------------------------------------------- Title

: actividad5

-- Design

: actividad5

-- Author

: fernando

-- Company

: Microsoft

---------------------------------------------------------------------------------- File

: actividad5.vhd

-- Generated : Sat Nov 30 13:14:24 2013

-- From
-- By

: interface description file

: Itf2Vhdl ver. 1.22

---------------------------------------------------------------------------------- Description :
--------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained

-- and may be overwritten
--{entity {actividad5} architecture {actividad5}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity actividad5 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
Z : out STD_LOGIC
);
end actividad5;

--}} End of automatically maintained section

architecture actividad5 of actividad5 is

begin

Z<= (B AND C AND D ) OR ( A AND C AND (NOT D ))OR

((NOT D ) AND (NOT D));
-- enter your statements here --

end actividad5;

Conclusiones

Al finalizar este trabajo se puede determinar clara mente que el

lenguaje VHDL es muy til para la comprensin de un circuito
electrnico ya que mediante la descripcin se pueden entender
mejor todos los parmetros y lo que implica un circuito lgico.

Pantallazos de active hdl

Actividad 1

Actividad 2

Actividad 4

Actividad 5

Bibliografa
Mdulo de sistemas digitales bsico, UNAD: lenguaje VHDL

http://www.youtube.com/watch?v=OIj59kyR7wU

http://www.youtube.com/watch?v=vlaYxhhznEU