4003-440 and 4003-713 Operating Systems

Homework #7
Due February 7, 2007
Name: _______David Oguns__________________Section:
______02____________________

1. Given five memory partitions of 100 KB, 500 KB, 200 KB, 300 KB, and 600 KB (in
order), how would each of the first-fit, best-fit, and worst-fit algorithms place processes
of 212 KB, 417 KB, 112 KB, and 426 KB (in order)?
Which algorithm makes the most efficient use of memory?
The best fit algorithm makes the most efficient use of memory
Answer:
a. First-fit:
100KB -200KB
600KB 417KB

500KB 212KB, 112KB

300KB

-426KB process unallocated.

-959KB unused memory.
b. Best-fit:
100KB -200KB 112KB
600KB 426KB

500KB 417KB
300KB 212KB

-533KB memory unused.

c. Worst-fit:
100KB -200KB
600KB 212KB, 112KB
-426KB process unallocated
-959KB unused memory.

500KB 417KB
300KB

2. On a system with paging, a process cannot access memory that it does not own. How
does the operating system use paging to enforce this? How could the operating system
modify the paging scheme to allow a process to access another process memory? What
are reasons for and against allowing this?
The operating system uses a page table that labels if the frame is valid or
invalid page to use for the current process. To allow the process to use another
processes memory, the operating system could create a second page table for
external processes it has access to and associate a valid or invalid bit for each entry
there. The reason for allowing it is so that processes running on the operating
system can allow access to each others memory when they allow it. The problem is
that since page tables resides in memory which processes may be able to access
illegally, they can gain further illegal access to other processes in memory. It is a
security risk.

3. Consider a paging system with the page table stored in memory.

a. If a memory reference takes 200 nanoseconds, how long does a paged memory
reference take?
400ns
b. If we add associative registers, and 75 percent of all page-table references are found in
the associative registers, what is the effective memory reference time? (Assume that
finding a page-table entry in the associative registers takes zero time, if the entry is
there.)
.75 x 200ns + .25 x 400ns = 250ns
4. What is the purpose of paging the page tables (in other words, 2-level paging, as
shown in Figure 8.14)?
Paging large physical memory addresses would result in the page tables
being relatively large for each process. In order to reduce the size of page tables
directly to physical memory, 2-level paging is used.

5. Consider the Intel address translation scheme shown in Figure 8.22.

a. Describe all the steps that the Intel 80386 takes in translating a logical address into a
physical address.
After the CPU generates a logical address, the segmentation unit converts it
into a linear address. The linear address is given to the paging unit which finally
generates the physical address in main memory.
b. What are the advantages to the operating system of hardware that provides such
complicated memory translation hardware?
Access time is much faster using hardware registers instead of increasing the
frequency of memory accesses to translate memory addresses.
c. Are there any disadvantages to this address-translation system? If so, what are they? If
not, why is it not used by every manufacturer?
Yes there are disadvantages. Not every operating system uses the same
memory address translation system. In those cases, they have to seek a solution to
bypass the Pentium hardware and implement their own solution in hardware. This
would waste some of the hardware inside of the processor.