ECE 428 Programmable ASIC Design

FPGA Implementation of
Combinational Logic
Haibo Wang
ECE Department
Southern Illinois University
Carbondale, IL 62901
7-1

Combinational Logic Implemented by Xilinx

XC4000 CLB

Any function of up to four variables, plus any second function of up to four

unrelated variables, plus any third function of up to three unrelated variables
Any single function of five variables
Any function of four variables together with some functions of six variables
Some functions of up to nine variables.

7-2

Combinational Logic Implemented by Xilinx

XC4000 CLB
Why can any five-input function be implemented by a XC4000 CLB?

F(a, b, c, d, e) = aF(a=1) + aF(a=0)

Both F(a=1) and F(a=0) are four-input functions
a
b
c
d
e

LUT 1

F(a=1)
LUT 3

F(a,b,c,d,e)
b
c
d
e

LUT 2

F(a=0)

7-3

Combinational Logic Implemented by Xilinx

XC4000 CLB
Any function of four variables together with some functions of
six variables can be implemented by a single CLB
What kind of six variable functions can be implemented with another
four variable function within a single CLB?

F(a,b,c,d,e,f) = abF1 + abF2 + abF3 + abF4

F1 = F(a=1, b=1); F2 = F(a=1, b=0);
F3 = F(a=0, b=1); F4 = F(a=0, b=0)
Condition: Among F1-F4, three of them are constant (e.g. F1=1, F2=F3=0)

LUT 1
LUT 3
LUT 2

Six-variable function
Four-variable function
7-4

Example: A Six-Input Majority Function

Six-input majority function: the function output is 1 if three or more than
three inputs are 1.

F (a, b, c, d , e, f ) = mi

(mi Minterm of function F)

Number of inputs
with logic 1
6
5
4

Minterms
abcdef
abcdef abcdef abcdef abcdef
abcdef abcdef
abcdef abcdef abcdef abcdef
abcdef abcdef abcdef abcdef
abcdef abcdef abcdef abcdef
abcdef abcdef abcdef
abcdef
abcdef
abcdef
abcdef
abcdef

abcdef abcdef abcdef

abcdef abcdef abcdef
abcdef abcdef abcdef
abcdef abcdef abcdef
abcdef abcdef abcdef
7-5

Example: A Six-Input Majority Function

F(a=1,b=1) =e+c+fc+ed

(F1)
F(a=1,b=0) =F(a=0,b=1) = cd+ef+df+ed+fc+ec (F2, F3)
F(a=0,b=0) =cdf + cde + efc + efd

(F4)

F = abF(a=1,b=1) + abF(a=1,b=0) + abF(a=0,b=1) + abF(a=0,b=0)

= a{bF(a=1,b=1) + bF(a=1,b=0)} + a{bF(a=0,b=1) + bF(a=0,b=0)}
Fa
b
c
d
e
f
c
d
e
f

F1
Fa
F2
CLB

Fa
b
c
d
e
f
c
d
e
f

F3
Fa
F4

CLB

a
1

F
CLB
7-6

Decoding Circuits
2-to-4 Decoding circuit

x1
x2

x1x2

o1

x1x2

o2
CLB

x1x2

o3

x1x2

o4
CLB

7-7

Decoding Circuits
10-to-1024 Decoding circuit
x9

x3
x2
x1
x0

1
1

F1

F4

O1023

F5

O1022

F3
F2

Disadvantages

1
1

CLB

x8
x7
x6
x5
x4

CLB
F1= x4x5x6x7
F2= x0x1x2x3
F3= x8F1F2
F4= x9F3
F5= x9F3

It needs 1024 CLBs; expensive to implement.

It is a two level implementation, resulting large delay.
7-8

Dedicated Decoding Circuits in Xilinx FPGAs

Four dedicated programmable decoding circuits are included in
Xilinx FPAGs.
The number of decoder inputs ranges from 42 to 132 for
different devices.
The decoding circuits use wired-AND gate structures (like the
AND plane in PAL).
I/O
A

From
B CLB

I/O
C

ABC
B
AC
7-9

Combinational Logic implemented by Actel ACT1

Example

0
1

0
1

0
1

0
0
1

A
B
C

Y=ABC = C(AB) + C0
= C(B A+B0) + C0
Actel ACT1 Cell

A
B

0
1

0
1

3-input AND gate implementation

7-10

Combinational Logic implemented by Actel ACT1

For a general three-input function
F(a, b, c) = aF(a=1) + aF(a=0)
= a(bF(a=1,b=1) + bF(a=1,b=0)) + a(bF(a=0 b=1) + bF(a=0,b=0))
F(a=0,b=0)
F(a=0,b=1)

0
1

b
0
1

F(a=1,b=0)
F(a=1,b=1)

Note: F(a=1,b=1), F(a=1,b=0),

0
1

F(a=0,b=1) and F(a=0,b=0)

must be one of the the
following values: c, c, 0, 1

b
a
a

If for every variable its complement is also available, any three-input combinational
function can be implemented by a single ACT cell.
Some functions with inputs up to eight can be implemented by a single ACT1 cell.
7-11

Example: A Six-Input Majority Function

Six-input majority function: the function output is 1 if three or more than
three inputs are 1.
F(a=1,b=1,c=1) = 1
(F1)
F(a=1,b=1,c=0) = F(a=1,b=0,c=1) =F(a=0,b=1,c=1) = e+f+d
(F2,F3,F4)
F(a=1,b=0,c=0) =F(a=0,b=1,c=0) = F(a=0,b=0,c=1) = ef+df+ed (F5,F6,F7)
F(a=0,b=0,c=0) = efd

(F8)

F = abcF1 + abcF2 + abcF3 + abcF4 + abcF5 + abcF6 + abcF7 + abcF8

= ab(cF1+cF2) + ab(cF3+cF5) + ab(cF4+cF6) + ab(cF7+cF8)

F1

F2

F3

F4

= a(bF1 + bF2) + a (bF3 + bF4)

H1

H2
7-12

Example: A Six-Input Majority Function

d
1
f

0
1
0
1

0
1

F2, F3, F4
d+f+e

1
e

0
d
f
d
1
f

0
1
0
1

0
1

0
d
f
e

0
1

0
1

F2
0
1

H1

F1

H2
H1
a

0
1
0
1

F
0
1

ef+df+ed

F8
0
1

0
1

F5, F6, F7

0
1

F5
F3
c
F2
F1
c
b

F8
F7
c
F6
F4
c
b

0
1
0
1

F4
0
1

H2

F3

edf
7-13

Decoding Circuits
4-to-16 Decoding circuit
a
0

0
1
0
1

b
0
1

0
0

O0

abcd

a a b b c c d d

d
It needs 16 ACT1 cells

Decoder circuits with more than four inputs need multi-level

implementation.
7-14

Decoding Circuits
A 10-to-1024 decoder needs

x0
cell

x0

x4~x7

4-to16

x9 x8~x9

2-to-4

x0~x3

4-to16

It needs 1070 ACT1 cells

cell
x9

level1

level2
level3

Actel FPGAs also use dedicated decoding circuits.

7-15

Speed Considerations
For a combinational circuit implemented by a single memory block, its delay
depends on neither the function type nor the input transition patterns.
Memory
For a combinational circuit implemented by mux-based FPGAs, its delay
normally depends on the function type and the input transition patterns.
0
1

1
0
1

0
a

0
1
0
1

0
F1=a

1
b
a

0
1

0
1

The delay of F1 is smaller

than that of F2
For F2, d1 is the output delay
when inputs switch from
F2=ab a=1 and b=1 to a=0 and b=1;
d2 is the delay when inputs
switch from a=1 and b=1 to
a=1 and b=0.

d2 > d1
Assume the delay of OR gate is smaller than that of MUX

7-16

Speed Considerations
To reduce propagation delay, always place signals which arrive late
close to the output.
Bad

Good
a
b
c
d
e

a
b
c
e
d

CLB
LUT1
LUT2

CLB
LUT1
LUT2

Signal e always arrives late

Good

0
1

0
1
b
a

0
1

0
1

Bad

0
1

0
F2=ab

1
a

0
1

0
1

F2=ab

b
Signal a always arrives late

7-17

Other Considerations
Always try to balance signal paths to avoid glitches

CLB

CLB

CLB

If possible, change circuit

implementation into the
following style
a

CLB
CLB

CLB

7-18