2.1.

1 INTRODUCTION
PIC16F877A is the heart of this system. It consists of clock circuit
and power on reset circuit. Clock circuit is build around crystal oscillator and
ceramic capacitor. Purpose of crystal oscillator is to stabilize the frequency and the
capacitor is to stabilize the amplitude if the clock. This circuit determines the
operating speed. Here we use 4MHz crystal oscillator, so the microcontroller will
work at the speed of 1uSec. Purpose of the microcontroller is to control the speed
of the DC shunt motor according to the load. It uses internal ADC and complete
one port for reading load and control the speed. That is it reads voltage output and
produces the digital output according to this input voltage. This microcontroller
will set the load limit and terminate the DC shunt motor to prevent from over load.
2.1.2 BOARD FEATURES
Includes 3 Zip Sockets to Program various series of PIC
Microcontrollers
PIC16F877A Microcontroller provided along with the chip
A Serial Port for In-System Programming
A Serial Port for RS232 Communication
Connector provided to connect LCD
4 , 7-Segment Displays with chip select facility using a Dip
Switch
LEDs Connected to all I/Os
Keys Connected to all I/Os
Pin outs for Port extension for users ease
2.1.3 CHIP FEATURES

 High-Performance RISC CPU

Only 35 single-word instructions to learn
10-bit, up to 8-channel Analog-to-Digital Converter (A/D)
Self-reprogrammable under software control
Operating speed: DC 20 MHz clock input
Low-power consumption
Up to 8K x 14 words of Flash Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM),
Up to 256 x 8 bytes of EEPROM Data Memory
14 interrupts ,3 timers.
2.1.4 PIN DIAGRAM

Figure 2.1.1 Pin diagram of PIC16F877A

2.1.5 ARCHITECTURE OF PIC16F877A

Figure 2.1.2 Architecture of PIC16F877A

2.1.6 MEMORY ORGANIZATION

There are three memory blocks in each of thePIC16F87X
MCUs. The Program Memory and Data Memory have separate buses so that
concurrent access can occur and is detailed in this section.
2.1.6.1 PROGRAM MEMORY ORGANIZATION
The PIC16F87X devices have a 13-bit program counter
capable of addressing an 8K x 14 program memory space. The PIC16F877/876
devices have 8K x 14words of FLASH program memory, and thePIC16F873/874
devices have 4K x 14. Accessing allocation above the physically implemented
address will cause a wraparound. The RESET vector is at 0000h and the interrupt
vector is at 0004h.
2.1.6.2 DATA MEMORY ORGANIZATION
The data memory is partitioned into multiple banks which
contain the General Purpose Registers and the Special Function Registers. Bits
RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. Each bank
extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for
the Special Function Registers. Above the Special Function Registers are General
Purpose Registers, implemented as static RAM. The Special Function Registers
can be classified into two sets: core (CPU) and peripheral. All implemented banks
contain Special Function Registers. Some frequently used Special Function
Registers from one bank may be mirrored in another bank for code reduction and
quicker access.
2.1.7 I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the device. In general, when a
peripheral is enabled, that pin may not be used as a general purpose I/O pin.
2.1.7.1 PORT A & THE TRISA REGISTER
PORTA is a 6-bit wide, bi-directional port. The
corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will
make the corresponding PORTA pin an input (i.e., put the corresponding output
driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., put the contents of the output latch on
the selected pin).Reading the PORTA register reads the status of the pins, whereas
writing to it will write to the port latch. All write operations are read-modify-write
operations Therefore, a write to a port implies that the port pins are read; the value
is modified and then written to the port data latch. Pin RA4 is multiplexed with the
Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKIpin is
a Schmitt Trigger input and an open drain output .All other PORTA pins have TTL
input levels and full CMOS output drivers .Other PORTA pins are multiplexed
with analog inputs and analog VREF input. The operation of each pin is selected
by clearing/setting the control bits in theADCON1 register (A/D Control
Register1).
2.1.7.2 PORT B &THE TRISB REGISTER
PORTB is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will
make the corresponding PORTB pin an input (i.e., put the corresponding output
driver in aHi-Impedance mode). Clearing a TRISB bit (= 0) will make the
corresponding PORTB pin an output (i.e., put the contents of the output latch on
the selected pin).Three pins of PORTB are multiplexed with the Low Voltage
Programming function: RB3/PGM, RB6/PG C and RB7/PGD. The alternate

functions of these pins are described in the Special Features Section. Each of the
PORTB pins has a weak internal pull-up. A single control bit can turn on all the
pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak
pull-up is automatically turned off when the port pin is configured as an output.
The pull-ups are disable don a Power-on Reset. Four of the PORTB pins,
RB7:RB4, have an interrupt on-change feature. Occur (anyRB7:RB4pinconfigured
as an output is excluded from the interruption.
2.1.7.3 PORT C & THE TRISC REGISTER
PORTC is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will
make the corresponding PORT C pin an input (i.e., put the corresponding output
driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the
corresponding PORTC pin an output (i.e., put the contents of the output latch on
the selected pin).PORTC is multiplexed with several peripheral functions .PORTC
pins have Schmitt Trigger input buffers. When the I2C module is enabled, the
PORTC<4:3>pins can be configured with normal I2C levels, or with SMB us
levels by using the CKE bit (SSPSTAT<6>).When enabling peripheral functions,
care should be taken in defining TRIS bits for each PORTC pin. Some peripherals
override the TRIS bit to make a pin an output, while other peripherals override the
TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the
peripheral is enabled, read-modify write instructions (BSF, BCF, and XORWF)
with TRISC as destination, should be avoided. The user should refer to the
corresponding peripheral section for the correct TRIS bit settings.
2.1.7.4 PORT D & TRISD REGISTERS
PORTD and TRISD are not implemented on thePIC16F873
or PIC16F876.PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin
is individually configure able as an input or output .PORTD can be configured as

an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSP
MODE (TRISE<4>). In this mode, the input buffers are TTL.
2.1.7.5 PORT E & TRISE REGISTER
PORTE and TRISE are not implemented on thePIC16F873
or PIC16F876.PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 ,and
RE2/CS/AN7) which are individually configure able as inputs or outputs. These
pins have Schmitt Trigger input buffers.
2.1.8 DATA EEPROM &FLASH PROGRAM MEMORY
The Data EEPROM and FLASH Program Memory are read
able and writable during normal operation over the entire VDD range. These
operations take place on a single byte for Data EEPROM memory and a single
word for Program memory. A write operation causes an erase-then-write operation
to take place on the specified byte or word. A bulk erase operation may not be
issued from user code (which includes removing code protection).Access to
program memory allows for checksum calculation .The values written to program
memory do not need to be valid instructions .Therefore, up to 14-bitnumbers can
be stored in memory for use as calibration parameters, serial numbers, packed 7-bit
ASCII, etc. The EEPROM Data memory is rated for high erase/write cycles
(specification D120). The FLASH program memory is rated much lower
(specification D130), because EEPROM data memory can be used to store
frequently updated values. An on-chip timer controls the write time and it will vary
with voltage and temperature, as well as from chip to chip. Please refer to the
specifications for exact limits (specifications D122 andD133).A byte or word write
automatically erases the location and writes the new value (erase before write).
Writing to EEPROM data memory does not impact the operation of the device.
Writing to program memory will cease the execution of instructions until the write

is complete. Read and write access to both memories take place indirectly through
a set of Special Function Registers (SFR).
The six SFRs used are:
EEDATA
EEDATH
EEADR
EEADRH
EECON1
EECON2
2.1.9 TIMER0 MODULE
The Timer0 module timer/counter has the following features:
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
2.1.9.1 TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting of two
8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1
Register pair (TMR1H:TMR1L) The Special Function Registers can be classified
intotwo sets: core (CPU) and peripheral. increments from 0000h to FFFF hand
rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt
enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE
(PIE1<0>).Timer1 can operate in one of two modes:

 As a timer
As a counter
The operating mode is determined by the clock select bit,
TMR1CS (T1CON<1>).In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising edge of the external clock
input.Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON
(T1CON<0>). Timer1 also has an internal RESET input. This RESET can be
generated by either of the two CCP modules (Section 8.0). Register 6-1 shows the
Timer1control register.
2.1.9.2 TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a postscaler. It
can be used as the PWM time-base for the PWM mode of the CCP module(s). The
TMR2 register is readable and writable, and is cleared on any device RESET. The
input clock (FOSC/4) has a prescale option of 1:1,1:4, or 1:16, selected by control
bitsT2CKPS1:T2CKPS0 (T2CON<1:0>).The Special Function Registers can be
classified into two sets: core (CPU) and peripheral. The Timer2 module has an 8bit period register, PR2.Timer2 increments from 00h until it matches PR2 and then
resets to 00h on the next increment cycle. PR2 is a readable and writable register.
The PR2 register is initialized to FFh upon RESET. The match output of TMR2
goes through a 4-bitpostscaler (which gives a 1:1 to 1:16 scaling inclusive) to
generate a TMR2 interrupt (latched in flag bitTMR2IF, (PIR1<1>)).Timer2 can be
shut-off by clearing control bit TMR2ON (T2CON<2>), to minimize power
consumption.
2.1.10 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE

The Master Synchronous Serial Port (MSSP) module is a

serial interface, useful for communicating with other peripheral or microcontroller
devices. These peripheral devices may be serial EEPROMs, shift registers, display
drivers, A/D converters, etc.
The MSSP module can operate in one of two modes:
Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I2C
2.1.10.1 SPI MODE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four modes of SPI are supported. To
accomplish communication, typically three pins are used:
Serial Data out (SDO)
Serial Data in (SDI)
Serial Clock (SCK)
2.1.10.2 I2C MASTER MODE SUPPORT
Master mode is enabled by setting and clearing the appropriate
SSPM bits in SSPCON and by setting the SSPEN bit. Once Master mode is
enabled, the user has six options:
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA and SCL.
3. Write to the SSPBUF register initiating transmission of data/address.
4. Generate a STOP condition on SDA and SCL.
5. Configure the I2C port to receive data.
6. Generate an Acknowledge condition at the end of a received byte of data.
2.1.11

UNIVERSAL

SYNCHRONOUS

TRANSMITTER (USART)

ASYNCHRONOUS

RECEIVER

The Universal Synchronous Asynchronous Receiver Transmitter

(USART) module is one of the two serial I/O modules. (USART is also known as a
Serial Communications Interface or SCI.) The USART can be configured as a full
duplex asynchronous system that can communicate with peripheral devices such as
CRT terminals and personal computers, or it can be configured as a half duplex
synchronous system that can communicate with peripheral devices such as A/D or
D/A integrated circuits, serial EEPROMs etc.
The USART can be configured in the following modes:
Asynchronous (full duplex)
Synchronous - Master (half duplex)
Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure
pins RC6/TX/CK andRC7/RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter. The USART module also has a multi-processor
communication capability using 9-bit address detection.
2.1.12 A/D CONVERTER
Clearing the GO/DONE bit during a conversion will abort the current
conversion. The A/D result register pair will NOT be updated with the partially
completed A/D conversion sample. That is, the ADRESH: ADRESL registers will
continue to contain the value of the last completed conversion (or the last value
written to the ADRESH: ADRESL registers). After the A/D conversion is aborted,
a 2TAD wait is required before the next acquisition is started. After this 2TAD
wait, acquisition on the selected channel is automatically started. The GO/DONE
bit can then be set to start the conversion.
2.1.13 INTERRUPTS OF PIC 16F877A
The PIC16F877 A family has up to 14 sources of interrupt. The
interrupt control register (INTCON) records individual interrupt requests in flag

bits. It also has individual and global interrupt enable bits. A global interrupt enable
bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an Interrupts flag bit and
mask bit are set, the interrupt will vector immediately. Individual interrupts can be
disabled through their corresponding enable bits in various registers. Individual
interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared
on RESET. The return from interrupt instruction, RETFIE, exits The interrupt
routine, as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin
interrupt, the RB port change interrupt, and the TMR0 overflow interrupt flags are
contained in the INTCON register .The peripheral interrupt flags are contained in
the special function registers, PIR1 and PIR2. The corresponding interrupt enable
bits are contained in special Function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function register INTCON.When an
interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the
return address is pushed onto the stack and the PC is loaded with 0004h. Once in
the Interrupt Service Routine, the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software
before re-enabling interrupts to avoid recursive interrupts. For external interrupt
events, such as the INT pin or PORTB change interrupts, the interrupt latency will
be three or four instruction cycles. The exact latency depends when the interrupt
event occurs. The latency is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of their corresponding mask bit,
PEIE bit, or GIE bit.
2.1.14 WATCH DOG TIMER (WDT)
The Watchdog Timer is a free running on-chip RC oscillator which
does not require any external components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if

the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP instruction .During normal
operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If
the device is in SLEEP mode, a WDT time-out causes the device to wake-up and
continue with normal operation (Watchdog Timer Wake-up). The TO bit in the
STATUS register will be cleared upon a Watchdog Timer time-out.
2.1.15 POWER DOWN MODE
Power-down mode is entered by executing a SLEEP instruction. If
enabled, the Watchdog Timer will be cleared but keeps running, the PD bit
(STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and is turned off. The
I/O ports maintain the status they had before the SLEEP instruction was executed
(driving high, low, or hi-impedance).For lowest current consumption in this mode,
place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing
current from the I/O pin, power-down the A/D and disable external clocks.
2.1.16 PIC 16F877A INSTRUCTION SET
PIC has a RISC based instruction set consisting of about 35
instructions. Almost all the data movements must be carried though the w
register. Instruction set can be categorized as
1. Data movement instructions
2. Data processing instructions
3. Execution change instructions
4. Processor control instructions
Microchips mid-range 8-bit microcontroller family uses a 14-bit wide instruction
set. This instruction set consists of 36 instructions, each a single14-bit wide word.
Most instructions operate on a file register, f, and the working register, W
(accumulator). The result can be directed either to the file Register or the W
register or to both in the case of some instructions. For byte-oriented instructions,

f represents a file register designator and d represents a destination

designator.The file register designator specifies which fileregister is to be used by
the instruction.

fr: one of the 80 memory ram positions implemented as 8 bit registers (File
Register Set or FRS) (0 =< fr <= 4f). The first 12 are special purpose
registers (SFR) and the other 68 are general purpose registers(GPR).

W: 8 bit accumulator of the Arithmetic Logic Unit (ALU)

d: mnemonic for the destination of one operation, which can be 1 ( a file

register f) or 0 (the accumulator w)

k: an 8 bit literal

b: 3 bit literal identifying one bit of a byte (0: least significant bit, 7: most
significant bit). Example: f(7)

addr: 11 bit literal representing an instruction address

C: Carry bit = STATUS(0)

Z: Zero bit = STATUS(2)

DC: Digit Carry bit = STATUS(1)

opr: mnemonic for one of the following binary operations:

add - addition

sub - subtraction

and - logical and

or - logical or