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WP 14 and Timing Sync

Eiscat Technical meeting
20131105
Leif Johansson National Instruments

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Eiscat
Syncronisation

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Signal vs. Time-Based Synchronization

Signal-Based

Share Physical Clocks / Triggers

Time-Based

Generate Signals

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Share Time

Ethernet (1588)
IRIG
GPS
Etc.

4

Generate Signals

Cooperation: NI and CERN White Rabbit

Partnering with CERN in developing White Rabbit (WR)
Performance

Distance: > 10 km
Scale: > 2000 nodes
Accuracy: < 1ns skew, < 100 ps jitter
o

Leverage Industry standards (802.x, IEEE 1588, SyncE)

Compensates for propagation delay (cable length, temperature variation,

etc.)

Gigabit Ethernet communication with deterministic capability

Generally Applicable

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White Rabbit PXI_Clk10

Disciplining Performance

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NI FlexRIO

PXI/ PXIe

NI FlexRIO Adapter Module

NI FlexRIO FPGA Module

PXI Platform

Interchangeable I/O
Digital or analog
NI FlexRIO Adapter Module
Development Kit (MDK)

Virtex-5 FPGA
132 digital I/O lines
Up to 512 MB of DRAM
Peer-to-peer data streaming

Data transfer
Synchronization
Clocking/triggers
Power/cooling

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Setup
Master PXI Chassis
PXI_Clk10

Att

PXI-6685
White Rabbit Master

Att
White Rabbit
Fiber Optic
Connection

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Ch1

PXIe-5186
Simultaneously sampled
8-bit vertical resolution
6.25GS/s sampling rate

Slave PXI Chassis

PXI-6685
White Rabbit Slave

Ch0

PXI_Clk10

Measurement
PXI systems will be allowed to warm up with free running
PXI_Clk10s for an hour
When Systems have warmed up the PXI_Clk10s are
attach to the corresponding Time Keepers, initiating
PXI_Clk10 Disciplining.
Measurements

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While logging the phase of the master and slave is aligned by

changing Phase lock offset on the slave.
For an hour the time delay is measured every 250ms.
For 72 hours the time delay is measured every 10sec.

PXI_Clk10 Phase alignment

Fine adjustment

Initial Adjustment

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PXI_Clk10 Stability first hour

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11

PXI_Clk10 Stability over 72 hours

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White Rabbit Absolute Time

Based Triggering Performance
October 2013

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Absolute Time
Absolute time is maintained by the Time Keeper on each
device.
This absolute time resolution is 10ns (100MHz).
When White Rabbit is enabled absolute time is locked
between master and slave.

The absolute time difference between master and slave is

constant but not necessary zero.

The absolute time is used for:

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Hardware Time Stamping of events (signal edges)

Scheduling Future Timed Events (FTEs)

14

Aligning Absolute Time

Align 100ns (10MHz) multiples of absolute time to
PXI_Clk10 edges on master and slave.
Generate a FTE from the Master trough a coax cable and
time stamp this on the Slave.

When sending an FTE on an 100ns multiple we can remove

propagation delay when the cable propagation delay is <100ns.
PXI_Clk10s are aligned and thus the 100ns multiples of absolute
time are also aligned in previous step.

Share the FTE time with the Slave over UDP

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This allows the slave to calculate its offset from the master and
adjust its absolute time to match the masters absolute time.
Round Slave time-stamp down to nearest 100ns multiple.
Adjustment = FTE Time rounded time stamp
15

Sample Clock Generation

The NI-5761R requires a
100MHz external clock.
This can be generate using
the DDS of a PXI-6653 in
slot 3.
The DDS is clocked with
PXI_Clk10.
To make sure the sample
clocks are phase aligned
the update is triggered PXI-6685
White Rabbit Slave
using a FTE trigger.

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Master PXI Chassis

FTE Trigger

PXI_Clk10

DDS

Sample Clock

White Rabbit
Connection

Slave PXI Chassis

FTE Trigger

PXI_Clk10

DDS

Sample Clock

Sample Clock Performance

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Triggering NI-5761R Setup

Master PXI Chassis
PXI-6685
PXI-6653

100MHz

Ch0

NI-5761R

White Rabbit
Connection

PXIe-5441
100MS/s, 16bit Arbitrary
Waveform generator
Generating 1MHz Sine

Slave PXI Chassis

PXI-6685
100MHz

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Ch0

PXI-6653
Ch0

NI-5761R
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Triggering NI-5761R Performance Measurement

The systems are allowed to warm up and white rabbit
PXI_Clk10 Disciplining enabled and phases aligned phase.
Absolute time is aligned as described.
Sample Clock Generation is started using a FTE trigger.
Measurement

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The NI-5761Rs acquires 1024 sample of channel 0 when it

detects a FTE Trigger on the Trigger bus.
The master collects the records and calculates the delay between
master and slave.
The time delays are logged to disk.

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Triggering NI-5761R Performance one hour

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Triggering NI-5761R Performance 72 hours

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*This is filtered data see notes

21

PXI_Clk10 Stability over 72 hours for Compare

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WP 14

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Cost estimate
Example Electronics for beam former

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Possible cost reduction

Configurable vs Modular (Mechasnical design)

FPGA cost optimisation

Channel density

Delay lines

Component prices reduction

Specification adjustment

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25

System Engineering

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Prototype System example PXIe

1085 Chassis Capabilities
60 AI channels/chassis
10 Gb/s (1.25 GB/s) per hop
Each FPGA module sources
& sinks a 10 Gb/s stream

To RMC-8355
with 10 GbE
PCIe card

Each green hop is

10 Gb/s sustained
and 4-5 us of
latency

1085 Chassis Configuration

(1) PXIe-8381 Gen2 x8 MXI
(1) PXIe-8384 Gen2 x8 MXI
(1) PXIe-???? T&S Module
(15) PXIe-7976R FlexRIO
(15) NI 5734 Digitizer FAMs

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27

What we need to consider

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Manufacturing Products

Access to chip suppliers

Roadmap visibility
Lifetime buy options

Volume manufacturing
Reliability testing

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Radiation, magnetic field,

altitude

29

Long term availability

Compliance / Certifications

Specialty testing

Lifecycle management

Reliability / availability

ITAR and others

CE, ROHS, China ROHS,
WEEE

Environmental conditions

Environmental Testing
System Reliability

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System Reliability

NI System Reliability Lab

Mission: Assess the reliability of National Instruments

product-based systems and drive product improvements

Created to focus on system reliability for the

o Compact

RIO and PXI / PXIe hardware platforms

o LabVIEW software platform

MTTF for PXIe-1075 is >20yrs

MTTF for cRIO system (controller and chassis) is
about 38yrs

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31

System Reliability
PXI/PXIe Reliability Testing
22 systems

20 systems at room temperature and 2

systems in temperature chamber
(cycles between 5C and 50C three
times per day)
5 systems running on dirty power

3 different hardware configurations

32 test applications running on
Windows and RT
24/7 execution during missions

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32

System Reliability
cRIO Reliability Testing
40 systems

32 systems at room temperature

and 8 systems in temperature
chamber (cycles between -40 and
70C three times per day)
8 systems running on dirty power

4 unique cRIO applications written

for RT and FPGA (10 systems for
each)
24/7 execution during mission

We run one or two missions per

year
Mission time ranges from 3 to 12
months

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33

System Reliability

Temperature Chamber

Cycle Temperature three

times per dayfor months

2 to 8 Systems run for

months at time in this
environment
PXI / PXIe 5C to 50C
cRIO - 40C to 70C

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System Reliability

Dirty Power Test Station

[Simulates a bad power grid]
5 to 8 Systems run for months at time in
this environment
Vary frequency from 47 to 63 Hz
Vary voltage level from 90 to 264 V

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35

RASM

ni.com

RASM = Reliability,Usability
Availability, Serviceability,
Manageability
Customers require a continual
output of features and innovation

Features
RASM
Customers highly value stability,
reliability, and availability

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RASM Defined
Reliability

Availability

A system operates as
intended, without failure or
down time, and satisfies the
desired performance
requirements.

The measure of how often a

systems is able to perform its
intended function, even in the
midst of failures.

Features and aspects of the

system design contributing to
ease of diagnosis and repair.

The extent to which a system
can be controlled, supervised
and monitored.

Serviceability

Manageability

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38


Approaches
to Maximizing Uptime

Supplier quality
Reliability lab testing
Simplified design
Site surveys

Convert failure to a planned outage

Eliminate the failure

Predictive failure analysis/alerts

Planned maintenance
Replacement inventories

Redundancy
Remote diagnostics
ECC, event logs, etc.
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Tolerate the failure

39

Life Cycle Management

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Sustainment-Dominated Life Cycle

Long operation and support phases

Operation & Support

Component A.1

Component A.2

Component A.3

Component A.4

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ni.com