Microelectronics Reliability 54 (2014) 26822687

Contents lists available at ScienceDirect

Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Methodology for accurate extrapolation of InGaP/GaAs HBT safe

operating area (SOA) for variations in emitter area and ballast resistor
size
Robert S. Howell, Randall Lewis, H. George Henry , Harold Hearne, Deas Brown, Dale Dawson, Andris Ezis
Northrop Grumman Corporation (Electronic Systems), Linthicum, MD 21090, USA

a r t i c l e

i n f o

Article history:
Received 8 July 2014
Received in revised form 4 September 2014
Accepted 15 September 2014
Available online 5 October 2014

a b s t r a c t
The authors present a methodology for extrapolating the safe operating area for HBTs, accounting for
variations in emitter area and ballast resistor size. Measurements of SOA curves for HBTs with varying
emitter areas and ballast resistor sizes were made, and a simple mathematical extrapolation developed
for other SOA curves. This extrapolation was successfully demonstrated as predicting a further SOA curve.
2014 Elsevier Ltd. All rights reserved.

Keywords:
Current collapse
HBT
SOA

1. Introduction
InGaP/GaAs HBTs are an outstanding solution for a number of
RF circuit design problems; however failure during operation is
known to occur for these devices due to a number of effects. These
include current multiplication and avalanche breakdown, thermal
runaway from the positive feedback loop between temperature
and current ow for HBTs, and current collapse, where one nger
of a multi-nger device exhibits thermal runaway while effectively
turning off the other ngers, reducing total current. Each of these
mechanisms can lead to catastrophic failure, but current multiplication, thermal runaway and current collapse all interact together
to a degree, making it difcult to distinguish one from another.
Thus, an essential element of the Process Design Kit (PDK) for
any InGaP/GaAs HBT process is a well-dened safe operating area
(SOA) within which it can be condently operated without fear
of failure due to any of these effects. An example of an SOA curve
is shown in Fig. 1.
Denition of the SOA is accomplished by measuring the ICE as a
function of VCE for different base current drives, generating a series
of curves, and dening the SOA boundary based on the inection
point for each ICE vs. VCE curve (this inection is often also accompanied by catastrophic failure). This is the green line1 shown in Fig. 1.
Corresponding author. Tel.: +1 (410) 765 7666.
E-mail addresses: rs.howell@ngc.com (R.S. Howell), george.henry@ngc.com
(H.G. Henry).
1
For interpretation of color in Fig. 1, the reader is referred to the web version of
this article.
http://dx.doi.org/10.1016/j.microrel.2014.09.018
0026-2714/ 2014 Elsevier Ltd. All rights reserved.

However, this experimentally derived SOA curve is valid for

only the specic layout and corresponding ballast resistor of the
tested HBT. As RF designers often require a tailored set of HBT
device peripheries and ballasting to meet specic RF performance
metrics (e.g. power handling, noise gure, linearity, etc.), this can
be a serious limitation. A more general set of SOA curves is of great
use within an InGaP/GaAs HBT PDK. As will be described here, this
was accomplished by characterizing a variety of HBTs of differing
geometries and ballast resistors in the fashion shown in Fig. 1
and using this data to build simple linear extrapolations of the
SOA curves as functions of nger area and ballast resistance. The
methodology was validated by performing extrapolations for a
geometry that had not been used in formulating the SOA extrapolation relationships and then comparing measured to predicted
SOA curves. Excellent agreement was achieved.
2. Materials and methods
The HBTs used in this study were fabricated at the Northrop
Grumman Advanced Technology Lab using the ATL HBTG1 process
[2]. It employs the InGaP/GaAs MOCVD epitaxial structure shown
in Fig. 2 with a uniformly-doped collector. The process ow is
emitter-rst and the minimum emitter dimension is 2 lm. A
cross-section cartoon illustrating the emitter-centered layout is
in Fig. 3 and a typical fabricated device is shown in Fig. 4. The emitter area can be increased by increasing the long dimension of the
emitters and/or adding more ngers. NiCr ballast resistors are
available to be added between emitter and ground. These are used
to suppress failures due to current collapse into a single emitter

R.S. Howell et al. / Microelectronics Reliability 54 (2014) 26822687

nger leading to thermal runaway and burnout. The suppression

occurs dynamically. As the current in a single nger rises, the voltage drop across the ballast resistor rises, reducing VCE across that
nger which reduces ICE for that nger, preventing runaway and
transferring more current to the other ngers. Similar suppression
is accomplished in other labs using ballast resistors in the base circuit. Values of Rballast are chosen depending upon the performance
demands of the circuit and values as high as 40 X have been used.
Insertion of ballast resistors involves a tradeoff with efciency and
gain. Baseline HBTs normally exhibit Ft = 35 GHz, DC b = 100, and
base/collector breakdown 35 V. They are integrated into a full
MMIC process which includes MIM capacitors, NiCr thin lm resistors (mentioned above), three levels of metal interconnects
(including metal on BCB), thinning to 100 lm, and through-wafer
vias.
Table 1 is a list of the devices chosen for this study and their
range of geometries and ballast resistors. These samples were chosen from a total of six HBTG1 fabrication lots so samples of the
same geometry can be compared lot-to-lot and wafer-to-wafer
within lots. The SOA curves for these HBT geometries were established using the set up shown diagrammatically in Fig. 5. HBTs
were mounted in 40 pin packages with good heat sinking to the
package. External capacitors and resistors, also shown in the diagram, were included in the base and collector circuits to prevent
oscillation during testing. To provide a sense of the lot to lot and
wafer to wafer variation for SOA, the same test device geometries
were harvested from different lots (e.g. congurations B & E in
Table 1) and different wafers within the same lot (e.g. congurations A1 and A2 in Table 1). Several HBTs of each conguration
were tested using 80 ls pulse widths to determine the loci of the
inection points for the ICE vs. VCE curve for a number of current
drives. This ICE/VCE test frequently caused catastrophic device failure and new devices were required to generate a complete set of
SOA curves across a broad range of VCE values. The full loci are a
composite of tests performed on multiple identical devices identically packaged. A very high degree of repeatability was observed
from one device to the next. Sample data illustrating the development of a full SOA loci of points is shown in Figs. 6 and 7. The
resulting collapse loci for all the HBTs tested within each conguration were then tted with the power function ICE,SOA = AVCEB. The
A and B tting parameters derived for all measured HBTs are
shown in Table 2. Of note, the B parameter is essentially constant
at 1.9, the variation from structure to structure being accounted
for by the A parameter. Similar data was taken at 50 C and

Inside SOA
Desired region for
device operation

Outside SOA
Active region for:
current multiplication
thermal runaway
current collapse

Fig. 1. Example ICE vs. VCE set of measurement curves, showing onset of failure at
high voltage and current levels. The loci of points forming the inection points to
the right determine the resulting safe operating area (SOA) limits for the given HBT
geometrical conguration.

2683

Base pad
p+ GaAs

Fig. 2. MOCVD epitaxial structure used for NGES ATL HBTG1.

Fig. 3. The HBT is emitter-centered and air bridged to the via-grounded thin lm
ballast resistor.

Fig. 4. Layout of a baseline four emitter nger HBT. Emitter area is increased by
adding or lengthening the emitter ngers. NiCr emitter ballast resistors of a range of
values can be added to suppress thermal runaway.

+125 C. To accomplish this, while the data was being taken the
samples were placed in a Thermostream which uses a local very
high rate airow to cool or heat a package. The curves were similar
to those obtained at room temperature.
The test procedure adopted here is similar to the Ib mode
described in [1]. Results reported there were qualitatively quite
similar to those achieved here. The ICE, VCE loci data reported in
[1] could also be tted to an ICE,SOA = AVCEB power function. Of particular note, the B value was also approximately 1.9. This appears
to be characteristic of HBTs with uniformly-doped collectors.
Devices with split collector doping show altered non-smooth ICE/
VCE relationships [3].

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R.S. Howell et al. / Microelectronics Reliability 54 (2014) 26822687

Table 1
HBT device congurations measured for SOA values. Dimensions describe the HBT emitter nger geometries, using a constant nger width and variable nger length and number
of ngers. Emitter nger width and length are given in units of microns. Conguration name assigns a letter name to each set of HBTs with a different geometry and/or ballast
resistor from a given lot or wafer (e.g. Congurations B and E had the same device layout and ballast resistance, but came from different lots, Conguration A1 and A2 had the
same device layout, ballast resistance, and lot origin, but came from different wafers within the lot).
Conguration name

A1, A2

B&E

C&D

F&G

Dimensions (emitter) (W  L  ngers)

Ballast resistance (X)

2  20  4
0

2  20  4
5

2  20  4
7

2  10  4
5

2  20  8
10

Fig. 7. Sample of composite data for a single curve for an HBT designed with 4
2lm  10 lm ngers and a 5 X ballast resistor. Data is from seven separate
samples and is quite repeatable. Max ICE for the HBTG1 is limited due to reliability
considerations so regions of high ICE are of less interest.
Fig. 5. Diagram of test set-up used to experimentally determine SOA curves for
InGaP/GaAs HBTs. The 40-pin package used for assembly of HBTs with external
oscillation suppression capacitors and resistors is at upper left.

Fig. 6. Sample SOA data taken using the methodology illustrated in Fig. 4 and
described above and illustrating the various criteria used to dene the SOA
boundry.

It should also be noted that data presented here is DC only. Evidence exists [4] that the SOA for RF operation is larger than that for
DC. Thus, these SOAs are worst case.
3. Results
The size of the area subtended by the HBT SOA locus and ICE/VCE
axes was shown to be a strong function of the ballast resistor and
total emitter area.

The measured impact of ballast resistors on SOA is shown in

Fig. 8. As is discussed above, ballast resistors are added into HBT
layouts to promote stability, and decrease the likelihood of catastrophic failure from current collapse in a single emitter nger
and thermal runaway. This is validated by the result obtained here
as the SOA increases with the addition and increasing value of the
ballast resistor. Fig. 8 also shows that consistency of measured SOA
values was very high, both for lot to lot uniformity, as exemplied
by the curve pairings of BE, CD and FG, as well as with wafer to
wafer uniformity within a lot, as exemplied by the curve pairing
A1A2.
With total emitter area equal to nger width  nger
length  number of ngers, a net increase in emitter area increases
the SOA size. This is to be expected, as a larger area decreases the
current density and decreases the self-heating effects which can
lead to current collapse. This effect is highlighted in Fig. 9 which
compares the SOAs of increased emitter area HBTs with a constant
ballasting resistor value. The SOA curve moves out towards the
right. The area can be increased by either widening the individual
ngers or adding additional ngers. Both approaches have drawbacks. Very large single emitters can have reduced RF performance
and variability of usage across the area. Additional ngers increase
the probability of current collapse and reduced SOA as is discussed
below.
As a check, SOA measurements were performed using a single
base drive for a single emitter nger HBT. A single nger eliminates
the possibility of current collapse and would provide a gauge on
the importance of this failure mechanism for the multi-nger
HBTs. The results comparing SOA for a 2 lm  20 lm emitter
structure against the Device A1 2 lm  20 lm  4 emitter nger
structure with zero ballast resistor is shown in Fig. 10. ICE was normalized in kA/cm2 in this case. That the SOA area for the 4 nger
structure is much smaller than for the single nger indicates that
current collapse for multi-nger structures plays an important role
in causing early failure. This emphasizes the importance of the

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Table 2
Measured SOA tting parameters.
Summary of measured SOA results, ICE,SOA = AVCEB
Device conguration

W (lm)  L (lm)  #F (emitter)

Ballast (X)

A1, A2
C, D
B, E
H
F, G

2  20  4
2  10  4
2  20  4
2  20  4
2  20  8

0
5
5
7
10

1.6732
2.6313
4.1929
4.6326
9.4769

1.956
1.985
1.929
1.8827
1.911

A1 25 oC Average Fit
B 25 oC Average Fit
C 25 oC Average Fit
F 25 oC Average Fit
G 25 oC Average Fit

F, G

A2 25 oC Average Fit
D 25 oC Average Fit

E 25 oC Average Fit
B, E

H 25 oC Average Fit

C, D
A1, A2
SOA moves out
with increasing RB

Fig. 8. Measured SOA curves for different HBT geometries and ballast resistors.
With increasing ballast resistance, the SOA curves move up and to the right, for a
larger SOA.

Fig. 10. Comparison of SOA for a 2lm  20 lm  4 nger HBT with Rballast = 0 X vs.
that of a 2lm  20 lm single nger HBT with no Rballast. That the single nger SOA
is well outside that of the 4 nger SOA indicates how important current collapse
into a single nger is to dening SOA for multi-nger structures.

consistency with the measured room temperature SOA. The cooler

temperature increases the SOA slightly, and the high temperature
decreases the SOA slightly, but neither of these temperature variants was observed to have a very large effect on the resulting
SOA curve. This implies that factors which control SOA are dened
by the characteristics of the devices themselves. The temperature
of the environment where the device is placed will have essentially
no effect.
4. Discussion

Fig. 9. SOA comparison between HBT congurations with identical ballast resistor
values (5 X) and different emitter areas, showing large emitter areas have a large
SOA.

ballast resistor for the design of robust circuits. A second consequence of additional ngers is a geometry-induced reduction in
cooling manifested as an increase in the thermal resistivity, Rth,
as discussed in [1]. This effect becomes more signicant as the
ngers are packed closer together, leaving less area for cooling.
Data to date, however, suggests that for multi-emitter nger HBTs,
which are being treated here, the impact of both effects, increased
probability of current collapse and increased Rth, due to adding
additional ngers diminishes rapidly with the number of ngers.
Thus, by comparison with the overall size, the impact of the
number of ngers is secondary and is not treated here. It can be
the subject of a future study.
Ambient temperature variation was not observed to be a driver
in SOA performance, as is shown by the measured SOA data from
device conguration F (2  20  8, Rb = 10 X) in Fig. 11. The measured SOA curves for both a low ambient temperature, at 50 C,
and at high ambient temperature, at 125 C, show a strong

While the measured SOA curves are useful, the availability of a

much broader set of potential HBT geometries is desirable in order
to specically tailor MMIC performance to specications. However,

Fig. 11. Measured SOA as a function of ambient temperature, for device conguration F (W  L  ngers = 2 lm  20 lm  8, Rb= 10 X), demonstrating the
absence of a strong correlation between SOA and ambient temperature.

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R.S. Howell et al. / Microelectronics Reliability 54 (2014) 26822687

the testing and creation of SOA curves for various geometries is

time consuming and expensive, and so an empirically based
extrapolation of SOA curves is very desirable, in order to expand
the MMIC design exibility while ensuring that catastrophic MMIC
failures from biasing outside of the SOA region are avoided.
The starting point for the extrapolation is the observation that
(i) the SOA locus follows a curve of the form ICE,SOA = AVCEB, and
(ii) as is shown here and in [1], B  1.9 for this technology. Thus,
the problem reduces to determining the values for A. Furthermore,
the key elements of the device design are the area and the ballast
resistor. To accomplish the extrapolation, the experimental SOA
data presented in the previous section was mapped along axis of
constant emitter area with increasing ballast resistor size (comparing Device B [2  20  4, 5 X with Device H [2  20  4, 7 X]), and
constant ballast resistor size with increasing emitter area (comparing Device D, [2  10  4, 5 X] with Device B [2  20  4, 5 X]). A
linear extrapolation was constructed from each of these that calculates the effect of changing either emitter area or ballast resistor on
the corresponding value for A. These are shown in Figs. 12 and 13.
In order to extrapolate to a new device geometry, a baseline experimental SOA was chosen, and the extrapolation factors for A
applied to the area and ballast resistor in turn.
An example of the methodology is the following extrapolation
to a 2  20  8 Rb = 10 X HBT geometry from the data in Figs. 12
and 13. As a starting point, we choose the 2  20  4 Rb = 5 X
structure for which A has been measured as 4.1929. First, we
extrapolate Rb from 5 X to 10 X using the equation on Fig. 13,
A = 3.0937 + 0.21985 Rb, to obtain A = 5.2922 for 2  20  4
Rb = 10 X. Next, we use the equation in Fig. 12, from which it
follows that the change in A for a change in emitter area is given
by DA = 0.024504  DAreaemitter with the area given in lm2. With
5.2922 as starting point for A and an increase in emitter area from
160 lm2 to 320 lm2 A = 9.21284 is calculated. A device of this
geometry was packaged and tested as is described in Section 2.
The values for A and B from the resulting curve t were
A = 9.4769 and B = 1.911. In Fig. 14 the measured and extrapolated
SOA locus are graphed. The extrapolated values are within 3% of
the measured values.
The accuracy of extrapolations such as these is dependent on
the accuracy of the values measured and the proximity of the
new, extrapolated device geometry to one for which there is actual
measured data. A quantitative assessment of the range over which
the linear assumptions implicit in these extrapolations are

Fig. 13. Fitting parameter A as a function of ballast resistor size for a constant
emitter area value of 160 lm2.

Fig. 14. Comparison of measured SOA with extrapolated SOA for the same device
geometry and ballast resistor size. The close t indicates that this method can be
used successfully to predict SOA curves for other HBT geometries and ballast
resistor sizes.

Table 3
Extrapolated SOA parameters for other HBT geometries, based on the applying
sequentially extrapolations based on changing emitter area and ballast resistor size
with the other variable held constant.
Summary of extrapolated SOA results, ISOA = AVCEB
Emitter W (lm)  L (lm)  #F

Ballast (X)

2  20  8
2  20  8
2  (2  20  8)
2  20  16
2  20  10

10
0
10
14
45

9.2128
3.2377
18.954
18.22
21.288

1.9
1.9
1.9
1.9
1.9

accurate has not yet been performed. They are being used
cautiously in predicting SOA loci for new geometries for HBTG1
while additional data is gathered. Higher order dependencies
may be identied. Using this and similar methodologies, several
other HBT SOAs were generate which are shown in Table 3.
5. Summary

Fig. 12. Fitting parameter A as a function of emitter area for a constant ballast
resistor value of 5 X. A similar relationship could be derived from the data in [1] for
a 0 X ballast resistor.

We present the results of an HBT SOA analysis and the use of

this data for the successful extrapolation of the SOA to generalized
HBT geometries and ballast resistor sizes. This methodology has
been shown to be valid within the geometries close to the mea-

R.S. Howell et al. / Microelectronics Reliability 54 (2014) 26822687

sured device parameter space. Further work is required to determine its range of accurate application. However, by judicious
choice of device geometries and ballast resistors tested, a relatively
small number of tests can provide data for very large device
parameter space.
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