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Virtuoso Digital
Implementation
Designed to complement the Virtuoso
Layout Suite, Virtuoso Digital
Implementation enables capacitylimited1 execution of a complete digital
implementation solution from RTL-toGDSII. Targeting mixed-signal designs
that contain small digital blocks,
Virtuoso Digital Implementation
enables Cadence Encounter RTL
Compiler synthesis and Encounter
Digital Implementation System
functionality. Encounter RTL Compiler
provides a high-performance synthesis
solution to help you efficiently develop
smaller, faster, lower-power chips.
Encounter Digital Implementation
System uses extremely fast, integrated
engines to optimize digital block
implementation. Both technologies
are based on the industry-leading
Encounter digital IC design platform,
proven to deliver high quality of silicon
(Figure 1).
VIRTUOSO PLATFORM
Virtuoso Spec-Driven Environment
Virtuoso Spectre Circuit Simulator
Virtuoso UltraSim
Full-Chip Simulator
Virtuoso XL Layout Editor
ENCOUNTER PLATFORM
LEF/DEF
OpenAccess
Benefits
Enables automated digital
implementation for small digital
blocks, including synthesis and
physical implementation
Matches the functionality enabled
by Encounter Digital Implementation
System L
1 Virtuoso Digital Implementation enables an RTL-to-GDSII solution that is limited in capacity. Encounter
RTL Compiler is limited to a final mapped instance count of 50k instances or 200k generic instances.
Encounter Digital Implementation System is limited to a capacity of 50k instances. Two Virtuoso Digital
Implementation licenses can be combined (stacked) to double the capacity limits. For users who require
larger or unlimited capacity, other Encounter products are available.
Features
Rtl synthesis
Read/write standard inputs/outputs
Built-in high-performance data path
Arithmetic optimizations
Total negative slack (TNS) optimization
Testability analysis and scan insertion
Clock gating
Multi-Vt leakage power optimization
Routing
Ease-of-use
Easy-to-use, built-in signal and power
wire editing functionality
Tcl programming interface throughout
the flow
Intuitive and helpful commands
Familiar use model
Easy-to-learn system enables ramp up
within a week
Helpful reports for all steps
Industry-proven routers
Support for advanced engineering
change order (ECO) routing
Specifications
Input
Mixed-language/mixed-level netlist:
gate-level netlist in Verilog, gate-level
EDIF netlist
www.cadence.com
Output
Platforms
Linux (32- and 64-bit)
Solaris (64-bit)
SOLX86 (64-bit)
IBM AIX (64-bit)
Cadence is transforming the global electronics industry through a vision called EDA360.
With an application-driven approach to design, our software, hardware, IP, and services help
customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com
2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Encounter, First Encounter, and Virtuoso are registered
trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders.
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