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Half adder :
Block Diagram:
a

HALF

ADDER

sum
carry

Truth table:
a

sum carry

0 0

1 0

1 0

0 1

Circuit diagram :

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Date: 18-12-13

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1. HALF ADDER AND FULL ADDER

AIM:
To design and simulate Half and Full adder using three different
architectures namely
i.
ii.
iii.

Dataflow
Behavioral
Structural

SOFTWARE USED:
1.Xilinx ISE 9.2i
2.Model SIM SE6.5
THEORY:
HALF ADDER:
A combinational circuit that performs the addition of 2 bits is called a half
adder. This circuit accepts two binary inputs and produces two binary outputs.
The input variables designate augends and addend bits; the output variables
designate sum and carry.
sum= ab.
carry = ab.
FULLADDER:
A combinational circuit that performs the addition of 3 bits is called a full
adder. This circuit accepts 3 binary inputs and produces two binary outputs. The
two outputs are denoted by sum and carry.
sum= ab c
carry = ab + bc+ca

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FULL ADDER :
Block Diagram:
a

sum

FULL

b
c

carry

ADDER

Truth table:
a

sum

carry

Logic circuit:

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Procedure:

Create a new project by using file-new project.

Name the new project and choose VHDL module.
Choose the architecture and give the entity details.
A sample module is generated .Additional required library files are
included.
Architecture is automatically generated.
Now the coding is done under the architecture part and at last give end
architecture name.
The syntax is checked.
Once the syntax is correct simulation is done.
Graph is plotted for various combination of input values.

Source code :( HALF ADDER)

Data Flow Model :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Half_Adder is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end Half_Adder;
architecture Half_Adder_arc of Half_Adder is
begin
sum <= a xor b;
carry <= a and b;
end Half_Adder_arc;
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Behavioral Model:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha behavioral is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end ha behavioral;
architecture Behavioral of ha behavioral is
begin
process (a,b)
begin
if a='0' and b='0' then
sum<='0';carry<='0';
elsif a='0' and b='1' then
sum<='1';carry<='0';
elsif a='1' and b='0' then
sum<='1';carry<='0';
elsif a='1' and b='1' then
sum<='0';carry<='1';
end if;
end process;
end Behavioral;

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Structural Model :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha structural is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end ha structural;
architecture structure of ha structural is
component xor1 is
port(l, m: in std_logic;n:outstd_logic);
end component;
component and1 is
port(x, y: in std_logic;z:outstd_logic);
end component;
begin
x1:xor1 port map(a, b, sum);
x2:and1 port map(a, b, carry);
end structural;

Subroutine Program :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

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entity xor1 is
Port ( x1 : in STD_LOGIC;
y1 : in STD_LOGIC;
w1 : out STD_LOGIC);
end xor1;
architecture dataflow of xor1 is
begin
w1<=x1 xor y1;
end dataflow;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and1 is
Port ( x2 : in STD_LOGIC;
y2 : in STD_LOGIC;
w2 : out STD_LOGIC);
end and1;
architecture dataflow of and1 is
begin
w2<=(x2 and y2);
end dataflow;

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Source code :(FULL ADDER)

Data flow :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Full_Adder_Design is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end Full_Adder_Design;
architecture Full_Adder_Design_arc of Full_Adder_Design is
begin
sum <= a xor b xor c;
carry <= (a and b) or
(b and c) or
(c and a);
end Full_Adder_Design_arc;

Behavioral Model:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fa is
Port ( a ,b,c : in STD_LOGIC;
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sum : out STD_LOGIC;

carry : out STD_LOGIC);
end fa;
architecture behavioral of fa is
begin
process (a,b,c)
begin
if a='0' and b='0' and c='0' then
sum<='0' ; carry<='0';
elsif a='0' and b='0' and c='1' then
sum<='1' ; carry<='0';
elsif a='0' and b='1' and c='0' then
sum<='1' ; carry<='0';
elsif a='0' and b='1' and c='1' then
sum<='0' ; carry<='1';
elsif a='1' and b='0' and c='0' then
sum<='1' ; carry<='0';
elsif a='1' and b='0' and c='1' then
sum<='0';carry<='1';
elsif a='1' and b='1' and c='0' then
sum<='0';carry<='0';
elsif a='1' and b='1' and c='1' then
sum<='1';carry<='1';
end if;

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end process;
end behavioral;

Structural Model :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fa;
architecture structural of fa is
component xor1 is
port(x1,y1,z1:in std_logic;
w1:out std_logic);
end component;
component and1 is
port(x2,y2:in std_logic; w2:out std_logic);
end component;
component or1 is
port(x3,y3,z3:in std_logic; w3:out std_logic);
end component;

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signalx,y,z:std_logic;
begin
x1:xor1 port map(a,b,c,sum);
x2:and1 port map(a,b,x);
x3:and1 port map(b,c,y);
x4:and1 port map(c,a,z);
x5:or1 port map(x,y,z,carry);
end structural;
Subroutine Program :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor1 is
Port ( x1 : in STD_LOGIC;
y1 : in STD_LOGIC;
z1:instd_logic;
w1 : out STD_LOGIC);
end xor1;
architecture dataflow of xor1 is
begin
w1<=x1 xor y1 xor z1;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and1 is

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Port ( x2 : in STD_LOGIC;
y2 : in STD_LOGIC;
w2 : out STD_LOGIC);
end and1;
architecture dataflow of and1 is
begin
w2<=(x2 and y2);
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or1 is
Port ( x3 : in STD_LOGIC;
y3 : in STD_LOGIC;
z3 : in STD_LOGIC;
w3 : out STD_LOGIC);
end or1;
architecture dataflow of or1 is
begin
w3<=x3 or y3 or z3;
end dataflow;

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Output Wave form of Full Adder :

Output Waveform of Half Adder :

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Result:
The design and simulation of the half adder and full adder using dataflow,
behavioral, structural modeling has been performed using VHDL codeand
software mentioned.
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4*1 Multiplexer :
Block diagram :

Function Table :

F=a s0s1+b s0s1+c s0s1+d s0s1

Logic Diagram :

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Ex No:2
Date : 8-1-14

2. MULTIPLEXER AND DEMULTIPLEXER

AIM:
To design and simulate Multiplexer and Demultiplexer using three
different architectures namely
i.
ii.
iii.

Dataflow
Behavioral
Structural

SOFTWARE USED:
ISE Design Suite 14.2.
THEORY:
MULTIPLEXER:
It is combinational circuit that selects binary information from one of the many
inputs and directs it to a single output. The selection lines or controlled lines. It
is used as a data selector and parallel to serial convertor. In reference to the
block diagram a two bit binary code on the data select input will also allow the
data on the corresponding data input to pass through the data output.
OUTPUT :(F)=a s0s1+b s0s1+c s0s1+d s0s1

DEMULTIPLEXER:
This is a circuit that receives data from one line and transmits this information
on one of the 2n possible output lines. It performs reverse operation of
multiplexer. The data input line goes to all of and gate. The two select lines
enable only one gate at a time and the data appearing on the input will pass
through the selected gate.
OUTPUT: Y0=DS0S1; Y1=DS0S1 ;Y2=DS0S1 ; Y3= DS0S1;
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1*4 Demultiplexer :
Block diagram :

Truth Table :

Y0=DS0S1; Y1=DS0S1 ;Y2=DS0S1 ; Y3= DS0S1;

Logic Diagram :

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Procedure :

Create a new project by using file-new project.

Name the new project and choose VHDL module.
Choose the architecture and give the entity details.
A sample module is generated .Additional required library files are
included.
Architecture is automatically generated.
Now the coding is done under the architecture part and at last give end
architecture name.
The syntax is checked.
Once the syntax is correct simulation is done.
Graph is plotted for various combination of input values.

Source code : (Multiplexer)

Data flow model :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end mux;
architecture dataflow of mux is

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begin
y<=((a and (not s0) and (not s1)) or
(b and (not s0) and s1) or
(c and s0 and (not s1)) or
(d and s0 and s1));
end dataflow;

Behavioral Model:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s : in STD_LOGIC_VECTOR(0 to 1);
y : out STD_LOGIC);
end mux;
architecture behavioral of mux is
begin
process(a,b,c,d,s)
begin
case s is
when "00" => y<=a;

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when "01" => y<=b;

when "10"=> y<=c;
when others => y<=d;
end case;
end process;
end behavioral;

Structural Modeling :
library IEEE;
use IEEE.std_logic_1164.all;
entity Structural_4x1 is
port(s1,s2,d00,d01,d10,d11 : in std_logic;
z_out : out std_logic);
end Structural_4x1;
architecture arc of Structural_4x1 is
component mux
port(sx1,sx2,d0,d1 : in std_logic;
z : out std_logic);
end component;
component or_2
port(a,b : in std_logic;
c : out std_logic);
end component;
signal intr1, intr2, intr3, intr4 : std_logic;
begin
mux1 : mux port map(s1,s2,d00,d01,intr1);
mux2 : mux port map(not s1,s2, d10,d11,intr2);
o1 : or_2 port map(intr1, intr2, z_out);
end arc;
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Subroutine Program for 4*1 Multiplexer:

library ieee;
use ieee.std_logic_1164.all;
entity mux is
port(sx1,sx2,d0,d1 :in std_logic;
z1,z2: inout std_logic;
z: out std_logic);
end mux;
architecture arc of mux is
begin
z1 <= d0 and (not sx1) and (not sx2);
z2 <= (d1 and (not sx1) and sx2);
z<= z1 or z2;
end arc;
entity or_2 is
port(a,b : in bit;
c : out bit);
end or_2;
architecture arc of or_2 is
begin
c<=a or b;
end arc;
1*4 Demultiplexer :
SourceCode :
Data flow Model :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dmux is
Port ( a : in STD_LOGIC;

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s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (0 TO 3));
end data;
architecture dataflow of dmux is
begin
y(0)<= a and (not s0) and (not s1);
y(1)<= a and (not s0) and (s1);
y(2)<= a and (s0) and (not s1);
y(3)<= a and (s0) and (s1);
end dataflow;

Behavioral Model :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dmux is
Port ( s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
a : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (0 to 3));
end dmux;
architecture Behavioral of dmux is
begin
process(a,s0,s1)

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begin
if a='1' and s0='0' and s1='0' then
y(0)<='1';y(1)<='0';y(2)<='0';y(3)<='0';
elsif a='1' and s0='0' and s1='1' then
y(0)<='0';y(1)<='1';y(2)<='0';y(3)<='0';
elsif a='1' and s0='1' and s1='0' then
y(0)<='0';y(1)<='0';y(2)<='1';y(3)<='0';
elsif a='1' and s0='1' and s1='1' then
y(0)<='0';y(1)<='0';y(2)<='0';y(3)<='1';
end if;
end process;
end Behavioral;

Structural Modeling:
library IEEE;
use IEEE.std_logic_1164.all;
entity Structural_1x4 is
port(s1,s2,data_in : in std_logic;
d1,d2,d3,d4 : out std_logic);
end Structural_1x4;
architecture arc of Structural_1x4 is
component dmux
port(sx1,sx2,d : in std_logic;
z1,z2 : out std_logic);
end component;
begin

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dmux1 : dmux port map(s1,s2,data_in,d1,d2);

dmux2 : dmux port map(not s1,s2,data_in,d3,d4);
end arc;
Subroutine Program for 1*4 Demultiplexer:
library ieee;
use ieee.std_logic_1164.all;
entity dmux is
port(sx1,sx2,d :in std_logic;
z1,z2: out std_logic);
end dmux;
architecture arc of dmux is
begin
z1 <= d and (not sx1) and (not sx2);
z2 <= d and (not sx1) and sx2;
end arc;

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Output Waveform of 4*1 Multiplexer :

Output Waveform of 1*4 Demultiplexer :

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Result:
The design and simulation of the multiplexer and demultiplexer using
dataflow, behavioral modeling and Structural modeling has been
performed using VHDL code and software mentioned.
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Ex No: 3
Date :22-1-14

3. 3x8 Decoder and 2 Bit Magnitude Comparator

AIM:
To design and simulate 3x8 Decoder and 2 Bit Magnitude Comparator
using three different architectures namely
i.
ii.
iii.

Dataflow
Behavioral
Structural

SOFTWARE USED:
1.Xilinx ISE 9.2i
2.Model SIM SE6.5
THEORY :
3x8 DECODER
A decoder is a device which does the reverse operation of an encoder, undoing
the encoding so that the original information can be retrieved. The same method
used to encode is usually just reversed in order to decode. It is a combinational
circuit that converts binary information from n input lines to a maximum of 2n
unique output lines.
A 3 to 8 decoder consists of three inputs and eight outputs.
Application :
A simple CPU with 8 registers may use 3-to-8 logic decoders inside the
instruction decoder to select two source registers of the register file to feed into
the ALU as well as the destination register to accept the output of the ALU. A
typical CPU instruction decoder also includes several other things.

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3X8 DECODER
Block Diagram :

Truth Table :
X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

F0
1
0
0
0
0
0
0
0

F1
0
1
0
0
0
0
0
0

F2
0
0
1
0
0
0
0
0

F3
0
0
0
1
0
0
0
0

F4
0
0
0
0
1
0
0
0

F5
0
0
0
0
0
1
0
0

F6
0
0
0
0
0
0
1
0

F7
0
0
0
0
0
0
0
1

F0=XYZ;

F6=XYZ;

F1=XYZ;

F7=XYZ;

F2=XYZ;
F3=XYZ;
F4=XYZ;
F5=XYZ;

Logic Circuit Diagram :

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2Bit Magnitude Comparator :

Magnitude comparator is a combinational circuit that compares two numbers
and determines their relative magnitude.
For a 2-bit comparator we have four inputs A1A0 and B1B0 and three outputs:
E (is 1 if two numbers are equal)
G (is 1 when A > B) and
L (is 1 when A < B)
Output Expressions :
f(A>B) = A1B1+ (A1 + B1) A0B0 = A1B1+ A0 B1B0+ A1A0B0
f(A=B)=A1A0B1B0+A1A0B1B0+A1A0B1B0+ A1A0B1B0
= (A1B1+A1B1)(A0B0+A0B0)
f(A<B)=A1B1+A0B0A1B1+A0B0A1B1
= A1B1+A0B0(A1B1+A1B1)

Procedure:

Create a new project by using file-new project.

Name the new project and choose VHDL module.
Choose the architecture and give the entity details.
A sample module is generated .Additional required library files are
included.
Architecture is automatically generated.
Now the coding is done under the architecture part and at last give end
architecture name.
The syntax is checked.
Once the syntax is correct simulation is done.
Graph is plotted for various combination of input values.

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2 BIT MAGNITUDE COMPARATOR

Block Diagram :

Truth Table :

Logic Circuit Diagram :

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Source Code:(3x8 Decoder:)

Data Flow Model:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoderdataflow is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d0 : out STD_LOGIC;
d1 : out STD_LOGIC;
d2 : out STD_LOGIC;
d3 : out STD_LOGIC;
d4 : out STD_LOGIC;
d5 : out STD_LOGIC;
d6 : out STD_LOGIC;
d7 : out STD_LOGIC);
end Decoderdataflow;
architecture Dataflow ofDecoderdataflow is
begin
d0<= (not a) and (not b) and (not c);
d1<= (not a) and (not b) and c;
d2<= (not a) and b and (not c);
d3<= (not a) and b and c;
d4<= a and (not b) and (not c);
d5<= a and (not b) and c;
d6<= a and b and (not c);
d7<= a and b and c;
end Dataflow;
Behavioral Modeling :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder is
Port ( din : in STD_LOGIC_VECTOR (2 downto 0);
dout : out STD_LOGIC_VECTOR (7 downto 0));
end Decoder;
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architecture Behavioral of Decoder is

begin
process(din)
begin
if (din="000") then
dout <= "10000000";
elsif (din="001") then
dout <= "01000000";
elsif (din="010") then
dout <= "00100000";
elsif (din="011") then
dout <= "00010000";
elsif (din="100") then
dout <= "00001000";
elsif (din="101") then
dout <= "00000100";
elsif (din="110") then
dout <= "00000010";
else dout <= "00000001";
end if;
end process;
end Behavioral;
Structural Modeling :
library ieee;
use ieee.std_logic_1164.all;
entity dec3x8 is
port(a,b,c,e:inbit; z0,z1,z2,z3,z4,z5,z6,z7:out bit);
end dec3x8;
architecture structural of dec3x8 is
component and4 is
port(g,h,i,j:inbit;k:out bit);
end component;

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component not1 is
port(a:in bit; b:out bit);
end component;
signal s1,s2,s3:bit;
begin
x1:not1 port map(a,s1);
x2:not1 port map(b,s2);
x3:not1 port map(c,s3);
x4:and4 port map(s1,s2,s3,e,z0);
x5:and4 port map(s1,s2,c,e,z1);
x6:and4 port map(s1,b,s3,e,z2);
x7:and4 port map(s1,b,c,e,z3);
x8:and4 port map(a,s2,s3,e,z4);
x9:and4 port map(a,s2,c,e,z5);
x10:and4 port map(a,b,s3,e,z6);
x11:and4 port map(a,b,c,e,z7);
end structural;
SubProgram for not1 :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity not1 is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end not1;
architecture Structural of not1 is
begin
b<=not a;
end Structural;

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SubProgram for and4 :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and4 is
Port ( g : in STD_LOGIC;
h : in STD_LOGIC;
i : in STD_LOGIC;
j : in STD_LOGIC;
k : out STD_LOGIC);
end and4;
architecture Structural of and4 is
begin
k<=g and h and i and j;
end Structural;
Source Code :(2 Bit Magnitude Comparator)
Data Flow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity comparator_2bit is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : in STD_LOGIC_VECTOR(1 downto 0);
equal : out STD_LOGIC;
greater : out STD_LOGIC;
lower : out STD_LOGIC
);

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end comparator_2bit;
architecture Dataflow of comparator_2bit is
begin
equal <= '1' when (a=b) else '0';
greater <= '1' when (a<b) else '0';
lower <= '1' when (a>b) else '0';
end Dataflow;

Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparator_2bit is
Port ( a : in STD_LOGIC_VECTOR:="00";
b : in STD_LOGIC_VECTOR:="00";
equal : out STD_LOGIC;
greater : out STD_LOGIC;
lesser : out STD_LOGIC);
end comparator_2bit;

architecture Behavioral of comparator_2bit is

begin
process(a,b)
begin
if (a=b)then

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equal<='1';
greater<='0';
lesser<='0';

elsif(a>b)then
equal<='0';
greater<='1';
lesser<='0';

elsif(a<b)then
equal<='0';
greater<='0';
lesser<='1';
end if;
end process;
end Behavioral;

Structural Modeling :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparator2bit is
Port ( a1 : in STD_LOGIC;
a0 : in STD_LOGIC;

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b1 : in STD_LOGIC;
b0 : in STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC);
end comparator2bit;

architecture Structural of comparator2bit is

component and1 is
port(c,d:in std_logic;
e:out std_logic);
end component;
component and6 is
port(f,g,h:in std_logic;
i:out std_logic);
end component;
component or1 is
port(j,k,l:in std_logic;
m:out std_logic);
end component;
component xnor1 is
port(n,o:in std_logic;
p:out std_logic);
end component;

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component not1 is
port(q:in std_logic;
r:out std_logic);
end component;

signal s,t,u,s1,t1,u1,s2,t2,s3,t3,u3,v3:std_logic;
begin
TT1:not1 port map (a1,s3);
TT2:not1 port map (a0,t3);
TT3:not1 port map (b1,u3);
T4:not1 port map (b0,v3);
T5:and1 port map (a1,u3,s);
T6:and6 port map (a0,u3,v3,t);
T7:and6 port map (a0,a1,v3,u);
T8:or1 port map (s,t,u,x);
T9:and1 port map (s3,b1,s1);
T10:and6 port map (b0,s3,t3,t1);
T11:and6 port map (b0,b1,t3,u1);
T12:or1 port map (s1,t1,u1,y);
T13:xnor1 port map (a1,b1,s2);
T14:xnor1 port map (a0,b0,t2);
T15:and1 port map (s2,t2,z);
end Structural;

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Subprogram for not1:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity not1 is
Port ( q : in STD_LOGIC;
r : out STD_LOGIC);
end not1;
architecture Structural of not1 is
begin
r<=not q;
end Structural;
Subprogram for and1:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and1 is
Port ( c : in STD_LOGIC;
d : in STD_LOGIC;
e : out STD_LOGIC);
end and1;
architecture Structural of and1 is
begin
e<=c and d;
end Structural;
Subprogram for and6:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and6 is
Port ( f : in STD_LOGIC;
g : in STD_LOGIC;
h : in STD_LOGIC;
i : out STD_LOGIC);
end and6;
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architecture Structural of and6 is

begin
i<=f and g and h;
end Structural;
Subprogram for or1:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or1 is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
l : in STD_LOGIC;
m : out STD_LOGIC);
end or1;
architecture Structural of or1 is
begin
m<=j or k or l;
end Structural;
Subprogram for xnor1 :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xnor1 is
Port ( n : in STD_LOGIC;
o : in STD_LOGIC;
p : out STD_LOGIC);
end xnor1;
architecture Structural of xnor1 is
begin
p<=n xnor o;
end Structural;

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2BIT Magnitude Comparator :

Output:

3x8Decoder:
OUTPUT:

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Result:
The design and simulation of the 3x8 Decoder and 2Bit Magnitude Comparator
using dataflow,behavioral,structural modeling has been performed using VHDL
code and software mentioned.
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Ex No: 4
Date: 29-1-14

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4. ARITHMETIC AND LOGIC UNIT

AIM:
To design and simulate Arithmetic and Logic Unit using architecture
namely
i.

Behavioral Modeling

SOFTWARE USED:
1.Xilinx ISE 14.7
2.ISIM Simulator
THEORY :
An arithmetic
and
logic
unit (ALU)
is
a digital
circuit that
performs integer arithmetic and logical operations. The ALU is a fundamental
building block of the central processing unitof a computer, and even the
simplest microprocessors contain one for purposes such as maintaining timers.
The processors found inside modern CPUs and graphics processing units
(GPUs) accommodate very powerful and very complex ALUs; a single
component may contain a number of ALUs.
Procedure:

Create a new project by using file-new project.

Name the new project and choose VHDL module.
Choose the architecture and give the entity details.
A sample module is generated .Additional required library files are
included.
Architecture is automatically generated.
Now the coding is done under the architecture part and at last give end
architecture name.
The syntax is checked.
Once the syntax is correct simulation is done.
Graph is plotted for various combination of input values.
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ARITHMETIC AND LOGIC UNIT

Block Diagram :

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SOURCE CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity aluarith is
Port ( a,b : in INTEGER;
x,y : in STD_LOGIC_VECTOR(7 DOWNTO 0);
x1 : in BIT_VECTOR(7 DOWNTO 0);
asel : in STD_LOGIC_VECTOR(1 DOWNTO 0);
lsel : in STD_LOGIC_VECTOR(2 DOWNTO 0);
l1sel : in STD_LOGIC_VECTOR(2 DOWNTO 0);
aout : out INTEGER;
lout : out STD_LOGIC_VECTOR(7 DOWNTO 0);
l1out : out BIT_VECTOR(7 DOWNTO 0));
end aluarith;

architecture Behavioral of aluarith is

begin
process(a,b,asel)
begin
case asel is
when "00"=> aout<= a+b;

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when "01"=> aout<= a-b;

when "10"=> aout<= a*b;
when "11"=> aout<= a/b;
when others=>aout<= a-b;
end case;
end process;

process(x,y,lsel)
begin
case lsel is
when "000"=> lout <= "00000000";
when "001"=> lout <= x or y ;
when "010"=> lout <= x nor y;
when "011"=> lout <= x xor y;
when "100"=> lout <= x xnor y;
when "101"=> lout <= x nand y;
when "110"=> lout <= x and y;
when "111"=> lout <= not y;
when others=>lout<="--------";
end case;
end process;

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process(x1,l1sel)
begin
case l1sel is
when "000"=> l1out <= "00000000";
when "001"=> l1out <= x1 SLA 2;
when "010"=> l1out <= x1 SRA 2;
when "011"=> l1out <= x1 SLL 2;
when "100"=> l1out <= x1 SRL 2;
when "101"=> l1out <= x1 ROL 2;
when "110"=> l1out <= x1 ROR 2;
when "111"=> l1out <= "00000000";
when others=>l1out<="00000000";
end case;
end process;
end Behavioral;

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OUTPUT WAVEFORM
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Result:
The design and simulation of the Arithmetic and logic unit (ALU) using
behavioral modeling has been performed using VHDL codeand simulated
through software mentioned.
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Ex No: 5
Date: 5-2-14

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5.DESIGN AND SIMULATION OF T-FLIPFLOP

AIM:
To design and simulate T-FlipFlop using architectures namely
i.
ii.
iii.

Dataflow Modeling.
Behavioral Modeling.
Structural Modeling.

SOFTWARE USED:
1.Xilinx ISE 14.7
2.ISIM Simulator.
Theory:
T Flip-Flop:
The T FF is a single input version of the JK FF, where both J and J inputs
are tied together. This FF has the ability to toggle regardless of its present state
when the clock pulse occurs and while the T input is 1.
Characteristic Equation: Qt+1=Qt xor t
Procedure:

Create a new project by using file-new project.

Name the new project and choose VHDL module.
Choose the architecture and give the entity details.
A sample module is generated .Additional required library files are
included.
Architecture is automatically generated.
Now the coding is done under the architecture part and at last give end
architecture name.
The syntax is checked.
Once the syntax is correct simulation is done.
Graph is plotted for various combination of input values.
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T-FLIPFLOP:
Block Diagram:

Characteristic Table :
Q

Q(t+1)

Qt+1=Qt xor t

Circuit Diagram :

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Source code :
Dataflow Modeling
library IEEE;
Use IEEE.STD_LOGIC_1164.All;

entity tff is
Port (t : in std_logic;
clk : in std_logic;
q : in out std_logic;
qbar : in out std_logic);
end tff;

architecture dataflow of tff is

signal s1,s2:std_ logic;
begin
s1<=t and clk and q;
s2<=t and clk and qbar;
q<=s1 nor qbar;
qbar<=s2 nor q;
end dataflow;

Behavioral Modeling :
library IEEE;
Use IEEE.STD_LOGIC_1164.All;

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entity tff is
Port (t : in std_logic;
clk : in std_logic;
q : in out std_logic;
qbar : in out std_logic);
end tff;

architecture Behavioral of tff is

begin
Process (t,clk,)
begin
if (clkevent and clk =1)then
if(t=0)then
q<=q;
qbar<=qbar;
else
q<=not q ;
qbar<=not qbar;
end if;
else
q<=q;
qbar<=qbar;
end if;
end process;
end Behavioral;

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Structural Modeling :
library IEEE;
Use IEEE.STD_LOGIC_1164.All;

entity tff is
Port (t : in std_logic;
clk : in std_logic;
q : in out std_logic;
qbar : in out std_logic);
end tff;

architecture structural of tff is

signal s1,s2 : std_ logic;
component nor2 is
port (a,b: in std_logic;
c : out std_logic);
end component;

component and3 is
port (a,b,c: in std_logic;
d : out std_logic);
end component;
begin
x1: and3 port map(t,clk,q,s1);

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x2: and3 port map(t,clk,qbar,s2);

x3: nor2 port map(s1,qbar,q);
x4: nor2 port map(s2,q,qbar);
end structural;

Subprogram for nor2 :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nor2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nor2;
architecture data_flow of nor2 is
begin
c<=a nor b;
end data_flow;

Subprogram for and3 :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and3 is
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Port ( a: in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : out STD_LOGIC);
end and3;
architecture Dataflow of and3 is
begin
d<=a and b and c;
end Dataflow;

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OUTPUT WAVEFORM :

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Result:
The design and simulation of the T-flipflop using dataflow,behavioral,
structural modeling has been performed using VHDL codeand software
mentioned.
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Ex No: 6
Date: 19-2-14

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6.DESIGN AND SIMULATION OF COUNTERS

AIM:
To design and simulate counters [updown,ring & mod10] using behavioral
modeling in VHDL code.
SOFTWARE USED:
Xilinx ISE 14.7
THEORY:
UPDOWN COUNTER
A counter that can change state in either direction, under the control of an up or
down selector input, is known as an up/down counter. When the selector is in
the up state, the counter increments its value. When the selector is in the down
state, the counter decrements the count.

RING COUNTER
A ring counter is a circular shift register which is initiated such that only one of
its flip-flops is the state one while others are in their zero states.
A ring counter is a Shift Register (a cascade connection of flip-flops) with the
output of the last one connected to the input of the first, that is, in a ring.
Typically, a pattern consisting of a single bit is circulated so the state repeats
every n clock cycles if n flip-flops are used. It can be used as a cycle counter of
n states.

MOD10 COUNTER
A MOD 10 counter has 10 possible states. In other words, it counts from 0 to 9
and rolls over. The decade counter is also known as a mod-counter when it
counts to ten (0, 1, 2, 3, 4, 5, 6, 7, 8, 9). A Mod Counter that counts to 64 stops
at 63 because 0 counts as a valid digit.

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UP-DOWN COUNTER:

TRUTH TABLE:
Present State

State When Count = 1

State When Count = 0

0000

0001

1111

0001

0010

0000

0010

0011

0001

0011

0100

0010

0100

0101

0011

0101

0110

0100

0110

0111

0101

0111

1000

0110

1000

1001

0111

1001

1010

1000

1010

1011

1001

1011

1100

1010

1100

1101

1011

1101

1110

1100

1110

1111

1101

1111

0000

1110
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PROCEDURE :
Open a new project from Xilinx ISE9.2i,a project navigation software
tool.
Select a source file name as VHDL module and define VHDL sources
respectively, the input and output ports.
Enter the program and save the file.
Check the syntax option from synthesis to know the error.
Go for the synthesis XST to view RTL schematic report (new list).
Launch Modelsim simulator from design entry utilities and enter the
value of input ports.

SOURCE CODES :
UP DOWN COUNTER(Behavioral)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity updowncounter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
count : in STD_LOGIC;
s : inout STD_LOGIC_VECTOR (3 downto 0));
end updowncounter;

architecture Behavioral of updowncounter is

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RING COUNTER :
Block Diagram :

Truth Table :
Reset

Present State

000

0
0

001

011

0
0
0
0

Next State
00000001
00000010
00000100

010

00001000
00010000

100

00100000

101

01000000

110

10000000

111

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begin
process(clk,reset,count)
begin
if reset='1' then s<="0000";
elsif count='1' and rising_edge(clk) then s<=s+1;
elsif count='0' and rising_edge(clk) then s<=s-1;
end if;
end process;
end Behavioral;

RING COUNTER(Behavioral)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ring_ctr is
Port ( clk,reset : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (0 to 1);
s : out STD_LOGIC_VECTOR (0 to 3));
end ring_ctr;

architecture Behavioral of ring_ctr is

begin

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MOD 10 COUNTER:
Block Diagram :

Truth Table :
Reset

Present State

Next State

0000

0001

0
0

0001

0010

0010

0011

0011

0100

0100

0101

0101

0110

0110

0111

0111

1000

1000

1001

1001

1010

1010

0000

0
0
0
0
0
0
0

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process(clk,reset,q)
begin
if reset='1' then q<="00";
elsif rising_edge(clk) then q<=q+1;
end if;
case q is
when "00"=>s<="0001";
when "01"=>s<="0010";
when "10"=>s<="0100";
when others=>s<="1000";
end case;
end process;
end Behavioral;

MOD-10 COUNTER(Behavioral)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mod_ctr is
Port ( clk,reset: in STD_LOGIC;
q : inout STD_LOGIC_VECTOR(3 downto 0));
end mod_ctr;

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architecture Behavioral of mod_ctr is

begin
process(clk,reset)
begin
if reset='1' then q<="0000";
elsif rising_edge(clk) then q<=q+1;
if q="1001" then q<="0000";
end if;
end if;
end process;
end Behavioral;

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OUTPUT WAVEFORMS:
UP-DOWN COUNTER

RING COUNTER :

MODULO-10 COUNTER :

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RESULT :
Thus the design and simulation of all the counters using behavioral modeling
are done and the outputs are verified.
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Ex No: 7
Date: 5-3-14

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7.DESIGN AND SIMULATION OF STATIC RAM

AIM :
To design and simulate a static random access memory using behavioral
modeling in VHDL.
SOFTWARE USED:
Xilinx ISE 14.7i
THEORY:
Static random-access memory (SRAM) is a type of semiconductor memory that
uses bistable latching circuitry to store each bit. The term static differentiates it
from dynamic RAM (DRAM) which must be periodically refreshed. SRAM
exhibits data remanence, but it is still volatile in the conventional sense that data
is eventually lost when the memory is not powered.
Procedure :
Open XilinxISE projectnavigatorwindow.
Close allprojects whichareopen.
Create anew project.
Select a project title and check next.
Select newsource and VHDLmodule.
Select sourcename andclick next till finish.
Writethe program with the correspondingmodellingtechnique.
Check the syntaxand correct theerrors.
Simulateitand forceinput values.
Observethewaveforms

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SRAM :
Logic Diagram :

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SOURCE CODE:
SRAM(Behavioral modeling)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity sram is
generic(width: integer :=4;
depth:integer:=4;
addr:integer:=2);
Port ( clk : in STD_LOGIC;
en : in STD_LOGIC;
rd : in STD_LOGIC;
wr : in STD_LOGIC;
rdaddr : in STD_LOGIC_VECTOR (addr-1 downto 0);
wraadr : in STD_LOGIC_VECTOR (addr-1 downto 0);
datain : in STD_LOGIC_VECTOR (width-1 downto 0);
dataout : out STD_LOGIC_VECTOR (width-1 downto 0));
end sram;

architecture Behavioral of sram is

type rmtyp is array (0 to depth-1) of std_logic_vector(width-1 downto 0) ;
signal tmpram:rmtyp;

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begin
process(clk,rd)
begin
if(clk' event and clk='1') then
if en='1' then
if rd='1' then
dataout<=tmpram(conv_integer(rdaddr));
else
dataout<=(dataout' range =>'Z');
end if;
end if;
end if;
end process;
process(clk,wr)
begin
if(clk' event and clk='1') then
if en='1' then
if wr='1' then
tmpram(conv_integer(wraadr))<=datain;
end if;
end if;
end if;
end process;
end Behavioral;

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OUTPUT WAVEFORM :

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Result:
Thus the static random access memory was successfullydesigned,
simulated and the output was verified .
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CIRCUIT DIAGRAM OF CMOS INVERTER:

CODING:(CMOS INVERTER)

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Ex No: 8
Date: 05-3-14

Dept. of ece

8.DESIGN AND SIMULATION OF CMOS LOGIC GATES

AIM:
To design and simulate CMOS inverter, CMOS NAND and CMOS NOR gate
using TANNER EDA.
SOFTWARE USED:
Tanner EDA 7.0
THEORY:
Cmos inverter:
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain
and gate terminals, a supply voltage VDD at the PMOS source terminal, and a
ground connected at the NMOS source terminal, where VIN is connected to the
gate terminals and VOUT is connected to the drain terminals. It is important to
notice that the CMOS does not contain any resistors, which makes it more power
efficient that a regular resistor-MOSFET inverter.As the voltage at the input of the
CMOS device varies between 0 and 5 volts, the state of the NMOS and PMOS
varies accordingly. If we model each transistor as a simple switch activated by
VIN, the inverters operations can be seen very easily.

Cmos NAND logic:

Cmos NAND logic consists of 2 n-MOS in parallel .Transistor sizing is done
according to the RC modelling to minimise the delay.If both inputs are high
then n-MOS transistors will conduct but p-MOS transistors will not.A
conductive path is established between the output and GND,making the output
low,if any of the input is low,one of the n-MOS will not conduct and p-MOS
will and output is pulled to Vdd.
Cmos NOR logic:
CMOS NOR logic consists of two n-MOS transistors in parallel and two
p-MOS transistors in series.If both the inputs are high then n-MOS transistors
will conduct, a conductive path is established between the output and GND,
and output is pulled down to GND. If any of the inputs are low, output is low.If

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CIRCUIT DIAGRAM FOR CMOS NAND GATE:

CODING:

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any of the inputs are low, output is low.If both inputs are low then output is
high.

PROCEDURE:
1. Open the schematic editor(S-edit) from the tanner EDA tool.
2. Get the required components from the symbol browser and design given
circuit using the S-edit.
3. Give the external supply from the library to the circuit.
4. Write the program in the T-edit and run the simulation and check for errors.
5. Remove all the errors and again write the program in the T-edit and run.
6. Output waveform is viewed in the waveform viewer.
7. Get the net list and verify the output.

NETLIST:(CMOS INVERTER)
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.

Parsing "C:\Users\KARUNYA\Desktop\Module0.sp"

Device and node counts:

MOSFETs - 2
BJTs - 0
MESFETs - 0
Capacitors - 0
Inductors - 0

MOSFET geometries - 2
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 2

Current sources - 0

VCVS - 0

VCCS - 0

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CIRCUIT DIAGRAM FOR CMOS NOR GATE:

CODING:

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CCVS - 0

CCCS - 0

V-control switch - 0
Macro devices - 0
Subcircuits - 0

I-control switch - 0
Functional model instances - 0
Subcircuit instances - 0

Independent nodes - 1

Boundary nodes - 3

Total nodes - 4

Parsing

0.01 seconds

Setup

0.01 seconds

DC operating point

0.00 seconds

Transient Analysis

0.00 seconds

----------------------------------------Total

0.02 seconds

NETLIST:(CMOS NAND )
NETLIST:
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Device and node counts:
MOSFETs - 4
BJTs - 0
MESFETs - 0
Capacitors - 0
Inductors - 0
Transmission lines - 0

MOSFET geometries - 2
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors - 0
Coupled transmission lines - 0

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OUTPUT: NOT WAVEFORM

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Voltage sources - 3

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0
Macro devices - 0

I-control switch - 0
Functional model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 3

Boundary nodes - 4

Total nodes - 7
Warning T-SPICE : The vrange voltage range limit (5.5) for diode tables has been exceeded.
Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has been
exceeded.
Warning T-SPICE : The vrange voltage range limit should be set to
at least 7.63709 for best accuracy and performance.

Parsing

0.00 seconds

Setup

0.00 seconds

DC operating point

0.00 seconds

Transient Analysis

0.01 seconds

----------------------------------------Total

0.01 seconds

NETLIST:(CMOS NOR)
NETLIST:
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.

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OUTPUT: NAND WAVEFORM

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Parsing "F:\Softwares\Tanner\S-Edit\Module0.sp"

Device and node counts:

MOSFETs - 4

MOSFET geometries - 2

BJTs - 0

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 0

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 3

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0
Macro devices - 0
Subcircuits - 0

I-control switch - 0
Functional model instances - 0
Subcircuit instances - 0

Independent nodes - 2

Boundary nodes - 4

Total nodes - 6

Parsing

0.00 seconds

Setup

0.00 seconds

DC operating point

0.00 seconds

Transient Analysis

0.00 seconds

----------------------------------------Total

0.00 seconds

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OUTPUT: NOR WAVEFORM

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RESULT:
The design and simulation of a CMOS inverter,CMOS NAND and CMOS
NOR logic has been verified using tanner tools.
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CMOS HALF ADDER:

LOGIC DIAGRAM:

NETLIST:

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Ex No: 9
Date: 12-3-14

Dept. of ece

9.DESIGN AND SIMULATION OF CMOS HALF AND FULL

ADDERS

AIM:
To design and simulate CMOS half-adder and full-adder using tanner EDA.
SOFTWARE USED:
Tanner EDA 7.0
THEORY:
HALF ADDER:
A combinational circuit that performs the addition of 2 bits is called a half
adder. This circuit accepts two binary inputs and produces two binary outputs.
The input variables designate augends and addend bits; the output variables
designate sum and carry.
The simplified SOP terms are
sum = ab+ab
carry = ab
FULLADDER:
A combinational circuit that performs the addition of 3 bits is called a full
adder. This circuit accepts 3 binary inputs and produces two binary outputs. The
two outputs are denoted by sum and carry.
The simplified SOP terms are
sum= abc+abc+abc+abc
carry = ab + bc+ca
PROCEDURE:
1.Open the schematic editor(S-edit) from the tanner EDA tool.
2.Get the required components from the symbol browser and design given
circuit using the S-edit.

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OUTPUT: CMOS HALF ADDER:

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3.Give the external supply from the library to the circuit.

4.Write the program in the T-edit and run the simulation and check for errors.
5.Remove all the errors and again write the program in the T-edit and run.
6.Output waveform is viewed in the waveform viewer.
7.Get the net list and verify the output.
CMOS HALF ADDER:
TSPICE CODE:
* Waveform probing commands
.probe
.options probefilename="ADDER.dat"
+ probesdbfile="C:\Users\Lab-4\Desktop\ADDER.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M1 Bbar B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 Bbar B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 Abar A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 Ybar Abar N5 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 N5 B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 N2 A Ybar Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M7 Gnd Bbar N2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M8 sum Ybar Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M9 carry Abar Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M10 Gnd Bbar carry Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M11 Bbar B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M12 N3 Abar Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M13 Abar A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M14 Ybar A N3 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M15 Vdd B N3 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M16 N3 Bbar Ybar Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
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CMOS FULL ADDER:

LOGIC DIAGRAM:

NETLIST:

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M17 sum Ybar Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M18 N6 Abar Vdd N7 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M19 carry Bbar N6 N7 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v20 Vdd Gnd 5.0
.model pmos pmos
.model nmos nmos
v1 A gnd BIT ({110011})
v2 B gnd BIT ({100001})
.tran 4n 400n
.print A B sum carry
* End of main circuit: Module0

CMOS FULL ADDER:

TSPICE CODE:
* Waveform probing commands
.probe
.options probefilename="full.dat"
+ probesdbfile="C:\Users\karunya\Documents\Tanner\S-Edit\full.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M1 S1bar S1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 S2 Cbar N9 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 N7 C S2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 N9 S1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 Gnd S1bar N7 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 SUM S2 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M7 S1 Abar N5 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M8 N2 B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M9 N3 A S1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

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OUTPUT: CMOS FULL ADDER:

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M10 N5 B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M11 Gnd Bbar N3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M12 Bbar B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M13 Cbar C Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M14 Abar A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M15 S3 A N2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M16 N4 C Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M17 S3 B N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M18 N10 A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M19 S3 C N10 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M20 CARRY S3 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M21 S1bar S1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M22 S2 C N19 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M23 N19 S1bar S2 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M24 N19 Cbar Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M25 Vdd S1 N19 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M26 SUM S2 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M27 Vdd B N1 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M28 N1 A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M29 S1 A N6 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M30 N6 Bbar S1 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M31 Bbar B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M32 Cbar C Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M33 Abar A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M34 N6 Abar Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M35 Vdd B N6 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M36 Bbar B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M37 N1 C N8 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

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M38 N8 B N1 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M39 S3 C N8 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M40 N8 A S3 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M41 CARRY S3 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v42 Vdd Gnd 5.0
.model pmos pmos
.model nmos nmos
V1 A gnd BIT ({0011})
V2 B gnd BIT ({0101})
V3 C gnd BIT ({0010})
.tran 4p 400n
.print A B C SUM CARRY
* End of main circuit: Module0

RESULT:

The design and simulation of half-adder and full-adder has been verified using
Tanner.
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Ex No: 10
Date: 19-3-14

Dept. of ece

10.DESIGN AND SIMULATION OF CMOS TRANSMISSION

GATE AND MULTIPLEXER USING TG

AIM:
To design and simulate 2x1 Mux and Transmission gate using Tanner
software.
SOFTWARE USED:
Tanner EDA 7.0
THEORY:
MULTIPLEXER:
It is combinational circuit that selects binary information from one of the many
inputs and directs it to a single output. The selection lines or controlled lines. It
is used as a data selector and parallel to serial convertor. In reference to the
block diagram a two bit binary code on the data select input will also allow the
data on the corresponding data input to pass through the data output.
TRANSMISSION GATE:
Transmission gates also known as pass gates represents another class of
logic circuits which use TGs as basic building block. It consist of a PMOS and
NMOS connected in parallel. Gate voltage applied to these gates is
complementary of each other(C and Cbar). TGs act as bidirectional switch
between two nodes A and B controlled by signal C. Gate of NMOS is connected
to C and gate of PMOS is connected to Cbar(invert of C). When control signal
C is high i.e. VDD, both transistor are on and provides a low resistance path
between A and B. On the other hand , when C is low both transistors are turned
off and provides high impedance path between A and B.

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TRANSMISSION GATE
CIRCUIT DIAGRAM:

CODING:

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PROCEDURE:
1. Open the schematic editor(S-edit) from the tanner EDA tool.
2. Get the required components from the symbol browser and design given
circuit using the S-edit.
3. Give the external supply from the library to the circuit.
4. Write the program in the T-edit and run the simulation and check for errors.
5. Remove all the errors and again write the program in the T-edit and run.
6. Output waveform is viewed in the waveform viewer.
7. Get the net list and verify the output.

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OUTPUT:

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Netlist:(Transmission gate)
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "C:\Users\KARUNYA\Desktop\Module0.sp"
Device and node counts:
MOSFETs - 4

MOSFET geometries - 2

BJTs - 0

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 0

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 3

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0

I-control switch - 0

Macro devices - 0

Functional model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 2

Boundary nodes - 4

Total nodes - 6
Parsing

0.00 seconds

Setup

0.00 seconds

DC operating point
Transient Analysis
Total

0.00 seconds
0.03 seconds

0.03 seconds

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2X1 MULTIPLEXER
CIRCUIT DIAGRAM :

CODING:

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NETLIST:
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "F:\Softwares\Tanner\S-Edit\Module0.sp"
Warning T-SPICE : DC sources have non-unique names. "V1".
Device and node counts:
MOSFETs - 6

MOSFET geometries - 2

BJTs - 0

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 0

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 4

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0
Macro devices - 0
Subcircuits - 0

I-control switch - 0
Functional model instances - 0
Subcircuit instances - 0

Independent nodes - 2

Boundary nodes - 5

Total nodes - 7
*** 1 WARNING MESSAGES GENERATED
Parsing

0.00 seconds

Setup

0.00 seconds

DC operating point
Transient Analysis
Total

0.00 seconds
0.04 seconds

0.04 seconds

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OUTPUT:

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RESULT:
The design and simulation of transmission gate multiplexer has been
verified using Tanner tools
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Ex No: 11
Date: 26-3-14

Dept. of ece

11.DESIGN AND SIMULATION OF BICMOS LOGIC CIRCUITS

AND BOOLEAN EXPRESSION

AIM:
To design and simulate BICMOS inverter, BICMOS NAND
BICMOS NOR gate and Boolean expression using Tanner EDA.

and

SOFTWARE USED:
Tanner EDA 7.0
THEORY:
BICMOS on chip is obtained by merging CMOS and BJT devices.An
alternative solution to the problem of driving large capacitive loads can be provided
by BICMOS.Taking advantage of the low problem consumption of the CMOS and
the high current driving capability of BJT during transients, the BICMOS can
combine the best of both worlds.The BICMOS combination has significant
advantages to offer such as improved switching speed and less sensitivity w.r.t the
load capacitance.In general, BICMOS logic circuits are not bipolar intensive i.e most
logic operations are performed by conventional CMOS sub circuits,while the bipolar
transistor are used only when high on chip or off chip drive capability is required.
The most significant drawback of BICMOS circuit lies in the increased
fabrication process complexity,it requires 3-4 masks in addition to the well
established CMOS process.
BICMOS INVERTER:
It consists of two MOS transistors(inverter part) and two npn BJT which
can drive a large capacitive load.In addition,two n-MOS transistors(Mb1 & Mb2) are
usually added to provide the necessary base discharge path.
When the input voltage is very close to zero, the n-MOS transistors Mh
and Mb1 are off,whereas p-MOS transistor Mp and thus the n-MOS transistor Mb2
are on.Since the base voltage of Q2 is equal to zero the bipolar output pull down
transistor is in cut off mode,consequently, both the BJT Q1 and Q2 are not able to
conduct any current at this point.

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BOOLEAN CIRCUIT FOR (A+BC+ABC):

CODING:

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When the input voltage is increased beyond the threshold, the n-MOS
transistor Mn starts to conduct a non-zero base currents for Q2.Thus,the BJT Q1 and
Q2 enter the forward active region. The base emitter junction voltage of both
transistors rise very abruptly and cause step down in DC voltage characteristics.For
high voltage levels,the drain to source voltage of Mn is zero and no base current can
be supplied to Q2.
BICMOS NOR LOGIC:
The base of the bipolar pull up transistor Q1 is being driven by two series
connected p-MOS transistors.Therefore the pull up device can be turned on only if
both the inputs are logic low.
The base of the bipolar pull down transistor Q2 is being driven by two //lel
connected n-MOS transistors.Therefore, the pull down device can be turned on if
either one or both of the inputs are high.Also, the base charge of the pull up device is
removed by two minimum sized n-MOS transistors connected in //lel between the
base node and the ground.
BICMOS NAND LOGIC:
The base of the bipolar pull up transistor Q1 is being driven by two//lel
connected p-MOS transistors.Here, the pull up device is turned on when either one or
both of the inputs are logic low.The bipolar pull down transistor Q2 on the other hand
is driven by two series connected n-MOS transistors between output node and the
base.Therefore, the pulldown device can be turned on only if both of the inputs are
logic high.For the removal of the base charge of Q1 during turn off,two series
connected n-MOS transistors are used,whereas only one n-MOS transistor is utilised
for removing the base charge of Q2.

PROCEDURE:
1.Open the schematic editor(S-edit) from the tanner EDA tool.
2.Get the required components from the symbol browser and design given
circuit using the S-edit.
3.Give the external supply from the library to the circuit.
4.Write the program in the T-edit and run the simulation and check for errors.
5.Remove all the errors and again write the program in the T-edit and run.
6.Output waveform is viewed in the waveform viewer.
7.Get the net list and verify the output.
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BICMOS INVERTER CIRCUIT:

CODING:

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Boolean Expression NETLIST:

TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Device and node counts:
MOSFETs - 12

MOSFET geometries - 2

BJTs - 0

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 0

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 4

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0

I-control switch - 0

Macro devices - 0

Functional model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 6

Boundary nodes - 5

Total nodes - 11
Warning T-SPICE : The vrange voltage range limit (5.5) for diode tables has been exceeded.
Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has been exceeded.
Warning T-SPICE : The vrange voltage range limit should be set to at least 1480.5 for best accuracy
and performance.
Parsing

0.04 seconds

Setup

0.00 seconds

DC operating point
Transient Analysis
Total

0.00 seconds
4.23 seconds

4.27 seconds
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BICMOS NAND CIRCUIT:

CODING:

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INVERTER NETLIST:
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Device and node counts:
MOSFETs - 2

MOSFET geometries - 2

BJTs - 2

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 1

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 2

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0

I-control switch - 0

Macro devices - 0

Functional model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 3

Boundary nodes - 3

Total nodes - 6
Warning T-SPICE : The vrange voltage range limit (5.5) for diode tables has been exceeded.
Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has been exceeded.
Warning T-SPICE : The vrange voltage range limit should be set to at least 25.525 for best accuracy
and performance.
Parsing

0.03 seconds

Setup

0.00 seconds

DC operating point
Transient Analysis
Total

0.00 seconds
0.16 seconds

0.19 seconds
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BICMOS NOR CIRCUIT:

CODING:

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BICMOS NAND NETLIST:

TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.

Device and node counts:

MOSFETs - 4

MOSFET geometries - 2

BJTs - 2

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 1

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 3

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0

I-control switch - 0

Macro devices - 0

Functional model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 3

Boundary nodes - 4

Total nodes - 7

Parsing

0.01 seconds

Setup

0.00 seconds

DC operating point
Transient Analysis

0.01 seconds
5.35 seconds

----------------------------------------Total

5.37 seconds
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Output :(Boolean Expression)

Output: (NOT Gate)

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BICMOS NOR GATE NETLIST:

TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.

Parsing "F:\Softwares\Tanner\S-Edit\Module0.sp"

Device and node counts:

MOSFETs - 4

MOSFET geometries - 2

BJTs - 2

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 1

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 3

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0

I-control switch - 0

Macro devices - 0

Functional model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 3

Boundary nodes - 4

Total nodes - 7
Parsing

0.03 seconds

Setup

0.00 seconds

DC operating point
Transient Analysis

0.00 seconds
0.01 seconds

----------------------------------------Total

0.04 seconds
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OUTPUT: (NAND GATE)

Output: (NOR Gate)

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RESULT:
The design and simulation of BICMOS inverter, BICMOS NAND,
BICMOS NOR logic and a Boolean Expression has been verified using tanner
tools.
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DYNAMIC LOGIC CIRCUIT:

Coding:

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Ex No: 12
Date: 2-04-14

Dept. of ece

12.DESIGN AND SIMULATION OF DIFFERENT CMOS DESIGN

STYLES

AIM:
To design and simulate different CMOS design styles using tanner EDA
for the expression .((A.B)+C)
SOFTWARE USED:
Tanner EDA 7.0
THEORY:
Dynamic logic:
In static circuits the output is connected to either GND or VDD via a
low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices.
Dynamic circuits use temporary storage of signal values on the
capacitance of high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors.
Conditions on Output:
1.Once the output of a dynamic gate is discharged, it cannot be charged
again until the next precharge operation.
2.Inputs to the gate can make at most one transition during evaluation.
3.Output can be in the high impedance state during and after evaluation
(PDN off), state is stored on CL.
Properties of dynamic gates:
1. Overall power dissipation usually higher than static CMOS
no static current path ever exists between VDD and GND (including
Psc)
no glitching
higher transition probabilities
extra load on Clk
2.PDN starts to work as soon as the input signals exceed VTn, so VM, VIH
and VIL equal to VTn
low noise margin (NML)
3.Needs a precharge/evaluate clock.
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DOMINO LOGIC :(circuit)

Coding:

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Advantages of dynamic logic:

smaller area than fully static gates
smaller parasitic capacitances hence higher speed
reliable operation if correctly designed.
DOMINO LOGIC:
When CLK is low, dynamic node is precharged high and buffer inverter
output is low.
Nfets in the next logic block will be off. When CLK goes high, dynamic
node is conditionally discharged and the buffer output will conditionally
go high.
Since discharge can only happen once, buffer output can only make
one low-to-high transition.
When domino gates are cascaded, as each gate evaluates, if its output
rises, it will trigger the evaluation of the next stage, and so onlike a
line of dominos falling.
Like dominos, once the internal node in a gate falls, it stays fallen
until it is picked up by the precharge phase of the next cycle. Thus
many gates may evaluate in one eval cycle.
PSEUDO LOGIC:
Uses a p-type as a resistive pullup, n-type network for pulldowns.

Characteristics:
Consumes static power.
Has much smaller pullup network than static gate.
Pulldown time is longer because pullup is fighting.
Producing O/P Voltages:
For logic 0 output, pullup and pulldown form a voltage
divider.

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PSEUDO LOGIC:

CODING:

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Must choose n, p transistor sizes to create effective

resistances of the required ratio.
Effective resistance of pulldown network must be comptued
in worst caseseries n-types means larger transistors.

PROCEDURE:
1.Open the schematic editor(S-edit) from the tanner EDA tool.
2.Get the required components from the symbol browser and design given
circuit using the S-edit.
3.Give the external supply from the library to the circuit.
4.Write the program in the T-edit and run the simulation and check for errors.
5.Remove all the errors and again write the program in the T-edit and run.
6.Output waveform is viewed in the waveform viewer.
7.Get the net list and verify the output.

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OUTPUT:(Dynamic logic)

OUTPUT:(Domino logic)

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DYNAMIC LOGIC :(Netlist)

TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.

Parsing "C:\Users\KARUNYA\Desktop\VLSI 12TH lab\Domino\Module0.sp"

Device and node counts:
MOSFETs - 5

MOSFET geometries - 2

BJTs - 0

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 0

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 5

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0

I-control switch - 0

Macro devices - 0

Functional model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 3

Boundary nodes - 6

Total nodes - 9
Parsing

0.01 seconds

Setup

0.00 seconds

DC operating point
Transient Analysis

0.00 seconds
0.01 seconds

----------------------------------------Total

0.02 seconds

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OUTPUT:(Pseudo logic)

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Domino logic:(Netlist)
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Device and node counts:
MOSFETs - 9

MOSFET geometries - 2

BJTs - 0

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 0

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 4

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0

I-control switch - 0

Macro devices - 0

Functional model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 6

Boundary nodes - 5

Total nodes - 11

*** 1 WARNING MESSAGES GENERATED

Parsing

0.01 seconds

Setup

0.00 seconds

DC operating point
Transient Analysis

0.00 seconds
0.07 seconds

----------------------------------------Total

0.08 seconds
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Pseudo Logic:(Netlist)
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "F:\Softwares\Tanner\S-Edit\Module0.sp"
Device and node counts:
MOSFETs - 4

MOSFET geometries - 2

BJTs - 0

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 0

Resistors - 0

Inductors - 0

Mutual inductors - 0

Transmission lines - 0

Coupled transmission lines - 0

Voltage sources - 4

Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0
Macro devices - 0
Subcircuits - 0

I-control switch - 0
Functional model instances - 0
Subcircuit instances - 0

Independent nodes - 2

Boundary nodes - 5

Total nodes - 7
Warning T-SPICE : The vrange voltage range limit (5.5) for diode tables has been exceeded.
Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has been exceeded.
Warning T-SPICE : The vrange voltage range limit should be set to
at least 28.6857 for best accuracy and performance.
Parsing

0.01 seconds

Setup

0.00 seconds

DC operating point
Transient Analysis
Total

0.00 seconds
0.01 seconds

0.02 seconds

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Result:
The design and simulation of dynamic,domino and Pseudo logics has
been verified using Tanner.
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