Ahmed Hassouna

213440 Digital System Design

Fall 2010 Mid Exam
Name

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Student ID

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Signature

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DO NOT OPEN
UNTIL TOLD TO DO SO
Instructions:
1. Please verify that your paper contains 6 pages excluding this cover.
2. Write down your name on the top of each page of this test.
3. This exam is closed book. No notes or other materials are permitted.
4. Total time is 1 Hours.
5. Total credits of this exam are 35 points.
6. To receive credit you must show your work clearly.
7. No re-grades will be entertained if you use a pencil.
8. Calculators are NOT allowed.
9. Mobile phones are NOT allowed.

Problem

Max Points

12

15

Actual

Total

Ahmed hassouna

Ahmed Hassouna
Student ID: ____________________
Ques-1: [FSM]

[2-5-2-3 points]

Design a Moore state diagram that recognizes an input sequence 11101. It has an input X
and output Y. The recognizer sets the output to 1 (Y = 1) for exactly one clock cycle if
the last five values on the input X were 11101.

a. For the given input sequence, define the output sequence.

X
Y

b. Draw the state machine.

c- How many FFs are required to implement this FSM.

Ahmed hassouna

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Ahmed Hassouna
Student ID: ____________________
d. Create the state table.

Present State

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Input

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Next State

Output

Ahmed Hassouna
Student ID: ____________________
Ques-2: [Sequential logic synthesis]

[15 points]

The following state machine is a recognizer that reads a stream of bits. When the
recognizer finds the sequence 11 or 00, it will set the output to 1, and start all over.
The input is represented by x. The output is represented by z. It is a Moore FSM output
depends only on the present state. Design the FSM using (D-type flip flops).

S0:00
S1:01
S2:10
S3:11

(a) Write the state table

Present
State
Q1 Q0

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Input
X

Next
State
Q1
Q0

Flip-flop
inputs
D1
D0

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Output
Z

Ahmed Hassouna
Student ID: ____________________
b- Find the equations

c) Draw the sequential circuit. Label your diagram clearly.

Ahmed hassouna

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Ahmed Hassouna
Student ID: ____________________
Ques-3: [FSM VHDL]

[1-1-1-5 points]

The following VHDL code is for a simple Finite State Machine (FSM).

a) Is the VHDL code for Mealy FSM or Moore FSM.

b) How many FFs are required to construct this FSM.

c) Is the rest signal synchronous or asynchronous.

Ahmed hassouna

library IEEE;
use IEEE.std_logic_1164.all;
entity fsm is
port (clk, reset, x1 : IN std_logic;
outp : OUT std_logic);
end entity;
architecture beh1 of fsm is
type state_type is (s1,s2,s3,s4);
signal state: state_type;
begin
process (clk,reset)
begin
if (reset ='1') then
state <=s1; outp<='1';
elsif (clk='1' and clk'event) then
case state is
when s1 => if x1='1' then state <= s2;
else state <= s3;
end if;
outp <= '1';
when s2 => state <= s4; outp <= '1';
when s3 => state <= s4; outp <= '0';
when s4 => state <= s1; outp <= '0';
end case;
end if;
end process;
end beh1;

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Ahmed Hassouna
Student ID: ____________________
d) Draw the state diagram.

Ahmed hassouna

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