Professional Documents
Culture Documents
REQUIREMENTS:
a) Supply voltage: 2.5 V
b) Implementation choices:
a. Use any design style, static logic (CMOS, pass-transistor logic, dynamic gates etc.)
b. You are to use AT MOST 4 adder modules (that is, N-bit adders) in your design.
c) Input operands:
a. Dividend and divisor are 8 bits wide (based on this, you need to determine the width of
the remainder and quotient)
b. Both dividend and divisor are positive numbers (leading zero)
d) Clock waveform
a. Input rise and fall times of the clock waveform are equal trise = tfall = 100ps
b. Clock swing is from 0 to 2V (Is there an advantage?)
e) Loading conditions
a. The input capacitance of your divisor and divider is Cin = 1 unit sized inverter (per bit)
b. Unit sized inverter is Wp = 2m, Wn = 1m, Lp = Ln = 0.25m
c. Each bit of the quotient and reminder is loaded with CL = 25 unit sized inverters
2. SIMULATION
Analyze the circuit by using SPICE to simulate the design and prove that it functions
correctly. You will need to determine the input pattern that causes the worst-case
propagation delay or energy consumption by analyzing your circuit schematic.
3. REPORT
The quality of your report is as important as the quality of your design. One must sell the
design by justifying all design decisions. Be sure to provide all relevant information.