IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 40, NO.

6, NOVEMBER/DECEMBER 2004

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Optimal Common-Mode Voltage Reduction PWM

Technique for Inverter Control With Consideration of
the Dead-Time EffectsPart I: Basic Development
Yen-Shin Lai, Senior Member, IEEE, and Fu-San Shyu

AbstractThe objective of this paper is to investigate the optimal

common-mode voltage reduction pulsewidth modulation (PWM)
technique when dead-time effect is taken into account. The effect
of dead time on common-mode voltage for inverter control and the
associated solution are discussed. Based upon these results, an optimal common-mode voltage reduction PWM technique, which requires no extra voltage/current sensors and compensation mechanism while not being affected by the dead time, is recommended.
The common-mode voltage can be reduced to one-third for the inverter with diode front end, which is widely used in industry. Intensive measured results are presented to fully support the claims.
Index TermsCommon-mode voltage, pulsewidth modulation
(PWM), space-vector modulation.
Fig. 1. Block diagram for one of the three inverter legs.

I. INTRODUCTION

HE increase of inverter switching frequency significantly

reduces the harmonic contents of inverter output waveforms. However, this improvement is accompanied by some
adverse effects, including the well-known common-mode current issue. The common-mode current of a three-phase inverter
system associated with common-mode voltage causes fault activation of current detection circuits [1], undesired electromagnetic interference (EMI) [2], and damage to motor bearings for
motor applications.
The solutions to cope with the common-mode voltage/current
issue include common-mode choke [3], four-phase inverter [4],
and filter [1], [5], [6]. The software approaches, which change
inverter control techniques to mitigate the common-mode
voltage, have also been presented for two-level inverters
[7][10] and three-level inverters [11], [12].
The PWM techniques shown in [8] and [9] use only nonzero
switching states for two-level inverter control. These approaches
do not invoke any zero switching state to reduce the commonmode voltage. However, the linear modulation range in [9] is
reduced, thereby reducing the range of speed (torque) control.
Reference [10] removes this limitation, however, the presented
technique is only for an inverter with an active front end.
Paper IPCSD-04-053, presented at the 2003 Industry Applications Society
Annual Meeting, Salt Lake City, UT, October 1216, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Drives Committee of the IEEE Industry Applications Society. Manuscript
submitted for review November 1, 2003 and released for publication July 9,
2004. This work was supported by the National Science Council (NSC), Taiwan,
R.O.C.
The authors are with the Department of Electrical Engineering National
Taipei University of Technology, Taipei 106, Taiwan, R.O.C. (e-mail:
yslai@ntut.edu.tw).
Digital Object Identifier 10.1109/TIA.2004.836149

The newly developed common-mode voltage reduction techniques [7], [8] have been shown to have no adverse effect on the
linear modulation range [13] and can be applied to both
and vector-controlled inverters with diode front ends. However,
the effect of dead time on the common-mode voltage issue has
not yet been discussed.
This paper investigates the optimal common-mode voltage
reduction pulsewidth modulation (PWM) techniques when
dead-time effect is taken into account. The effect of dead
time on common-mode voltage and the associated solution
are discussed. Based upon the investigations, an optimal
common-mode voltage reduction PWM technique will be
recommended. The common-mode voltage associated with
this technique is not affected by the dead time. Therefore,
the common-mode voltage can be reduced to one-third for
the inverter with diode front end, despite dead-time effect. Experimental results are presented to fully support the
above-mentioned claims.
The effect of dead time on inverter control will be explained
first, followed by the common-mode voltage reduction PWM
techniques. Then, the effects of dead time on the common-mode
voltage will be presented. Finally, an optimal common-mode
voltage reduction PWM technique will be recommended when
dead-time effect is considered
II. EFFECT OF DEAD TIME ON INVERTER CONTROL
In this section the effect of dead time on the inverter control
will be discussed for the development to follow.
Fig. 1 illustrates the block diagram for one of the three inverter legs. As shown in Fig. 1, the rising edges of PWM signals have proper delay which is greater than the turn-off time of
the power devices, such that the turn-off delay of power devices

0093-9994/04$20.00 2004 IEEE

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 40, NO. 6, NOVEMBER/DECEMBER 2004

TABLE I
SWITCHING PATTERNS FOR COMMON-MODE VOLTAGE REDUCTION
PWM TECHNIQUE, NSVM 1

TABLE II
SWITCHING PATTERNS FOR COMMON-MODE VOLTAGE REDUCTION PWM
 = Boolean Not of \S "
TECHNIQUE, NSVM 2; S

TABLE III
SWITCHING PATTERNS FOR COMMON-MODE VOLTAGE REDUCTION PWM
S = Exclusive OR of \S " and \S "
TECHNIQUE, NSVM 3; S

analysis has been shown [14] that the rms amplitude of fundamental voltage error is proportional to dead time and inverter
switching frequency as described in (1)
(1)
where
dc-link voltage;
dead time;
switching frequency.
For an inverter with 5-kHz switching frequency, dead time
s, and 310-V dc-link voltage, the voltage error caused by
kHz
s
V
V.
the dead time is:
Although the value seems trivial, the associated adverse effect
on vector-controlled drive performance becomes relevant in the
low-speed range, especially with high switching frequency and
greater dead-time value [15].
III. COMMON-MODE VOLTAGE REDUCTION TECHNIQUES

Fig. 2. Illustrations of control signals without and with dead-time control, and
the associated output voltages.

will not cause short circuit and damage to the power devices.
Fig. 2 illustrates the control signals without and with dead-time
control, and the associated output voltage. As shown in Fig. 2(a),
during the period of dead time (freewheeling period), the output
voltage is clamped to the negative dc-link rail by the low-side
antiparallel diode for providing a positive line current. Under
this circumstance, the output voltage is smaller than that of the
ideal case. In contrast, when the current is negative, the output
voltage is clamped to the positive dc-link rail by the upper side
antiparallel diode during the freewheeling period.
, defined as the inverter output voltage
The voltage error
minus its ideal counterpart (output without dead time), depends
upon the direction of current, as shown in Fig. 1. A simplified

Theoretically, the common-mode voltage can be reduced to

one-third of the dc-link voltage without using any null switching
states [7], [8]. The basic concept is to use nonzero switching
states which correspond to the voltage vectors with 180 phase
shift, to replace the null switching state, while not affecting the
linear modulation range.
Tables IIII summarize the switching patterns for these
newly developed common-mode voltage reduction PWM techniques. The vector times are the same as those for three-phase
modulation techniques [18]. However, the null switching states
S and S are replaced by S and S , respectively, as illusBoolean Not of S
trated in Table I. In Table I, S
S
switching states, either (100), (010), or (001);
switching states of inverter control, either (110), (011),
S
or (101); S and S are (000) and (111) switching states,
respectively
For inverter-controlled drives with diode front end as shown
in Fig. 3, the common-mode voltage is defined by (2)
(2)

LAI AND SHYU: OPTIMAL COMMON-MODE VOLTAGE REDUCTION PWM TECHNIQUE FOR INVERTER CONTROLPART I

Fig. 3.

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Inverter-controlled motor drive system.

Fig. 4 shows the common-mode voltages for the techniques

[7], [8]. In theory, the common-mode voltage is limited to
one-third dc-link voltage rather than dc-link voltage as compared with that for conventional PWM techniques. Moreover,
the number of commutations in a sampling period is the same
as that for three-phase modulation technique.
IV. OPTIMAL COMMON-MODE VOLTAGE CONSIDERING
DEAD-TIME EFFECT
Fig. 5 shows the common-mode voltages for a three-phase inverter system with 310-V dc-link voltage and 2- s dead time. As
shown in Fig. 5, the maximum peak-to-peak value of commonmode voltage is up to around 200 V for the inverter controlled
by NSVM1 technique. As shown in the previous section, the
theoretical value would be approximately 100 rather than 200
V. Moreover, as shown in Fig. 5, the number of these unexpected peaks of common-mode voltage increases when the inverter switching frequency increases.
We may have the following questions when we see Fig. 5. Does
the common-mode voltage technique work? What is the reason
for these unexpected peaks of common-mode voltages? Can this
issue be solved? What would be the cost to pay for? We will look
into the reasons for these unexpected peaks shown in Fig. 5 and
give the answers to the above-mentioned issues in this section.
Fig. 6 shows the measured results for NSVM1 technique.
As shown in Fig. 6(a), the unexpected peak occurs during the
period of dead time. As highlighted in Fig. 6(b), when the current of phase c is positive, and the currents of phase a and
phase b are negative, the unexpected peaks of common-mode
voltage occur. Fig. 7 illustrates the theoretical analysis for
the case highlighted in Fig. 6. As shown in Fig. 7(a), the
common-mode voltage varies between
and
, without considering the dead-time
effect. Fig. 7(b) shows the voltage waveforms, including
common-mode voltage, while taking the dead-time effect into
account. As shown in Fig. 7(b), the unexpected peak occurs
when the current of phase c is positive, and currents of phase
a and phase b are negative. Under these circumstances,
the output voltage for phase a and phase b are clamped to
the positive dc-link rail as shown in Fig. 1 and explained in
, which
Section II, thereby resulting in a peak of
gives a peak of approximately 200 V as referred to the negative
.
peak,
A similar situation can happen to SVM2 PWM technique as
illustrated in Fig. 8 when the current of phase b is negative,
and currents of phase a and phase c are positive. Under

Fig. 4. Common-mode voltage for the common-mode voltage reduction

techniques.

this condition, the output voltages for phase a and phase c

are clamped to the negative dc-link rail as shown in Fig. 1 and
explained in Section II, thereby resulting in a peak of
.
As we carefully inspect the switching patterns and commonmode voltage waveforms shown in Figs. 7 and 8, we can conclude that the unexpected peaks of common-mode voltage may

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 40, NO. 6, NOVEMBER/DECEMBER 2004

Fig. 6. Measured results for NSVM1 PWM technique.

Fig. 5. Common-mode voltage waveforms for NSVM1 PWM technique, X =

2 ms=div, Y = 50 V=div.

come out only at the instants when two phases commutate simultaneously. At these commutation instants, the outputs of three
phases are clamped to either the positive or negative dc-link
rail caused by the dead time, thereby increasing the commonmode voltage even when using only nonzero switching states. In
theory, the common-mode voltage reduction PWM techniques,
NSVM1 and NSVM2, work well for no dead-time effect.
It is well known that dead-time control is unavoidable for
inverter control. Can the dead-time effect on the common-mode
voltage be overcome? What would be the cost? Several deadtime compensation techniques have been proposed to deal with
the voltage distortion issue caused by dead-time control [14],
[16]. However, either a voltage or current sensor is required to
detect the direction of current and polarity of output voltage,
respectively.
Based upon the above-mentioned conclusion, there will be
no chance to clamp all three-phase outputs to either positive
or negative dc-link rails if only one of the three phases commutates at any commutation instant and no zero switching
state is invoked for inverter control. Under these two conditions,
the common-mode voltage will be limited within
and
, despite of the current
direction of currents or polarities of output voltages.

LAI AND SHYU: OPTIMAL COMMON-MODE VOLTAGE REDUCTION PWM TECHNIQUE FOR INVERTER CONTROLPART I

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Fig. 9. Illustration of voltage waveforms for optimal common-mode voltage

reduction PWM technique with considering dead-time effect.

Fig. 7. Illustration of voltage waveforms for NSVM1 PWM technique.

Fig. 8. Illustration of voltage waveforms for NSVM2 PWM technique.

However, unexpected peaks of common-mode voltage caused

by dead-time effect may occur at the transition of two sectors
for double-edge modulation. Fig. 10(a) illustrates this kind of
special case using the transition between Sector 1 and Sector
2 as an example. As shown in Fig. 10(a), the common-mode
voltage (absolute value) arises when the three terminals of inverter output are connected to the negative dc-link rail caused
by the dead-time effect at the transition point.
Fig. 9 illustrates the voltage and common-mode voltage
waveforms for the NSVM3 PWM technique. As shown in
Fig. 9, only one of the three phases commutates at any commutation instant and no zero switching state is invoked for inverter
control. Therefore, the common-mode voltage varies between
and
, despite the
direction of currents or polarities of output voltages. Therefore,
taking dead-time effect into consideration, NSVM3 PWM
technique is the optimal PWM approach for common-mode
voltage reduction.
Similar results occur when the three terminals of inverter
output are connected to the positive dc-link rail caused by
the dead-time effect at the transition point. This issue can be

Fig. 10.

Modifications to the switching patterns at the transition of sectors.

coped with by retaining the edge sequence as demonstrated

in Fig. 10(b). As shown Fig. 10(b), the edge sequence is not
toggled as the reference voltage crosses over the sectors. Therefore, three terminals of the inverter output are not connected

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Fig. 11.

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 40, NO. 6, NOVEMBER/DECEMBER 2004

Experimental system.

Fig.
12. Experimental
results,
modulation index = 0:575 p.u.

NSVM

PWM

Fig.
13. Experimental
results,
modulation index = 0:8 p.u..

NSVM

PWM

technique,

Fig.
14. Experimental
results,
modulation index = 1:15 p.u..

NSVM

PWM

technique,

technique,

to the negative or positive dc-link rail simultaneously, even

considering dead-time effect.
V. EXPERIMENTAL RESULTS
Fig. 11 shows the experimental system, which consists of
an insulated gate bipolar transistor (IGBT) inverter, field-programmable gate array (FPGA) controller, A/D converter, and
control, in which
induction motor. The induction motor has
the fundamental frequency is proportional to the modulation
index. The input signals, therefore, include the modulation
index and switching frequency, which are converted to digital
ones by the A/D converter. The FPGA realizes the requested
logic circuits for PWM control as demonstrated in [17]. The
dead time is 2 s and the dc-link voltage is 310 V. As the active
pulsewidth is less than 2 s, it is retained at 2 s to avoid any
potential damage to the IGBT.
Figs. 1214 show the experimental results for NSVM3
PWM techniques for inverter switching frequency of 2 kHz,

and modulation index in p u

0.575, 0.8 and 1.15, respectively. The experimental waveforms include PWM voltage,
common-mode voltage, and three-phase currents.
As shown in these experimental results, the common-mode
voltage is restricted to approximately 100 V; see Trace 2
of these figures, 100 V/div, which is around one-third dc-link
voltage, even under the effect of dead time, thereby confirming
the theoretical analysis.
Moreover, the common-mode voltage PWM technique does
not cause any adverse effect on the modulation range. The maximum linear modulation range is 1.15 (in p.u.) which is the same
as that for conventional space-vector modulation techniques.
Similar results for the NSVM 3 PWM technique can also be
derived for other cases with various switching frequencies, as illustrated in Fig. 15. As shown in Fig. 15, for a three-phase inverter
system with 2- s dead time, the maximum peak-to-peak value of
common-mode voltage is around 100 V. As compared to Fig. 5 for
the NSVM 1 technique, no unexpected peaks of common-mode

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VI. CONCLUSION
This paper has contributed to the investigation of the
dead-time effect on the common-mode voltage. It has been
shown that the common-mode voltage may not be restricted
to the theoretical value for common-mode voltage reduction
techniques under the effect of dead time. The reasons were
explored by both theoretical analysis and experimental results.
Based upon these results, an optimal common-mode voltage
reduction PWM technique was recommended, which restricts
the common-mode voltage peaks to one-third dc-link voltage,
without any compensation technique, while not causing any
adverse effect on the linear modulation range. Experimental
results were presented to fully support the above-mentioned
claims.
For the effect of common-mode voltage reduction PWM technique on the performance of motor drives, the reader can be
referred to [19]. Moreover, the effect of distribution of zero
voltage vectors on harmonic content has been discussed in [20].
We will report on the effect of common-mode voltage PWM
techniques without using zero voltage vectors on current harmonics and core losses in the future.

REFERENCES

Fig. 15.

Common-mode voltage waveforms for NSVM3 PWM technique,

X = 2 ms=div, Y = 50 V=div.

voltage caused by dead-time effect occur. Therefore, these experimental results confirm that the presented technique reduces the
common-mode voltage to one-third despite the inverter switching
frequency when dead-time effect is considered.

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Yen-Shin Lai (M96SM01) received the M.S. degree from National Taiwan University of Science and
Technology, Taipei, Taiwan, R.O.C., and the Ph.D.
degree from the University of Bristol, Bristol, U.K.,
both in electronic engineering.
In 1987, he joined National Taipei University of
Technology, Taipei, Taiwan, R.O.C., as a Lecturer.
He is currently a Professor and Chairman of the Department of Electrical Engineering. His research interests include design of control IC for the applications of power electronics, dcdc converter control
and inverter control.
Dr. Lai received the John Hopkinson Premium for the 19951996 session
from the Institution of Electrical Engineers, U.K., and the Third Prize Paper
Award from the Industrial Drives Committee of the IEEE Industry Applications
Society in 2002.

Fu-San Shyu received the B.S. and M.S. degrees in

electrical engineering from National Taipei University of Technology, Taipei, Taiwan, R.O.C., where he
is currently working toward the Ph.D. degree.
His research interests include inverter/converter
control and circuit design.