National University of Computer & Emerging Sciences

A#2

EE227: Digital Circuit Design

Sections: A, B, C (Fall 2015)
Issue date

Due date

Instructor: Azhar Rauf

Saturday

Tuesday

Sep 19

Sep 29

Solo Assignment Quiz Based

Name: ____________________________

Roll No: ________________

Signature: _________________________

Section: ________________

Important Notes:

Submission Guidelines:

1.

Failure to follow these may VOID your assignment.

ZERO Tolerance Policy for plagiarism and

cheating.

2.

Violators may receive F in the course and/or will

1.

This cover must be first page of the assignment.

be reported to the Department Discipline Committee

2.

Assignments should be done on A4 sized blank

white (photocopy) paper (70g).

(DDC).
3.

Assignments may carry unequal weights.

3.

Multiple pages must be double stapled.

4.

No retake or allocation of average marks for

4.

No binding (file, transparent, ring binding etc).

assignments in any case, irrespective of the reason,

5.

Assignment must be submitted on or before the due

date listed above. If in class, submit @ class start.

genuine or otherwise.
6.

No late assignment accepted after due date or after

class start.

7.

Do not write anything below.

If grading is based on quiz, quiz date will be same

as submission date.

Checked by
Plagiarism
% Attempted
Total Marks

Yes

No

Marks Obtained

NUCES-FAST: Fall15: DLD (EE)

Assign # 02

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1. Implement following logical functions without minimization using i) NAND ii) NOR

a)
b)
c)
d)
e)

F=(X+YZ) (Y+Z)
F=( (XYZ)+(YX) )
F=WX+YZ+WYZ
F(W,X,Y,Z) = (0,4,11,14)
F(W,X,Y,Z)=(0,4,11,14)

2. With reference to Question 1 discuss which implementation is better (NAND or NOR)? Do both
implementations require same level of gates? Can you spot a trend that would indicate which
implementation is optimal before actually implementing it?

3. With the use of maps, find the simplest sum-of-products form of the function F = f.g, where:
f = abc + cd + acd + bc
and
g = (a + b + c + d) (b + c + d) ( a + c + d)

4. Analyze following circuit and write equation for x10.

5. Design and implement a BCD to Excess-3 code converter. What is the gate count for this
implementation? Can you reduce the gate count by gathering common terms in the output
equations?

NUCES-FAST: Fall15: DLD (EE)

Assign # 02

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6. A majority circuit is a combinational circuit whose output is equal to 1 if the input variables
have more 1s than 0s. The output is 0 otherwise.
a) Design a 3-input majority circuit by finding the circuits truth table, Boolean
equation, and a logic diagram.
b) Verify the logic diagram in part a) above using Proteus. Attach screenshot.

7. A committee has five members (including head). They are gathered in meeting hall to pass a bill.
The head of committee has decided to take vote of all members. All members can vote YES or
NO (0 or 1). If more than 60% voters agree, the bill will be passed else it will be discarded.
Design a logic circuit to turn on RED or GREEN LED to show if bill is passed or not.

8. What if in Question 7 vote of the head of committee has 40% weight and other members votes
has remaining equal weight. Design a logic circuit to turn on RED or GREEN LED to show if bill
is passed or not.

9. Design a combinational circuit that converts a four-bit Gray code (see Table 1.6 in text) to a fourbit binary number.
a) Implement the circuit with exclusive-OR gates.
b) Implement the circuit with NAND gates.

10. The control logic for a simple alarm system in a house has three inputs and a single output, which
activates an alarm. The three inputs are:

windows sensor
doors sensor
master key

The sensors operate as follows:

window sensor (W)

door sensor (D)
master key (K)

0 = all windows closed;

1 = a window is open
0 = all doors closed;
1 = a door is opened
0 = alarm system is disarmed; 1 = alarm system is armed

If the alarm system is disarmed then the logic signals from the sensors are ignored and the alarm
will not sound. The alarm is activated by logic 1 from the output of the control logic. Design the
circuit to meet the requirements of this control logic.

End of Assignment No. 2

NUCES-FAST: Fall15: DLD (EE)

Assign # 02

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