Switching Circuits & Logic Design

Multi-level Gate Circuits

NAND and NOR Gates
Professor Chien-Mo James Li
Graduate Institute of Electronics Engineering
National Taiwan University
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Review Questions
What is K map
How to obtain SOP from K map?

How to obtain POS from K map?

What is Prime Implicant?
Essential prime implicant?

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Objective of this Chapter

Design minimal two-level and multi-level circuits using

AND-OR OR-AND
NAND
NOR

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Outline

Multi-Level Gate Circuits.

NAND and NOR Gates.
Design of Two-Level Circuits Using NAND and NOR Gates.
Design of Multi-Level NAND and NOR Gate Circuits.
Circuit Conversion Using Alternative Gate Symbols.
Design of Two-Level, Multiple-Output Circuits
Determination of Essential Prime Implicants for Multiple-Output
Realization.
Multiple-Output NAND and NOR Circuits.

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Level of Gates
Maximum number of gates cascaded in series between a circuit
input and the output is the number of levels of gates
AND OR NAND NOR counted
Inverter not counted

Example: four-level logic

Fig 7-1

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Terminology
AND-OR circuit

Two-level circuit
A level of AND gates followed by an OR gate at the output
OR-AND circuit
Two-level circuit
A level of OR gates followed by an AND gate at the output
OR-AND-OR circuit
Three-level circuit
A level of OR gates, followed by
A level of AND gates, followed by
A OR gate at the output
Circuits of AND and OR
No particular ordering of gates

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Boolean Expression
AND-OR circuit SOP

Factor out some terms increases the number of levels

OR-AND circuit POS
Multiply out some terms increases the number of levels

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Why Care Levels?

We used to use two-level circuits

AND-OR; OR-AND

Why care about multi-level circuits?

1. More levels sometimes reduce area

But not always
2. More level usually mean more delay
Slower circuit

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3-level Realization
Fig 7-2
Gate count: 6 gates, 19 gate inputs

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4-level Realization
Fig 7-1

Gate count: 6 gates, 13 gate inputs

Smaller area in 4-level realization, but longer delay

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Food for Thought

Q: Which is better? 3-level or 4-level implementation?

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Multi-level Design Example

Fig 7-3

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SOP Realization
SOP is two level
Partial factor to three level

Fig. 7-4

Fig. 7-5

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POS Realization
POS is two level
partial multiply out is 3 level

Fig. 7-6

Fig. 7-7
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Comparison of area
SOP

3-level better than 2-level

POS
2-level better than 3-level
SOP

POS

2-level

5 Gates
16 GI

5 Gates
14 GI

3-level

5 Gates
12 GI

7 Gates
16 GI

Unfortunately, there is no simple way to determine whether

POS is better than SOP or not

2-level is better than multiple level or not

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Complement
If an expression for f has n levels,

complement of that expression is also n level of expression for f

example P 194, (7-7)
f = c(d+ab) + c(d+ab)
= c(d+a)(d+b) + c(d+a)(d+b)

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(7-7)

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Outline

Multi-Level Gate Circuits.

NAND and NOR Gates.
Design of Two-Level Circuits Using NAND and NOR Gates.
Design of Multi-Level NAND and NOR Gate Circuits.
Circuit Conversion Using Alternative Gate Symbols.
Design of Two-Level, Multiple-Output Circuits
Determination of Essential Prime Implicants for Multiple-Output
Realization.
Multiple-Output NAND and NOR Circuits.

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NAND
NAND = AND + NOT
Fig 7-8

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NOR
NOR = OR + NOT
Fig 7-9

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Functionally Complete
For Logic Operation

A set of logic operation is said to be functionally complete if any

Boolean functions can be functionally complete in terms of this
set of operations

For Logic Gates

A set of logic gates is functionally complete if all switching

functions can be realized using this set of gates

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FC Example
{AND OR NOT} is FC
{AND NOT} is FC

Realize OR using {AND NOT}

P 196

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NAND is FC
Using only NAND to realize {AND OR NOT}
Fig 7-10

Of course, NOR is also FC

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AND is NOT FC
NOT impossible using only AND

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How to determine FC?

1. write a minimum SOP expression for the function realized by each

gate
2. if no complement appears
Then not FC because NOT impossible
3. Attempt to realize AND or OR
FC if AND or OR realizable

NOTE:

1 and 0 are available inputs

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Question
XOR is FC?

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Outline

Multi-Level Gate Circuits.

NAND and NOR Gates.
Design of Two-Level Circuits Using NAND and NOR Gates.
Design of Multi-Level NAND and NOR Gate Circuits.
Circuit Conversion Using Alternative Gate Symbols.
Design of Two-Level, Multiple-Output Circuits
Determination of Essential Prime Implicants for Multiple-Output
Realization.
Multiple-Output NAND and NOR Circuits.

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Two-Level Circuits
Example: Fig 7-11

F=A+BC+BCD Four possible forms starting from SOP

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Two-Level Circuits (contd)

Example: Fig 7-11 F=(A+B+C)(A+B+C)(A+C+D)

Four possible forms starting from POS

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Other Possibility?
The other eight possible two-level forms are not FC

AND-AND OR-OR OR-NOR AND-NAND

Example

NAND-NOR is actually AND

Not FC
p 199

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Mini 2-level NAND-NAND

Design Procedure

1. find a minimum SOP for F

2. Draw corresponding two-level And-OR circuit
3. Replace all gates with NAND
Interconnect unchanged
Complement inputs of the output gate
Why ? DeMorgans Law
If F = l1+l2 + l3 + + P1 + P2 + P3
Then F = (l1l2l3P1P2P3)

Fig. 7-12
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Mini 2-level NOR-NOR

Design procedure

Similar to NAND-NAND

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FFT
Q: Why NAND? Why NOR? They are not easy to understand.

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Outline

Multi-Level Gate Circuits.

NAND and NOR Gates.
Design of Two-Level Circuits Using NAND and NOR Gates.
Design of Multi-Level NAND and NOR Gate Circuits.
Circuit Conversion Using Alternative Gate Symbols.
Design of Two-Level, Multiple-Output Circuits
Determination of Essential Prime Implicants for Multiple-Output
Realization.
Multiple-Output NAND and NOR Circuits.

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Multi-level NAND Circuits

Design procedure

1. simplify switching function

2. design a multi-level circuit of AND and OR gates
AND OR gates must alternate
Output gate must be OR
3. number the levels
starting with the output gate as level 1
4. replace all gates with NAND gates,
Interconnect unchanged
5. Invert inputs to level 1,3,5

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Example
Fig 7-13

F = a[b+c(d+e)+fg]+hij+k

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Validate the above procedure

Dividing the multi-level circuits into two-level subcircuits

Apply the previous results of two-level circuits to each two-level

subcircuits

Fig. 7-13
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Multi-level NOR Circuits

Similar procedure

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Outline

Multi-Level Gate Circuits.

NAND and NOR Gates.
Design of Two-Level Circuits Using NAND and NOR Gates.
Design of Multi-Level NAND and NOR Gate Circuits.
Circuit Conversion Using Alternative Gate Symbols.
Design of Two-Level, Multiple-Output Circuits
Determination of Essential Prime Implicants for Multiple-Output
Realization.
Multiple-Output NAND and NOR Circuits.

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Alternative Gate Symbols

Purpose: help to transform circuits in graphic way

Fig. 7-14

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NAND-NAND AND-OR
Fig 7-15

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OR-AND NOR-NOR
Fig 7-16

AND-OR alternate

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OR-AND NOR-NOR (contd)

Verify section 7.4
is correct

Fig. 7-16
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What if AND OR dont Alternate?

Still can convert AND OR circuits to NAND circuits

Additional inverters may be required

Procedure

1-1. convert all AND gates to NAND gates

by adding bubbles at gate output
1-2. convert all OR gates to NAND gates
By adding bubbles at gate inputs
2. If an inverted output drives inverted input, no further action
needed
Cancelled
3. If noninverted gate output drives inverted gate input or vice
versa,
Insert inverter
4. If variable drives inverted input, complement the variable

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Example (step 1)
Fig 7-17

Step 1: replace gates

(Thick lines mean inversion needed)

Two inversions

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Example (step 2,3)

Step 2: dont insert inverters to thin lines
Step 3: insert inverters to thick lines

Fig. 7-17
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Example (step 4)
Step 4: invert inputs if needed

Fig. 7-17
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Example (final answer)

Fig. 7-17

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Outline

Multi-Level Gate Circuits.

NAND and NOR Gates.
Design of Two-Level Circuits Using NAND and NOR Gates.
Design of Multi-Level NAND and NOR Gate Circuits.
Circuit Conversion Using Alternative Gate Symbols.
Design of Two-Level, Multiple-Output Circuits
Determination of Essential Prime Implicants for Multiple-Output
Realization.
Multiple-Output NAND and NOR Circuits.

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Multiple Output Circuits

Circuits with more than one output
Minimization of each output separately does not necessarily lead to
best overall solution

Example

Fig 7-18:

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F1 F3

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If Realized Independently
9 gates
21 gate inputs

Fig. 7-19
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If Optimized Together
7 gates
18 GI

Fig. 7-20

Not surprising

Sharing of common terms results in smaller hardware

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Another Example
Fig 7-21
Independent optimization: 10 gates 25 GI
Use common terms: 8 gates, 22 GI

Fig. 7-21

*colored loops are shared common terms

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Common Terms not Always Win!

Sharing common terms does not necessarily results in best solution
Example Fig. 7-23

Solution (B) No common terms results in better solution

Sometimes, team work is not more efficient

Unfortunately, no simple way to tell when to share common terms

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Outline

Multi-Level Gate Circuits.

NAND and NOR Gates.
Design of Two-Level Circuits Using NAND and NOR Gates.
Design of Multi-Level NAND and NOR Gate Circuits.
Circuit Conversion Using Alternative Gate Symbols.
Design of Two-Level, Multiple-Output Circuits
Determination of Essential Prime Implicants for Multiple-Output
Realization.
Multiple-Output NAND and NOR Circuits.

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Design Multiple output Logic

Similar to single output logic

Section 5.4

First step

Find essential Prime Implicants

Second step
Select remaining terms to form the minimum solution

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Review: Distinguished 1-cell

A minterm that is covered by only one prime implicant
example

m2 is distinguished 1-cell
m3 is not

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Review: Essential Prime Implicant

Definition

prime implicant that contains a distinguished 1-cell

Example
BC BD AC are EPI
CD is not
EPI MUST be included in minimum SOP

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Find EPI in Multiple output Logic

Be careful when finding EPI for multiple output logic

Some prime implicants essential to an individual function may

NOT be essential to the multiple output realization
Example: Fig 7-21
bd is essential PI for f1 only, Not for f2 or f3
So bd does not appear in solution 7-23b

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New Rule in Multiple Output Logic

Only check 1s which DO NOT appear on the other function maps
Example: Fig 7-23

m1 is distinguished for f2 abc is EPI for f2

m2 is distinguished for f1 ad is EPI for f1
m5 is distinguished for f1 abc EPI for f1
m12 is distinguished for f2 bd is EPI for f2
NOTE: m0 is NOT checked

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Another Example
Fig 7-22

m1 is distinguished cd EPI for f1

abd is not EPI because m15 shared by f1 and f2

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Outline

Multi-Level Gate Circuits.

NAND and NOR Gates.
Design of Two-Level Circuits Using NAND and NOR Gates.
Design of Multi-Level NAND and NOR Gate Circuits.
Circuit Conversion Using Alternative Gate Symbols.
Design of Two-Level, Multiple-Output Circuits
Determination of Essential Prime Implicants for Multiple-Output
Realization.
Multiple-Output NAND and NOR Circuits.

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Multiple Output Multiple Level

Similar to single output, multiple level

First find OR-AND or AND-OR

Then convert to all NOR or all NAND
Fig 7-24

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Example (contd)
Fig 7-24

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FFT
Q: Why NAND? Why NOR? They are not easy to understand.

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Why NAND? Why not AND?

In CMOS technology,

AND = NAND + NOT

OR = NOR + NOT
NAND NOR are small in area
NAND, NOR : 2 PMOS + 2NMOS
AND, OR: 3 PMOS+3NMOS
NAND NOR are faster than AND OR
NAND NOR: 1 gate delay
AND OR: 2 gate delay

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Next Time
ch 1 Introduction Number Systems
and Conversion
ch 2 Boolean Algebra
ch 3 Boolean Algebra (contd)
holiday no class
ch 4. Application of Boolean Algebra
ch 5 Karnaugh Maps
ch 7 Multi-Level Gate Circuits;
NAND NOR Gates
ch 8 Combinational Ckt Design
Midterm

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