Switching Circuits & Logic Design

Registers and Counters

Professor Chien-Mo James Li
Graduate Institute of Electronics Engineering
National Taiwan University
Logic Design

NTUEE C.M. Li

Objective of this Chapter

Introduce registers and counters

building blocks of sequential circuits

This chapter is VERY IMPORTANT!!

Logic Design

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Registers & Counters

Registers

A group of Flip-flops with a common clock input

Counters

A group of flip-flops which change states in a prescribed

sequence when input pulses are received

They are both useful elements in logic design

Logic Design

NTUEE C.M. Li

Outline

Registers and Register Transfers.

Shift Registers.
Design of Binary Counters.
Counters for Other Sequences.
Counter Design Using S-R and J-K Flip-Flops.
Derivation of Flip-Flop Input Equations.
Summary.

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4-bit D FF Registers
With data, load clear and clock inputs

ClrN = 0, all cleared to zero

Load =1, new values loaded
Fig. 12-1 (a) Use gated clock
Timing problem, not good

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Logic Design

4-bit D FF Register (2)

Fig 12-1 (b) A better implementation

Load=1, Clk enabled

Load=0, Clk disabled

Bus = a group of wires

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8-bit Register with Tri-state Output

When En =1, tri-state
When En=0, output = Q
Fig. 12-3

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Data Transfer Between Registers

Fig 12-2
When En=1 Load=1, Reg Q = Reg A, at postive clock edge
When En=0 Load=1, Reg Q = Reg B, at postive clock edge
When Load = 0, what happens?

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Data Transfer using Tri-state Bus

All register connected in parallel to common tri-state bus
Data transfer from Reg. A,B,C,D, to Reg G,H

Only one Register out of (A,B,C,D) drives the bus at a time

Two registers (G,H) can both receive data at a time

LdH

Fig. 12-4
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Decoder
Line decoder decodes input EF to four signals

EnA, EnB, EnC, EnD

Only one active (zero) at a time
One-hot signal
Only one bus driver is allowed
when
EF=00, Reg A stored in G (LdG=1) or H (LdH=1) or both
EF=01, Reg B stored in G (LdG=1) or H (LdH=1) or both
EF=10, Reg C stored in G (LdG=1) or H (LdH=1) or both
EF=11, Reg D stored in G (LdG=1) or H (LdH=1) or both

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Accumulator
Accumulator is a special register that

Stores one number

a second number can be added to it, leaving the result stored in
the same register
X(t+1) = X(t) + Y
Fig. 12-5

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Accumulator (2)
When Ad=1, ClrN=1, X=X+Y, at rising edge of CLK
When Ad=0, ClrN=1, X unchanged
When ClrN=0, X reset to zero

Fig. 12-5

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How to Load Accumulator?

Method 1:

ClrN=0, clear contents

ClrN=1, Ad=1, X =0+Y
Method 2: Insert MUX
Ld=1, X=Y
More hardware, save extra step of clearing Acc.

Fig. 12-6

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Iterative Structure
Iterative structure

A structure that consists of repeated identical small modules

(aka. Cells)
Example
Accumulator is iterative structure
Parallel adder also
Fig. 12-5

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Outline

Registers and Register Transfers.

Shift Registers.
Design of Binary Counters.
Counters for Other Sequences.
Counter Design Using S-R and J-K Flip-Flops.
Derivation of Flip-Flop Input Equations.
Summary.

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Shift Register
Shift register = register in which data can be stored and

shifted to left or right

Example
Right-shift register
When shift=1
Shift to right

Fig. 12-7
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8-bit Serial-In Serial-Out S.R.

SI = serial In
SO = Serial Out
Data shifting in register

Like pipeline
No access to internal bits until shifted out
Fig. 12-8

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Timing Diagram

Fig. 12-9

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Parallel-in Parallel-Out Right S. R.

Fig 12-10

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Logic Design

Operation
3 operations
Table 12-1

Input

Logic Design

Next

State

Action

Sh

Q3+

Q2+

Q1+

Q0+

Q3

Q2

Q1

Q0

No change

D3

D2

D1

D0

load

SI

Q3

Q2

Q1

Right shift

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Timing Diagram
SI keeps zero

Logic Design

Fig. 12-11

load

shift

shift

shift

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Next-State Equations
(12-1)

Q3+=
Q2+=
Q1+=
Q0+=

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Applications of Shift Registers

1. Multiplication and Division (see CH 18)

Shift right = number divided 2

Shift left = number times 2
2. Serial communication
Parallel data converted into serial data

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Shift Register with Feedback

Connect serial output to serial input

Called cyclic shift register

Cyclic Shift Register performs end-around shift

Example
Feedback shown by dashed lines
0111 1011 1101 1110 0111

Fig. 12-7

SR with feedback can produce fixed sequence of states

Counter

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Example: Johnson Counter

Fig 12-12

inverted feedback
6 states in a loop
2 states in another loop

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Outline
Registers and Register Transfers.
Shift Registers.
Design of Binary Counters.

Using D FF and T FF
Counters for Other Sequences.
Counter Design Using S-R and J-K Flip-Flops.
Derivation of Flip-Flop Input Equations.
Summary.

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Organization

*different from textbook

Two counter design; Four types of flip-flops

Two methods

Table method
Kmap method
Order of this lecture is different from textbook

D-FF

T-FF

SR-FF

JK-FF

Binary
counter

12.3

12.3

Selfdefined
counter

12.4

12.4

12.5

12.5

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Logic Design

Binary Counter
Count the number of clock pulses

Output sequence in the order of binary numbers

000->001 010011100101
State Table
TABLE 12-2
Present state

Logic Design

Next state

C+

B+

A+

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Binary Counter Using D-FF

Present state
C
B
A
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Next state
C+
B+
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0

A+
1
0
1
0
1
0
1
0

D-FF Inputs
DC
DB
DA
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0

Fig 12-16

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Input Equations

(12-2)
DA = A
DB = BA + BA = B XOR A
DC = CBA+CB+CA=C XOR (BA)

Changed
Fig 12-15

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Binary Counter Using T-FF

Present state
C
B
A
0
0
Table 12-2 0
0
0
1
0
1
0
TA= 1
0
1
1
1
0
0
TB=A
1
0
1
TC=AB
1
1
0
1
1
1

Next state
C+ B+
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0

A+
1
0
1
0
1
0
1
0

T-FF Inputs
TB
TA
TC
0
0
1
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1

Fig. 12-14

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Logic Design

Binary Counter Using T-FF

Double check

A toggles every clock

B toggles every two clocks
C toggles when A=B = 1

Present state
C
B
A
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Next state
C+ B+
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0

A+
1
0
1
0
1
0
1
0

Fig 12-13

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D-FF vs T-FF Binary Counters

T-FF = D-FF + XOR

TA= 1
TB=A
TC=AB

DA = A
DB = BA + BA = B XOR A
DC = CBA+CB+CA=C XOR (BA)

Fig 12-15

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Outline

Registers and Register Transfers.

Shift Registers.
Design of Binary Counters.
Self Defined Counters Design Using D-FF and T-FF
Counter Design Using S-R and J-K Flip-Flops.
Derivation of Flip-Flop Input Equations.
Summary.

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Organization

D-FF

T-FF

SR-FF

JK-FF

Binary
counter

12.3

12.3

Selfdefined
counter

12.4

12.4

12.5

12.5

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Logic Design

Counter Using D-FF

Step 1.

State Graph and State Table

Fig 12-21

Logic Design

Table 12-3

Present
state
C B A

Next state

C+ B+ A+ DC DB DA

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D-FF Inputs

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Step 2. Next-state Maps

Make K map of A+ B+ C+ from State table

Fig 12-22

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Step 3. Input Maps

Because Q+ = D

Input equation is the same as next state equation

Input map is the same as next state map

Fig 12-22

Next-state map = input map

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Step 4. Input Equations & Circuit

Input equations

Dc = B
DB = C+AB
DA = A(B+C)
Fig 12-26

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Logic Design

Counter Using T-FF

Same Example

Use T-FF
Step 1: state table

Fig 12-21

Logic Design

Table 12-3

Present
state
C B A

C+ B+ A+ TC

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Next state

T-FF Inputs
TB

TA

40

Step 2. & 3
K Map of Ta Tb Tc

When c+ not equal c, Tc=1

When c+ equal c, Tc=0
Fig 12-22

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Step 4.
Fig 12-23

TA=B+C

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K map method
Copy numbers in C=0 half, complement numbers in C=1 half
Fig 12-22

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Comparison for two Methods

Table method

State table input table input maps input equations

Slower but less error prone

K-Map method

Next-state map input maps input equations

Faster but error prone

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Timing Diagram

Fig. 12-24

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Outline

Registers and Register Transfers.

Shift Registers.
Design of Binary Counters.
Counters Design Using D-FF and T-FF
Counter Design Using S-R and J-K Flip-Flops.
Derivation of Flip-Flop Input Equations.
Summary.

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Organization

D-FF

T-FF

SR-FF

JK-FF

Binary
counter

12.3

12.3

Selfdefined
counter

12.4

12.4

12.5

12.5

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Logic Design

Counter Using SR-FF (table method)

Same Example

Use SR-FF
Step 1: state table
Table 12-5

Fig 12-21

Logic Design

Table 12-6

Present
state
C B A

Next state

C+ B+ A+ SC Rc

SB RB SA RA

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SR-FF Inputs

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Design Counter Using SR-FF

S

Q+

Q+

Q+

Table12-5 (b)

Table12-5 (c)

Table12-5 (a)

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Step 2 & 3
Next state Map
Input Map

Fig 12-27

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Step 4.
Counter using SR-FF

Fig 12-27

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FFT
Q1: Does the design obey the rule that S and R are never one at the

same time?
Q2: How do you guarantee this rule is never violated using our
design flow?

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K-Map Method (1)

First draw next state map

Fig 12-27

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Logic Design

K-Map Method (2)

For C=0 half

If C+=1, then S=1, R=0

If C+=0,then S=0, R=X

Logic Design

Fig 12-27

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K-map Method (3)

For C=1 half

If C+=1, S=X, R=0

If C+=0, S=0, R=1

Fig 12-27

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Logic Design

Counter Using JK-FF (table method)

Same Example
Table 12-8

Use JK-FF
Step1: state table
Table 12-7

Fig 12-21

Logic Design

Present
state
C B A

Next state

C+ B+ A+ JC

K c JB

KB

JA K A

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JK-FF Inputs

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Counter Using JK-FF

J
0
0
0
0
1
1
1
1

K
0
0
1
1
0
0
1
1

Table 12-7 (a)

Logic Design

Q
0
1
0
1
0
1
0
1

Q+

Q+

0
1
0
0
1
1
1
0

0
1
1

1
0
1

Table 12-7 (b)

Q+

Table 12-7 (c)

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K-map method
Fig 12-28

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Results

Fig 12-28
JA= B+C KA=1
JB= C
KB=AC
JC=B
KC=A

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Comparison of 4 Designs

TFF
DFF
SRFF
JKFF

More complex sequential circuits

Less complicated combinational circuits

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FFT:
why do we need so many FFs?

Which is better?

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Outline

Registers and Register Transfers.

Shift Registers.
Design of Binary Counters.
Counters for Other Sequences.
Counter Design Using S-R and J-K Flip-Flops.
Derivation of Flip-Flop Input Equations.
Summary.

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Summary
Table method

1. state table (PS, NS)

2. state table (input part)
3. input maps
4. input equations

Kmap method

1. state table (PS, NS)

2. next state maps
3. input maps
4. input equations

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Logic Design

Determine FF Input Eq. from NS Eq.

Table 12-9

Important !! Memorize this table

Q=0

Q=1

Q+=0

Q+=1

Q+=0

Q+=1

Table 12-9
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Example (1)

Fig. 12-22

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Example (2)
ABC are other inputs
Q is state

Fig 12-29

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Outline

Registers and Register Transfers.

Shift Registers.
Design of Binary Counters.
Counters for Other Sequences.
Counter Design Using S-R and J-K Flip-Flops.
Derivation of Flip-Flop Input Equations.
Summary.
Other Additional Topics
Up/down counter
Loadable counter
Incompletely specified states

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Logic Design

Up-Down Binary Counter

Count in both directions

U=Up, D=down
Fig 12-17
State Table

Fig 12-17

C+B+A+
CBA

U=1

D=1

000

001

111

001

010

000

010
011
100
101
110
111
101
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Next-State Equation

P. 365
DA=A+=A(U+D)
DB=B+=B(UA+DA)
DC=C+=C(UBA+DBA)
Fig 12-8

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Loadable Counter
Fig 12-19

Symbol
State Table

Fig 12-19

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Loadable Counter
Fig 12-20
Add highlighted gates to original binary counter

mux , AND

Fig 12-20

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Incompletely Specified States

Note: state 001 originally not specified

Incompletely specified state

Fig 12-25
Why 001 111?
Textbook p.340
Q: Why worried about 001?
When power up
Initial states unknown

Exercise:

show state graph is correct

Logic Design

Fig 12-25

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Next Time

ch 9 Multiplexers Decoders and PLD

ch 11 Latches and FF
ch 12 Registers and Counters
ch 13 Analysis of Clock Sequential Ckts
ch 14 Derivation of State Graphs and
Tables
ch 16 Sequential Ckt Design
ch 18 Ckts for Arith. Operations
final exam

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