Switching Circuits & Logic Design

Analysis of Clocked Sequential Circuits

Professor Chien-Mo James Li
Graduate Institute of Electronics Engineering
National Taiwan University
Logic Design

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Review
1. what are D-FF, T-FF, JK-FF?
2. please fill in the truth table

Q Q+ | D
Q Q+ | J K

3. draw the state table of a simple counter

Design using D-FF

Design using JK-FF

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Flow of Design a Sequential Ckt.

specification
Ch 14
State graph
State Table
Ch 12

Ch 13

K-map
FF, Comb Logic
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Objective of this Chapter

Analyze sequential circuits

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Outline

A Sequential Parity Checker.

Analysis by Signal Tracing and Timing Charts.
State Tables and Graphs.
General Models for Sequential Circuits.

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Parity
What is parity?

Total number of 1s in a sequence

Odd parity
Even parity
Example
Odd parity of 8 bits

Why parity?

Used for error checking in communication

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Block diagram of Parity Checker

Sequential parity checker

Z=1 when total number of 1 input received is odd

Fig. 13-1
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Waveforms
Assume: Negative edge triggered

Fig. 13-2

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State Graph
S0 = total number of 1 inputs received is even
S1 = total number of 1 inputs received is odd
More details later

Fig. 13-3

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State Table
Table 13-1

Design using TFF

Present
State

Next state

Present
Output (Z)

X=0

X=1

S0

S0

S1

S1

S1

S0

Tab. 13-3 (a)

Q+

X=0

X=1

X=0

X=1

Tab. 13-3 (b)

Fig. 13-4
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Outline

A Sequential Parity Checker.

Analysis by Signal Tracing and Timing Charts.
State Tables and Graphs.
General Models for Sequential Circuits.

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Signal Tracing
What is signal tracing?

Given a circuit, Given a sequence of inputs

Find
Circuit states
Circuit output sequences

How?

1. Assume initial state of FF

2. For first input, determine circuit output(s) and FF inputs
3. Determine new state of FF after the next active clock edge
See next slide
4. Repeat 2 ~ 4 for each input

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Moore vs. Mealy Sequential Circuit

Moore circuits (or Moore machines)

Output depends only on present state

Mealy circuits (or Mealy machines)

Output depends on BOTH present state and input

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Edward F. Moore (1925-2003, USA)

Edward F. Moore was a professor of mathematics and computer

sciences at the University of Wisconsin-Madison from 1966 until he

retired in 1985.
He was a pioneer of Automata theory and introduced what are now
know as Moore machines, named after him. He also invented a well
known algorithm for finding the minimum state equivalent Finite
Automaton.
His Gedanken (thought) paper , which appeared in the Annals of
Mathematics in 1956 together with his work on switching theory and
logic, initiated a vigorous research area. He proposed an elegant
form of a universal Turing machine at a time when few people had a
good grasp of the meaning of Turing machines as models of
computers.
Animals and plants can reproduce themselves, but it was only recently shown
that machines can be made which also reproduce themselves. Other kinds
of self-reproducing machines will be described, and one simple mechanical
model, with no electrical or magnetic complications, will be there in working
order for the audience to inspect and operate.
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Example Moore Circuit

Output depends only on present state
Fig 13-5

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Timing Chart

Fig. 13-6
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G. H. Mealy (?, USA)

G. H. Mealy, a state machine pioneer, who wrote A Method for
Synthesizing Sequential Circuits, Bell System Tech. J. vol 34, pp.
10451079, September 1955.

Mealy machines provide a rudimentary mathematical model for

cipher machines. Considering the input and output alphabet the
Latin alphabet, for example, then a mealy machine can be designed
that given a string of letters (a sequence of inputs), it can process it
into a ciphered string (a sequence of outputs). However, although
you could probably use a Mealy model to describe Enigma, the state
diagram would be too complex to provide feasible means of
designing complex ciphering machines.

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Example Mealy Circuit

Output depends on BOTH present state and input

Fig. 13-7

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Timing Chart

Fig. 13-8
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False Output
What is false output?

After changes state and

before inputs change
The output may temporarily assume as incorrect value
Why?
Old input + new state
Produce false output
Also known as (AKA)
Glitches or spikes
Only Mealy circuits have false outputs
Output of Mealy machine is trustable only immediately before
active clock edge
Q: why Moore machine has no false output?

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False Output (2)

False output in parenthesis

X=1

A=0 0
B=0 1
Z=1 (0) 1

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0
1
1
1
0 (1) 0

1
1
1

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0
0

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FFT
Q: Since Mealy circuits have false outputs, why do we need Mealy?

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Outline

A Sequential Parity Checker.

Analysis by Signal Tracing and Timing Charts.
State Tables and Graphs.
General Models for Sequential Circuits.

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State Table and State Graph

Signal tracing is too slow

Need systematic way to analyze sequential circuits

State table

The table that describe the relationship of the present state and
next state
Of course the output can also be described
Aka transition table

State Graph

The graph that describe the relationship of the present state and
next state

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Steps to Analyze Circuits

1. initial state

Input equations, output equations

2 next-state equation
3. next-state map
4. state table
5. state graph

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Review
Characteristic equations (CH 11)

Memorize them, very important!!

Q+ = S + RQ (SR=0)
Q+ = GD + GQ
Q+ = D
Q+ = DCE + Q CE
Q+ = JQ + KQ
Q+ = T Q = TQ + TQ

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(S-R latch or flip-flop )

(gated D latch )
(D flip-flop )
(D-CE flip-flop )
(J-K flip-flop )
(T flip-flop )

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(13-1)
(13-2)
(13-3)
(13-4)
(13-5)
(13-6)

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Moore Example
Fig 13-5

1. input equations DA=

output equation Z=
2. next-state equations A+=
3. Next-state map

DB =
B+=

Fig 13-5

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4. State Table
State Table 13-2(b)

Transition Table 13-2(a)

AB
X=0

A+ B+
X=1

00=S0, 01=S1
11=S3,10=S3

PS
X=0

NS
X=1

00

10

01

S0

S3

S1

01

00

11

S1

S0

S2

11

01

11

S2

S1

S2

10

11

01

S3

S2

S1

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5. State graph
TABLE 13-2 (b)
Fig 13-9

PS

NS

X=0

X=1

S0

S3

S1

S1

S0

S2

S2

S1

S2

S3

S2

S1

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Mealy Example
1. input equation

JA=
JB=

KA=
KB=

2. next-state equation

A +=
B +=

output equation
Z=

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Fig. 13-10

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 3. next-state map

Output map

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4. State Table
State Table 13-3 (b)

Transition Table 13-3 (a)

A+ B+

AB

X=0

X=1

Z
X=0 =1

S0

S0

S1

S1

S1

S2

S2

S2

S0

S3

S3

S1

X=0

X=1

Z
X=0 =1

00

00

01

01

01

11

11

11

00

10

10

01

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PS

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NS

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5. State Graph
Fig 13-11

PS

NS
X=0

X=1

Z
X=0 =1

S0

S0

S1

S1

S1

S2

S2

S2

S0

S3

S3

S1

X
Z

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Compare State Table

Moore

Mealy

PS
X=0

NS
X=1

PS

NS
X=0

X=1

Z
X=0 =1

S0

S3

S1

S0

S0

S1

S1

S0

S2

S1

S1

S2

S2

S1

S2

S2

S2

S0

S3

S2

S1

S3

S3

S1

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Compare State Graph

Moore

Mealy

X
X

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Serial Adder Example

What is serial adder?

X=Xn-1 x1x0 Y=yn-1y1y0

Binary numbers are fed in serially, one pair of bits at a time
Subscript represents clock cycle index

Fig. 13-12
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Parallel Adder
Fig 4-3
All inputs are fed simultaneously in parallel

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State Table
Fig 13-12 (b)

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xi

yi

ci

ci+1

si

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Timing Chart
Aka. timing diagram

Fig. 13-13

Immediately before clock edge

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State Graph
xi yi / si

w/ carry

w/o carry

Fig. 13-14
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4-state example
TABLE 13-4
Present
State

Next State
X1X2
=00

01

10

S0

S3

S2

S1

S0

S2
S3

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Present Output(Z1Z2)

11

X1X2
=00

01

10

11

S1

S0

00

10

11

01

S1

S2

S3

10

10

11

11

S3

S0

S1

S1

00

10

11

01

S2

S2

S1

S0

00

00

01

01

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4-state example

Fig. 13-15
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FFT
When do you need serial adders?

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Outline

A Sequential Parity Checker.

Analysis by Signal Tracing and Timing Charts.
State Tables and Graphs.
General Models for Sequential Circuits.

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General Models for Mealy Circuits

m inputs, X1 Xm
n outputs, Z1 .. Zn
K FFs, Q1 ,, Qk

f(X, Q)

Z = f(X, Q) output
Q+ = g(X, Q) next state

g(X, Q)

Fig. 13-17
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General Models for Moore Circuits

m inputs, X1 Xm
n outputs, Z1 .. Zn
K FFs, Q1 Qk

Z = f(Q) output function, also (S)

Q+ = g(X, Q) next state function, also (S, X)

g(X,Q)

f(Q)

Fig. 13-19
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Comparison
Moore Circuits

Electronic Alarm clock

Mealy Circuits
Traditional alarm clock

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Review, CH11
Setup time (tsu)

time that D must be stable before the active edge of clock

Propagation time (tp)
time from clock changes until output Q changes
Combinational Circuit Delay (tc) was called td in CH11
time to propagate through combinational logic gate (no clock)

Fig. 11-16

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 CH 11

Tclk, min = Tp+Tc+Tsu

CH13, Now with Mealy

Tclk, min = Tx+Tc+Tsu

Tx means delay of input

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Outline

A Sequential Parity Checker.

Analysis by Signal Tracing and Timing Charts.
State Tables and Graphs.
General Models for Sequential Circuits.

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Construction of Timing Charts

P 406
1. state change occurs AFTER active clock edge
2. input stable immediately BEFORE and AFTER active clock edge
3. Moore: output change only when state change
Mealy: output change whenever input change
4. Mealy has false outputs
5. How to use state table to draw Mealy outputs?
a. Draw Present State (PS)
b. Draw Next State (NS)
c. Use NS and OLD input to draw false output
d. Use NS and NEW input to draw real output
6. Mealy: read output just BEFORE active edge

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This is a

simplified
version of Fig
13-6
ABD
B is new state +
old input
D is new state +
new input

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New state

New state

Old input

New input

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 Continued from

last figure
X changes
at time C
ABCD

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Continued from

last figure
DEF

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 Apply input

right before
clock edges
X=010
Observe output
right before
clock edges
Z=110

0
1

1
1

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0
0
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Next Time
ch 9 Multiplexers Decoders and PLD
ch 11 Latches and FF
ch 12 Registers and Counters
ch 13 Analysis of Clock Sequential Ckts
ch 14 Derivation of State Graphs and
Tables
ch 16 Sequential Ckt Design
ch 18 Ckts for Arith. Operations
final exam

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