Introductory Digital Design Lab

An Opportunity for Experience

Abstract

The purpose of this paper is to examine the emphasis placed on practical lab experience by Eastern
Washington University's Electrical Engineering and Computer Engineering Technology programs. The
paper analyzes a two-course core program requirement in digital logic, focusing primarily on the
experience that students gain in elementary digital circuit design upon completing the course lab section.
The paper defines the prerequisites of the course and its final expectations. It further focuses on the final
project of the course, which exemplifies the knowledge required to successfully design and implement a
functioning circuit. Finally, the results of the final project and its functionality are shown.

Introduction

Eastern Washington University is a small regional institution located in Cheney, Washington. As part of it's
expanding engineering curriculum, students in Electrical Engineering, Computer Engineering Technology,
and Electronics Technology programs are required to take a two-course series in digital logic. The first
course, Engr 160, provides an introduction to basic concepts in digital design. Students gain practical
experience with digital hardware in the laboratory oriented continuation of the sequence, Engr 250. By the
completion of this series, students are expected to be able to both design and implement combinational and
sequential digital circuits using standard components such as flip-flops, multiplexers, decoders, shift
registers, and counters. Several projects are assigned, the culmination of which is a design challenge which
must be solved using only discrete transistor-to-transistor logic (TTL) components.

Class periods for the lab course are given once a week throughout the duration of the school quarter, with
an hour of instruction preceding most labs. Weekly assignments are posted online in advance to give
students time to prepare ideas before meeting with their lab partners for actual design. All assignments in
the class require that students work in small groups of three to five individuals to prepare and implement
their circuit designs. A weekly assignment is considered complete only after an informal report is written to
present the logic and reasoning behind the circuit and the process used to create a functioning device.

A large percentage of the course grade is divided among two major projects, a midterm and a final, which
both require a significant amount of time and effort to implement. In order to successfully complete the
projects, students must work together to create a solution using knowledge they have gained from the class.
The projects not only provide experience in design, but challenge the students’ problem solving abilities
and teamwork skills. While both projects are analogous in process and application, the final project is more
complex in certain aspects, chosen as a final test of the students’ knowledge. Students are given a set of
criteria for their final project, and are allotted the last three class periods to build and test it. They are then
required to create a formal report covering in detail each aspect of their project including teamwork
efficiency, design process and theory, and circuit schematics and function derivations.

This paper follows the experience of a group of five students who completed a final project assigned by
EWU instructor Esteban Marek-Rodriguez in the Winter Quarter of 2006. This project is chosen in an
effort to illustrate the benefit of reinforcing elementary knowledge in digital design through a laboratory
environment.

Project Overview

Group Members: David Freiberger, Andrew Livengood, Tyler Spence, James Wilson, Adam Zinnecker.

The design of any logic circuit beyond a minimal number of operations is challenging when restricted to
TTL component technology. Students in Engr 250 are allowed to choose their method of implementation,
provided it is feasible and does not use programmable gate arrays or other components with programmable
memory storage capabilities. Thus the project outlined below makes use of multiple components, many of
which had not been used by the students beforehand.

Assignment:

• Design and construct a “smart” traffic light signal that meets the following specifications:
• The circuit controls a light at a busy intersection of a main street and a (seldom used) side street.
• The main street is to have a green light for a minimum of 15 seconds, or as long as there is no
vehicle waiting at the side street.
• The side street light remains green for a maximum of 15 seconds, or until there are no more
vehicles waiting.
• A 4-second yellow light transitions between green and red for each street.
• Pushbuttons are to be used to model sensors, outputting a 1 when a car is waiting or a 0 otherwise.

The following features may also be implemented for additional credit:

• Include two seven segment displays to indicate the amount of time a car waits.
• Add a sensor on the main street to override the side street sensor and initiate a light change as long
as the side street light has been green for at least 10 seconds.
• Increasing the difficulty of the design, make both streets two-way, and include left turn signals in
the design.

Student Design Approach

It is optimal to design a project in stages, beginning with a plan or outline, continuing with a draft and
computer simulations, and finally creating a bread-boarded circuit for debugging and analysis. Students
should attempt to work as a team, equally dividing the project among members, and carefully employing
the strengths of each member.

It was decided to attempt a similar approach on this project, and as a first step an entire class period was
spent discussing the pros and cons of each team members’ ideas, illustrating those ideas to each other, and
finally narrowing them down to three related methods of implementation. It quickly became apparent that
the greatest challenge of the project would be to implement turn-signal indicators into the design, an extra
credit feature provided for an additional challenge. It was assumed that the indicators must be connected to
an extra set of turn sensors which would activate a separate set of lights to allow a lane of turning traffic
through the intersection. While seemingly a simplistic idea, the fact that this turn signal would introduce
several extra variables into the design presented a major problem.

The first of the designs considered was a sequential logic circuit utilizing three sensor inputs and reduced
state equations to create seven distinct light states. This type of circuit would allow for all of the features of
the project to be implemented, including the turn signal indicator. It was determined that there would be a
minimum of 8 variables for the flip-flop state equations. While it is possible to derive functions for over
five variables using the Kline-McClusky mapping technique, because of the large number of gates
necessary to implement eight variable state functions for each flip-flop in the design, it is not feasible to
utilize only non-programmable TTL components.

The next possible design was based upon a counter IC. Using inputs from the sensors, timer IC’s, and
combinational logic, the design bypassed much of the complexity of the sequential logic circuit. However,
this approach did not suggest an easy method for implementing the turn signal indicators without limiting
their functions to a narrow set of situations.

The final design proposition was to use a universal shift register (USR) to control the light circuit. By
connecting a specific light condition to each output of the shift register, and initiating data shifts resulting
from a series of logic gates monitoring the state of the sensors and outside counters, it was suggested that
the design was feasible. It was also deemed a possibility to use the parallel loading capabilities of a USR in
order to “skip” through light states and successfully implement an intelligent turn signal indicator into the
design. The major drawback to this method was the possibility of being forced to implement a large loop of
small combinational circuits in order to keep track of the current state of the USR and switch it to the next
proper state.

After all three proposed design were considered, a decision was made for each member to independently
evaluate their proposed designs. Upon reconvening it was decided to omit the turn signal indicator in the
project design, and to follow a relatively straight-forward approach centered around shift registers and
counter chips.

From the planning process alone, much was learned about working together in teams and collaborating
together. By spending extra time in the planning process, the student group was able to add their ideas
together to create a draft which would more than fulfill the project’s specifications. The draft was then
analyzed and functions were synthesized from spreadsheet truth tables into simulation software.

Project Design

Design Layout
The project was designed using a modular block approach, breaking the circuit into three distinct units of
operation, each fully capable of operating as standalone units for testing and analysis purposes. Each unit
was fully described in a data spreadsheet, consisting of a truth-table with the following I/O conditions:
• • a set of unique conditional inputs;
• • a set of state-describing inputs connected to specific outputs of the other two units; and
• a set of outputs acting as state-describing outputs or as external outputs to other parts of the
circuit.

The unique conditional inputs are inputs that depend on environmental variables, in this case the street
sensor switches. The state-describing inputs and corresponding outputs (from other units) act to tell each
unit what the other units are doing. For example, a wait-time counter that displays how long a car has been
waiting must begin counting if the street sensors and the present signal light state meet a specific set of
conditions. The external outputs act as either pulse signals lasting one clock cycle or as graphical outputs to
visual displays. For example the wait-time counter IC is triggered by a positive-edge pulsed signal from the
wait-time counter unit, thus changing through combinational logic a continuous output into a seven-
segment display driver.

The basic reasoning behind the modular block approach is to simplify wiring of the circuit and final
debugging. For this circuit, three modular units were conceptually created to be combined together to
implement the whole project. The purpose of the Signal Processing Unit (SPU) was to interpret data from
the street sensors, the present state of the lights, and how long the street signal light had been active. The
SPU was then to output a single signal pulse to the Signal Display Unit (SDU), which would switch to the
next street-light state in a continuous sequence. Depending on the state of the SPU and SDU, the Wait-
Time Unit (WTU) displayed how long a car had been waiting for either signal. Each individual module is
described next.

Unit 1. Signal Processing Unit

The core processor of the entire circuit was built to meet the following I/O specifications:

1) Two conditional inputs, Tx and Ty, should indicate how long a light has been in any one state.
These inputs were connected to a timer circuit consisting of a counter IC and two multiplexer IC’s.
The counter used was a 74163 synchronous-reset 4bit binary counter IC with parallel-loading
capabilities. To reduce the number of variables indicating how long the timer had been running,
the four outputs of counter chip were multiplexed through two 74151 8x1 MUX chips to give
 outputs indicating a range of time values.

2) Two state-describing signals, Mp and Sp, should indicate the present state of the street signal
light.
These inputs are directly connected to present-state indicator outputs from the SDU, and are
described in a later section.
3) Two conditional inputs, Ms and Ss, should indicate the state that the street sensors are in.
These inputs are connected to two street sensors, which in this circuit consisted of de-bounced
toggle switches (SPDT switch and flip-flop).
4) A single pulse output, J, should exist for one clock cycle when the lights should change state.
This output is based upon a function comprised of the previous six inputs, and was derived from a
truth table and implemented with two 16x1 74150 MUX’s wired together and reduced to form a
single 64x1 multiplexing unit capable of handling the six input variables.

The MUX’s were connected together by wiring the most significant bit Tx of the input function through an
inverter so that one MUX chip was enabled when the other one was disabled, thus forming a six-variable
function implementation.
The outputs of both MUX’s were then AND’ed together to provide the single output bit, J.

Unit 2. Signal Display Unit

The SDU's primary purpose was to drive a series of LED's representing stop-light signal indicators. The
concept behind the unit was to assign a distinct state indexed by two bits for each LED based on a
corresponding function wired to that LED. Four states are enough to indicate all possible conditions.
These states are shown in Table [##]. Since only four states were necessary for the LED's, two bits were
adequate for indicating each state. Each state represented the on/off condition of six LED's, two each of
red, yellow, and green, the purpose of which was to indicate what street was "GO" and what street was
"STOP," simulating the common traffic light layout. The state functions were designed to select the next
state in a looping sequence, based on the two-bit increment count sequence.
To illustrate the logic, suppose that the initial state of two bits, called X and Y, is 0 0. The 00 state then
corresponds to a green light for the main street and a red light for the side street, and so the functions of the
green LED for main street and red LED for side street are both outputting a high voltage level, or 1, while
all other LED's are outputting low. If then the XY bits are incremented by one binary count to 0 1, the
light's will switch to yellow- red, as indicated by the table. To produce the incremented count, the two state
inputs were wired directly to the two least significant bits of a 74163 counter. Thus when the counter
received a clock pulse, J, it would increment its count and correctly change the state of the stop lights.

The clock pulse of the counter in this circuit was wired to the output, J, of the signal processing unit
multiplexer, and thus performed the correct state change operations. The outputs of the LED lights were
also connected initially as inputs to two multiplexers whose' function was to output the present state of the
LED lights, the state-describing inputs, Mp and Sp, to the signal processor. After developing this part of the
circuit, it was realized that it would be more efficient to simply wire the state describing inputs to the same
outputs of the counter IC as the LED functions were connected to. Because of time restrictions however,
the circuit was left as built.

Unit 3. Special Design Feature: Wait Time Counter

The wait time counter was built as an optional feature of the project, and was to count how long any car
had been waiting for a red light. Since only sensors detecting a car at a red light should activate the counter,
a simple function, as diagramed above, was implemented to enable the counter part of the circuit based on
the sensors and present state of the lights. The counter was to have a maximum value of 14 or 15 seconds at
any count before resetting to zero because of SPU's functions, and it was to always reset to zero when a
change of light state occurred or sensors changed status.

Because of differences in available counters and changes to other parts of the circuit, the final design of
Unit 3 only partly resembled the circuit originally simulated and outlined in this document. The actual
implementation followed in concept with this circuit, but a simpler implementation using XOR gates was
developed. For the timer-output displays, two standard 7447 BCD-to-seven-segment decoder ICs were used
in cathode arrangements with cathode seven-segment LED displays.

While this unit was simulated with expected results in Multisim, because of the changes in design of the
final circuit, and because of synchronization issues that were not fixed due to time constraints, this unit
only partly functioned. In post-review of the project it was decided that the errors in counting due to
erroneous initial counter values might have been fixed by simply making the two sensor switches act on the
common clock pulse and thus synchronize their value changes with the rest of the circuits.
 Application and Troubleshooting

Using a modular approach to circuit construction , the group built and tested each individual system, and
subsystem of the circuit, ensuring that the output from each coincided with the input to the next stage.
During the construction process, the greatest learning experiences came from unforeseen circumstances.

The circuit was originally designed and tested in Multisim, a popular circuit simulation program with a rich
set of available components. When the group began constructing the circuit, certain components used in the
design were unavailable in the laboratory, and could not be obtained within the time frame necessary to
complete the project. The 75160 and 74169 counter IC's were replaced with the 74163 model. It was also
necessary to replace the 74152 8 x 1 multiplexers with the 74151 component. This unforeseen component
change forced the team members to reconfigure the circuit "on-the-fly" in order for the circuit to function
correctly.

Because of the separation of units, an error was introduced into the circuit that was never fully corrected. It
was only realized afterwards that synchronization of all inputs into the circuit was necessary, including
using debounced toggle switches for the sensors and latches to control the timing of signals between units.
While simulations of the circuit worked completely, certain aspects of the final circuit did not. Although
reasons for this were not immediately apparent, the two main discrepancies were due to a lack of identical
parts and the groups’ unfamiliarity with circuit simulation software. The most challenging difference in
parts were the asynchronous-reset counter chips, which were replaced with synchronous-reset counters.
Because it was not realized until later that the circuit needed to be synchronous, the signal that the
simulated counters were receiving would last only a very brief pulse between the units, before
combinational circuitry would cause the SPU to return it’s output to zero. This brief pulse was too short to
reset the main counter of the circuit which depended on its reset signal to know how long to hold a light in
one state. The other discrepancy that caused ambiguity in results was due to the groups’ inexperience in
circuit simulation software. None of the team members had used Multisim for digital logic testing, and it
was not realized that alternate settings must be applied when physical component limitations are to be
considered in simulations, instead of running the circuit in the fast “ideal” mode.

The finished project functioned correctly with the exception of sporadic counting errors in the SPU and
wait time counter due to the unknown timing problems mentioned above. It was however a successful
project in that all the base requires worked as required, and all other features that were attempted work to at
least some extent most of the time. The real success of the project however was the experienced gained by
each team member, not only in digital logic, but in teamwork, organization, presentation, and
communication.

Materials
Preliminary Design
2 - 74150 16 x 1 Multiplexer ICs
2 - 7404 NOT Gate ICs
2 - 74160 Synchronous 4-bit Counter ICs (replaced with 74163)
1 - 74169 Synchronous 4-bit Counter IC (replaced with 74163)
1 - 7408 Quad 2-Input AND Gate IC
1 - 7400 Quad 2-Input NAND Gate IC
1 - 74139 2 x 4 Decoder IC
1 - 74153 8 x 1 Multiplexer IC
2 - 74152 8 x 1 Multiplexer IC (replaced with 74151)
1 - 7432 Quad input OR Gate
6- Assorted LEDs
6 - 470W Resistors
2- Seven Segment Display Units
Final Design Additions*
1 - 7474 D Flip Flop
1 - 74151 8 x 1 Multiplexer IC
1 - 7432 OR Gate IC

*The final design replaced all counters with similar devices, requiring a few minor changes in the original
circuit. Extra chips that implemented those correctional functions not in the original design are listed here.

Conclusion and Results

This paper described the design theory and process behind a final project as built by collaborating students
in the lab section of a introductory digital design class at Eastern Washington University. It presented the
methodology behind the preparation for the project, and then proceeded to summarize the basic elements of
the project. It further showed how adding a degree of complexity to a basic laboratory class encourages
students to think outside the textbook and work together to find better solutions.

The practical experience gained from this project proved to be an effective introduction to the sort of design
challenges engineers must address daily. From process to product, the greatest learning experience was a
result of difficulty rather than success. Tasks in this project that appear simple on the surface proved to be
more complex upon further investigation. Conversely, the aspects with the greatest complexity became
manageable when broken into smaller functional components operating within the symbiotic environment
of the circuit.

Basic digital logic provides a foundation for many advanced topics. Real-world design challenges stimulate
interest and enhance the overall understanding of subject matter. They prove ideal not only in a digital
design series, but across engineering education.