IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO.

1, JANUARY 2012

473

Analysis, Design and Experimental Results of Wide

Range ZVS Active-Clamped L-L Type Current-Fed
DC/DC Converter for Fuel Cells to Utility Interface
Akshay K. Rathore, Member, IEEE, Ashoka K. S. Bhat, Fellow, IEEE, and Ramesh Oruganti, Senior Member, IEEE

AbstractA wide range zero-voltage switching (ZVS) activeclamped L-L type current-fed isolated dcdc converter is proposed for fuel cells to utility interface application. The proposed
converter maintains ZVS of all switches from full load down to
very light load condition for wide input voltage variation. Detailed
operation, analysis, design, simulation and experimental results
for the proposed converter are presented. The auxiliary active
clamping circuit absorbs the turn-off voltage spike and also assists in achieving ZVS of main switches. The ZVS of auxiliary
switches and main switches is achieved by the energy stored in the
boost inductors and series inductor (aided by parallel inductor),
respectively. Rectifier diodes operate with zero-current switching.
An experimental converter rated at 200 W has been designed,
built and tested in the laboratory to verify the analysis, design and
performance of the proposed converter for wide variations in input
voltage and load.
Index TermsFuel cells, high-frequency dc/dc converter,
renewable energy systems, zero voltage switching (ZVS).

I. I NTRODUCTION

INCE THE conversion of renewable energy sources into

useful ac or dc power has been of increasing importance
due to the environmental and global energy requirements, the
design and development of low-cost, high-efficient and smallsize power conversion systems is still a subject of research.
Even though solar and wind energy is available and free of cost,
they are subjected to weather conditions. Therefore, fuel cells
are seen as potential source of energy because they provide
continuous power in all seasons as long as the continuity of
fuel supply is maintained and that there is production of thermal
power in addition to the electrical power that can be used for cogeneration/heating and thus increases the overall efficiency of
power conversion system. Fuel cells to utility interfaced inverter
for residential power is an important application and is reported
in literature. A high-frequency (HF) transformer isolated dcdc
converter is part of a fuel cell power generation system [1][16]
to boost the low fuel cell stack voltage to higher than the peak of
Manuscript received April 8, 2010; revised January 17, 2011; accepted
March 3, 2011. Date of publication April 21, 2011; date of current version
October 4, 2011. This work was supported by a Grant from Natural Sciences
and Engineering Research Council (NSERC) of Canada.
A. K. Rathore and R. Oruganti are with the Department of Electrical and
Computer Engineering, National University of Singapore, Singapore 117576
(e-mail: eleakr@nus.edu.sg; eleramsh@nus.edu.sg).
A. K. S. Bhat is with the Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC V8W 3P6, Canada (e-mail:
bhat@ece.uvic.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2011.2146214

the utility line voltage with necessary isolation. Soft-switching

is necessary to operate the converter at HF and to realize smallsize, lightweight and low-cost converter. Many dcdc converter
topologies have been presented for this application [1][24]
but none of them is able to maintain soft-switching over the
complete load variation and entire operating range of fuelcell voltage changes caused by change in fuel flow and fuel
cell stack temperature. Converter presented in [18] is hardswitched and two devices are connected in parallel to improve
the efficiency. Switching frequency is 50 kHz. Current-fed fullbridge converter reported in [19] is a hard-switched converter
and therefore operated at 10 kHz, which increases the size of
magnetics/filters and therefore, of the converter. Full bridge
voltage-fed converter has several problems: rectifier diode ringing, duty cycle loss, snubber across secondary, pulsating current
at input increases filter size, and limited zero-voltage switching
(ZVS) range [20]. Many extra components are used to achieve
ZVS in [21] that is not a simple topology and exhibits lower
efficiency. A topology similar to [2] is presented in [22], but
secondary side switches lose ZVS at light load and higher input
voltage, the ZVS range is calculated in [13]. A non-isolated
bidirectional converter with active-clamping has been proposed
[23] for ZVS up to 40% load but operation with wide input
voltage variation is not reported. A solution to achieve ZVS
using many extra components is given in [24] but ZVS range is
not mentioned.
A comparison of soft-switched dcdc converters for fuel
cells to utility interface is given in [13] and it was shown
that a two-inductor current-fed isolated dcdc converter [17],
[25][30] is suitable for such applications. However, the major
limitations of such converters are hard switching and switch
turn-off voltage spike [16], [17], [25][27]. An active clamping
[31][33] based ZVS configuration was proposed [5], [12],
analyzed and designed in [12][14], [16]. Active-clamp snubs
the voltage turn-off spike and aids in ZVS of HF switches
but cannot maintain ZVS for the wide operating range of load
and input voltage. Variable frequency switching approach is
considered in [34] to obtain ZVS requires a large variation in
switching frequency for wide variation in input voltage.
None of the topologies available in the literature is able to
maintain ZVS over the entire operating range based on the fuel
cell voltage specifications. To achieve ZVS for wide variation
in input voltage and load while maintaining high efficiency has
been a challenge, especially for low-voltage and higher current
input applications. This paper introduces a design as a solution
to cover ZVS over this wide operating range. In this paper,

0278-0046/$26.00 2011 IEEE

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 1, JANUARY 2012

Fig. 1. Active-clamped L-L type ZVS current-fed dcdc converter.

an L-L type active-clamped current-fed converter, shown in

Fig. 1, is proposed. This is a modified active-clamped currentfed converter [12][14], [16] by connecting an extra inductor in
parallel to the transformer secondary. Based on a comparison
of HF isolated fuel cells to utility interface schemes, a dc-to-dc
converter followed by a current controlled inverter was selected
[35], [36]. The proposed converter satisfies the front-end dcto-dc converter requirements for this application due to the
following reasons. 1) This two-inductor current-fed converter
comprises dual boost converter, therefore higher boost ratio
is obtained and the required voltage translation is achieved
with lower HF transformer turns ratio. 2) Input current in a
current-fed converter is dc whereas in voltage fed converters
it is pulsating, requiring a larger filter size to avoid the ripple
current being reflected to the fuel cells. 3) The fuel cell exhibits
very wide variation in voltage and hence in the output power
depending on the fuel flow, fuel cell stack temperature, etc.
Achieving soft-switching for the entire operating range of such
a wide variation of load and input voltage is a challenge
while maintaining higher efficiency, especially for low input
(2241 V), high output (350 V) voltage specifications. The
present converter maintains soft-switching for this entire operating range and maintains higher efficiency. The front-end
converter efficiency is a major factor in deciding the overall
efficiency of the fuel cell to utility interface power conditioning
unit as it deals with higher currents and therefore higher losses.
4) For the specifications of the present application, a single-cell
of this converter can be realized for higher power than voltagefed PWM and resonant converters as in the latter, it is difficult
to realize the very low design value and low HF transformer
leakage inductance [13]. 5) Input current ripple frequency is
twice the switching frequency. 6) Lower conduction losses
in switches due to two inductor topology (current divider) as
compared to current-fed full-bridge converter topology resulting in higher efficiency. 7) The rectifier diodes operate with
zero-current switching (ZCS). Also, the converter is free from
the problem of duty cycle loss and diode voltage is clamped
at output voltage thus avoiding the lossy snubber required to
eliminate rectifier diode stress/ringing required in converters
with inductive-filter.
The current carried by the parallel inductor is less than 2.5%
of the input current. Therefore, power loss is considerably
small. Also, this is a small-size inductor. If the value of Lp
is completely obtained by magnetizing inductance Lm of the
HF transformer, still the proposed design and derived analytical
equations are valid. It will provide the values of Ls and Lm
to maintain zero-voltage switching over the entire operating

range of fuel cell voltage and output power. This paper proposes
a design with only a slight modification instead of involving
several extra active and/or passive components. This way it is
still able to maintain high efficiency. It should be noted that
the addition of an extra parallel inductor makes the transformer
leakage or series inductor current continuous and also increases
the number of state variables. Therefore, the operation, analysis
and design get modified due to the third state variable and this
was completely neglected in the earlier analysis and design.
Due to imperfect ratio of Ls /Lm than the desired design value
(given in the design section), an extra small-size inductor Lp
is added in our experimental converter used for verification of
analysis in our lab. In a practical industrial converter, one can
control the magnetizing inductance value close to the required
parallel inductance to avoid the use of external inductance.
Also, slight changes in this value should not affect the performance too much as far as the ZVS condition discussed in the
design section is satisfied.
The objectives of this paper are to present the operation,
steady-state analysis, design, simulation and experimental results of this converter. The layout of the paper is as follows:
Detailed operation and analysis during different intervals of
operation of the proposed topology are given in Section II.
A complete design procedure illustrated by design example
of a 200 W converter is presented in Section III. Simulation
results using PSIM 6.0.1 for the designed 200 W converter are
presented in Section IV to verify the analysis. An experimental
converter rated at 200 W has also been built and tested in the
laboratory to verify the analysis and to test the performance of
the proposed converter for wide variations in input voltage and
load. Experimental results obtained are given in Section IV.
Analytical, simulation and experimental results are compared
at different operating conditions of load and input voltage.
II. O PERATION AND A NALYSIS OF THE C ONVERTER
The following assumptions are made for the operation and
analysis of the converter: a) Boost inductors L1 and L2 are
assumed large so that the current through them can be considered constant. b) Clamp capacitor Ca is assumed large to
maintain constant voltage across it. c) All switches and diodes
are assumed ideal. d) Series inductor Ls includes the leakage
inductance of the transformer. e) Magnetizing inductance of the
HF transformer is a part of parallel inductance Lp .
Here, L-L type denotes the series inductance that includes
HF transformer leakage inductance Ls and parallel inductance
Lp (equivalent of transformer magnetizing inductance and

RATHORE et al.: WIDE RANGE ZVS ACTIVE-CLAMPED L-L TYPE CURRENT-FED DC/DC CONVERTER

475

Fig. 2. Operating waveforms of active-clamped L-L type ZVS current-fed

dcdc converter shown in Fig. 1.

external parallel inductance). This term is used to distinguish

it from the regular two inductor current-fed converter that uses
only series tank inductance.
The operating waveforms are given in Fig. 2. The two main
switches M1 and M2 are operated with gating signals phase
shifted by 180 with an overlap. The overlap varies with duty
cycle. The duty cycle of the main switches is always kept
greater than 50% due to increased circulating current through
the auxiliary devices and input inductors (L1 and L2 ). It results in unwanted conduction losses and Q-loss causing lower
converter efficiency, particularly at partial load as the auxiliary
circuit loss becomes competitive to the losses in main switches.
The auxiliary switches are controlled by gating signals complementary to the corresponding main switch gating signals. So,
the duty cycle of the auxiliary switches is always less than 50%.
Fixed frequency duty cycle modulation is used for control. The
operation of the converter during different intervals in an HF
half cycle is explained using the equivalent circuits shown in
Fig. 3. For the next half cycle, the intervals are repeated in the

Fig. 3. Equivalent circuits during different intervals of operation of the

proposed converter for the waveforms shown in Fig. 2.

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 1, JANUARY 2012

same sequence with other symmetrical devices conducting to

complete the full HF cycle. The analysis is done to obtain the
design equations to design and select the components as well as
to evaluate the converters performance theoretically.
Interval 1 (Fig. 3(a); to < t < t1 ): In this interval, both the
main switches M1 and M2 are ON. Boost inductors L1 and L2
are storing energy. Power is transferred to the load by the output
filter capacitor Co . The series and parallel inductors are shorted

flows through them, given by
and a constant current ILp,peak

iLs = iLp = ILp,peak

(1)

where iLs is series inductor current, iLp is parallel inductor


is the peak value
current reflected to primary side and ILp,peak
of parallel inductor current, given by

=
ILp,peak

V
.
 in
2 fs Ls + Lp

(2)

The main switch voltage vM 1 increases from Vo /n to Vin +

VCa . A positive voltage equal to (vM 1 Vo /n) appears across
the series inductor and current through it, iLs rises linearly.
Output voltage Vo appears across the parallel inductor Lp and
current through it starts increasing linearly. Rectifier diodes
DR1 and DR4 are forward biased and start conducting when
the series inductor current iLs rises above iLp and power is
transferred to the load. The voltage across the main switch vM 1
is given by
vM 1 =

D
Vin .
1D


iLs = ILp,peak
+

Voltage across the auxiliary switches is

VM a1 = VM a2 = Vin + VCa =

(4)

Duty ratio of main switches M1 and M2 , D = Ton /Ts ; Ton =

main switch conduction time and Ts = switching period.
Currents through main switches M1 and M2 are given by

iM 1 = (Iin /2) + ILp,peak

(5)


iM 2 = (Iin /2) ILp,peak
.

(6)

Voltage across the rectifier diodes

VDR = Vo /2.

(7)

Interval 2 (Fig. 3(b); t1 < t < t2 ): At t = t1 , main switch

M1 is turned off. Boost inductor L1 current (Iin /2) starts
charging the main switch snubber capacitor C1 and discharging
the auxiliary switch snubber capacitor Ca1 linearly. The boost
inductor L1 current (Iin /2) is divided in proportion of their
snubber capacitances. Rectifier diodes are reverse biased and
power is still transferred to the load by filter capacitor.

) flows through the
The same constant current (ILp,peak
series and parallel inductors. At the end of this interval, voltages across the main switch M1 and auxiliary switch Ma1
reach VM 1 (t2 ) = Vo /n and VM a1 (t2 ) = Vin + VCa Vo /n,
respectively.
Interval 3 (Fig. 3(c); t2 < t < t3 ): The boost inductor current is still charging and discharging the snubber capacitors.

(9)

The current iLp through parallel inductor Lp is given by

Vo
(t t2 ).
Lp

(10)

ILp,peak is the peak current through the parallel inductor Lp (on

secondary side). Current through the switch M2 is given by
iM 2 =

Vin
.
1D

vM 1 (Vo /n)
(t t2 ).
Ls

iLp = ILp,peak +

(3)

(8)

The current through series inductor Ls , iLs is given by

Voltage across the auxiliary capacitor Ca is

VCa =

Iin
1
Vo
+

(t t2 ).
n
2 (C1 + Ca1 )

Iin
vM 1 (Vo /n)

ILp,peak
+
(t t2 ).
2
Ls

(11)

Current through conducting rectifier diodes is given by

iDR =

iLs
iLp .
n

(12)

The auxiliary clamp capacitor current iCa increases linearly

and reaches its peak value at the end of this interval that is equal

iLs (t3 ). Since this interval
to ICa,peak = Iin /2 + ILp,peak
is very small and the series inductor current changes a very
little, the peak auxiliary clamp capacitor current is ICa,peak
=

.
Iin /2 + ILp,peak
At the end of this interval, the auxiliary switch snubber
capacitor Ca1 is discharged completely to zero and the main
switch snubber capacitor C1 is charged to its full voltage,
equal to Vin + VCa . Final values are: vCa1 (t3 ) = vM a1 (t3 ) =
0; vM 1 (t3 ) = vC1 (t3 ) = Vin + VCa = Vin /(1 D).
Interval 4 (Fig. 3(d); t3 < t < t4 ): In this interval, the antiparallel body diode Da1 of the auxiliary switch Ma1 starts
conducting and Ma1 can be gated for ZVS turn on. Current
through the series inductor iLs is increasing with the slope of
[(Vin + VCa Vo /n)/Ls ]. Current through the parallel inductor is increasing with the same slope.
The current through series inductor Ls , iLs is given by
iLs = iLs (t3 ) +

VCa + Vin (Vo /n)

(t t3 ).
Ls

(13)

Current through the switch M2 is given by

iM 2 = iM 2 (t3 ) +

VCa + Vin (Vo /n)

(t t3 ).
Ls

(14)

RATHORE et al.: WIDE RANGE ZVS ACTIVE-CLAMPED L-L TYPE CURRENT-FED DC/DC CONVERTER

Current through the parallel inductor is given by

iLp = iLp (t3 ) +

Vo
(t t3 ).
Lp

(15)

where the voltage across the switch Ma1 (or capacitor Ca1 ) is
given by

 
Iin
Ls

+ ILp,peak

vM a1 =
2
(C1 + Ca1 )

Auxiliary capacitor current during this interval is decreasing

and is given by
iCa = ICa,peak

VCa + Vin
Ls

Vo
n

(t t3 ).

iLs

iLs =
iM 2 =
iCa

VCa + Vin
Iin
+
2
Ls

Vo
n


(t t4 )

Iin
+ iLs
2

(17)
(18)


VCa + Vin
Iin
iLs =
=
2
Ls

Vo
n


(t t4 ). (19)

Parallel inductor current at the end of this interval is

iLp (t5 ) = ILp.peak +

V0
(1 D) Ts .
Lp

sin (r (t t5 ))



[1 + sin (r (t t5 ))] .
= Iin + ILp,peak

(20)

At the end of this interval, C1 discharges to Vo /n and Ca1

charges to (VCa + Vin Vo /n). Final values are (neglecting
small increase in current in this short interval)
vM a1 (t6 ) =VCa +Vin Vo /n; vM 1 (t6 ) = Vo /n;

iLs (t6 ) =ILs,peak = Iin +ILp,peak
;

.
iM 2 (t6 ) =IM 2,peak = 3Iin /2+ILp,peak

Interval 7 (Fig. 3(f); t6 < t < t7 ): The current iLs is still

charging Ca1 and discharging C1 in a resonant fashion. This period is also very small and the series inductor current decreases
very little in this interval. The resonant frequency is given by
(21). At the end of this interval, the capacitor C1 discharges
completely to zero and capacitor Ca1 charges to its initial value.
Final values are: vM 1 (t7 ) = 0; vM a1 (t7 ) = VCa + Vin .
Interval 8 (Fig. 3(g); t7 < t < t8 ): In this interval, antiparallel body diode D1 of main switch M1 starts conducting
and now M1 can be gated for ZVS turn on. The series inductor
current iLs decreases with a negative slope of [Vo /(n Ls )].

Ls (C1 + Ca1 )

(21)
iM 1 =

(22)

(26)
(27)

This interval ends when the series inductor current reaches

Iin /2. Final values are: iD1 (t6 ) = 0; iLs (t6 ) = Iin /2.
Interval 9 (Fig. 3(h); t8 < t < t9 ): In this interval, switch
M1 is turned on with ZVS. The current through the switch M1
starts increasing and the series inductor current is decreasing
with the same slope. Series inductor current is transferred to
the switch M1 . The interval ends when the series inductor current equals to parallel inductor current and switch M1 current

reaches to Iin /2 ILp,peak
Vo
Iin

(t t8 )
2
n Ls

(28)

Vo
(t t8 )
n Ls

(29)

Voltage across the capacitor C1 or switch M1 is given by

vM 1 = (VCa + Vin ) vM a1

Vo
(t t7 )
n Ls

iD1 = iLs Iin /2.

iLs =
r = 

(24)

Main switch current is given by



3Iin

+ ILp,peak [1 + sin (r (t t5 ))] . (25)
iM 2 =
2

iLs = iLs (t7 )

At the end of this interval, the auxiliary capacitor current

rises to negative ICa,peak and therefore the series inductor
current reaches (Iin /2 + ICa,peak ) that is its peak value and

approximately equal to Iin + ILp,peak
. Current through the

.
switch M2 also reaches its peak, equal to 3Iin /2 + ILp,peak

Final values are: iCa (t5 ) = ICa,peak = (Iin /2 + ILp,peak );


iLs (t5 ) = Iin + ILp,peak
; iM 2 (t5 ) = 3Iin /2 + ILp,peak
.
Interval 6 (Fig. 3(f); t5 < t < t6 ): The auxiliary switch Ma1
is turned off at t = t5 . The series inductor current iLs charges
Ca1 and discharges C1 . The series inductor Ls resonates with
snubber capacitors Ca1 and C1 . This period is very small and
the series inductor current increases a very little in this interval.
The resonant frequency is given by
1

(23)

(16)

At the end of this interval, i.e., t = t4 , iCa reaches zero,

series inductor current iLs reaches Iin /2 and switch M2 current
reaches Iin . Final values are: iLs (t4 ) = (Iin /2); iCa (t4 ) = 0;
iM 2 (t4 ) = Iin .
Interval 5 (Fig. 3(e); t4 < t < t5 ): In this interval, the auxiliary switch Ma1 is turned on with ZVS. The series inductor
current increases above Iin /2 with the same slope as interval 4.
The auxiliary capacitor current iCa decreases linearly (negative
direction). The current through the parallel inductor is increasing with the same slope as interval 4. The equations for this
interval are


477

iM 2 = Iin

Vo
(t t8 ).
n Ls

(30)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 1, JANUARY 2012


Final values are: iM 1 (t9 ) = Iin /2 ILp,peak
; iM 2 (t9 ) =



Iin /2 + ILp,peak ; iLs (t9 ) = iLp (t9 ) = ILp,peak .
Based on the above analysis, the design equations for the
converter were derived and presented in next section.

III. D ESIGN OF THE C ONVERTER

In this section, design procedure is illustrated by a design
example with a converter of following specifications: input
voltage Vin = 22 to 41 V, output voltage Vo = 350 V, output
power Po = 200 W, minimum load = 10% (20 W), switching
frequency fs = 100 kHz.
1) Average input current is Iin = Po /(Vin ). Assuming an
ideal efficiency of 100%, Iin = 9.1 A.
2) Dmax is selected at minimum input voltage, i.e., Vin =
22 V and full load based on maximum switch voltage rating
VSW (max) using


Dmax = 1 Vin /VSW (max) .

(31)

For VSW (max) = 110 V, Dmax = 0.8.

3) Inductor values Ls and Lp : inductor value Ls is selected
at minimum input voltage and full load condition using
RL
Ls =
fs

(Vin /Vo )2
(Vin /Vo ) (1 Dmax )


.
n
1 + Ls /Lp

(32)

Selecting the inductance values for a certain rated power Po

and switching frequency fs depends upon the transformer turns
ratio n, inductor ratio Lp /Ls , and the maximum duty cycle
Dmax at full load calculated earlier.
Now the transformer turns ratio n = Ns /Np , is selected to
maintain D > 0.5, i.e., voltage regulation with load and fuel
cell stack voltage variation given by
n Vo
D =1
Vin

(V /V )2
L f
 in o  s s

RL
1 + Ls /Lp

(33)

and realizable value of Ls including transformer leakage

(which is an issue mainly for power rating above 1 kW)
given by (32). Also, n should be such that Ls is positive,
using (32)
n > (1 Dmax )


Vo 
1 + Ls /Lp .
Vin

(34)

Fig. 4. Variation of (a) value of series inductance Ls (H), and (b) switch RMS
current (A), with respect to inductor ratio Lp /Ls for various transformer turns
ratio n for the design example.

Inductor ratio Lp /Ls is selected based on the ZVS range,

given by (35) and main switch RMS current given by (36),
which should be low for high efficiency
Iin,critical




2 

 tf (Iin,F
L /2+ILp,peak )
Vin


1DRL

Vin

1DF L
RL

FL

ILp,peak
.
Ls
(35)
Here, tf is fall time of the switches during turn-off (higher
value is taken between fall times of main and auxiliary
switches). Subscripts F L and RL denote full load and
reduced load conditions. (See (36), shown at the bottom of the
page.)
Here, TDR is rectifier diode conduction time given by

Therefore, minimum value of n = 3.5 for Lp /Ls = 10.

Fig. 4(a) shows the calculated values of Ls with respect to
inductor ratio Lp /Ls for three values of turns ratio n.


Isw,rms =

Iin
2

2
D+


ILp,peak

2

D+

TDR =

2
Iin

n Vin

Vo fs 1 +

Ls
Lp

.



TDR
2 TDR


+ Iin ILp,peak D 1 +
Ts
Ts

(37)

(36)

RATHORE et al.: WIDE RANGE ZVS ACTIVE-CLAMPED L-L TYPE CURRENT-FED DC/DC CONVERTER

TABLE I
VARIATION IN D W ITH T URNS R ATIO n FOR VARIOUS
O PERATING C ONDITIONS

479

connect in parallel on secondary side of the transformer is

given by
Lp,ex = 

Lm
Lm
Lp

.
1

(38)

4) Values of boost inductors are given by

During derivation of equations, snubber charging/
discharging intervals (t1 t3 , t5 t7 , t10 t12 , t14 t16 ),
which are of short duration, are neglected.
Fig. 4(b) shows the calculated values of switch RMS current
with respect to Lp /Ls for four values of turns ratio n. Smaller
value of Lp /Ls will achieve ZVS at light load but increase peak
and rms currents through the switches, leading to low efficiency
of the converter.
For smaller turns ratio, i.e., n = 3.5, value of Ls is low
[Fig. 4(a)] and it reduces ZVS range. For higher transformer
turns ratio, i.e., n = 4.5, value of Ls is high [Fig. 4(b)] and
increases ZVS range. Choosing a design (at 22 V, full load)
with smaller value of D, say 0.6 for example (instead of 0.8),
will result in smaller value of series inductance Ls , which
will not be able to store sufficient energy to maintain ZVS for
the wider input voltage range and light load conditions. Also,
choosing a design (at 22 V, full load) according to Fig. 4(a)
for turns ratio n > 4, for example n = 4.5 or 5, will require
higher transformer turns ratio, resulting in higher conduction
losses [Fig. 4(b)] due to increased rms current through the
switches and low converter efficiency. In addition, a design
with D < 0.5, means auxiliary switches operates with D >
0.5. This design and such conditions (D < 0.5) result in higher
circulating current through the auxiliary switches and inductors
L1 and L2 as given in Section I. It increases losses in auxiliary
switches and inductors with no gain at the output resulting in
low converter efficiency at light load as the auxiliary circuit loss
becomes competitive to the losses in main switches. Therefore,
n = 4 with D > 0.5 is chosen.
Turns ratio n = 4 gives realizable value of Ls , maintains voltage regulation at light load for given wide input
voltage variation (Table I) and maintains ZVS till high input voltage. Therefore, transformer turns ratio n = 4 is selected. From Fig. 4(b), for a given n, switch rms current
decreases as the ratio Lp /Ls increases. For the selected
value of n = 4, reduction in rms current is negligible for
Lp /Ls > 25. Therefore, an inductor ratio of Lp /Ls = 25 is
selected.
For Lp /Ls = 25, the cutoff value of input current for ZVS
turn-on of switches [using (35)] is Iin,critical = 1.12 A for
the selected switches mentioned in snubber design. Therefore, the converter is able to maintain ZVS till 12% load.
During analysis and design, ideal components and 100% efficiency is assumed. But in practice, the input current Iin is
higher than assumed and ZVS at load lower than 12% can be
achieved.
From the above discussions, using Dmax = 0.8, n = 4 and
Lp /Ls = 25, calculated values are Ls = 4 H. Lp = 1.61 mH.
If Lm is the magnetizing inductance of the transformer (on
secondary-side), then the external inductor value required to

L1 = L2 = (Vin )(D)/ [(Iin )(fs )]

(39)

where Iin is the boost inductor ripple current.

For Iin = 0.5 A, L1 = L2 = 352 H. Maximum voltage
across the inductors=VCa = 88 V, given by (3).
5) Inductors ratings: The RMS current through the series
and parallel inductors Lp , are



2
2 2 TDR + I 
ILs,rms = Iin
(40)
Lp,peak
3 Ts

1/2

ILp,peak
4 TDR
1
ILp,rms =
.
(41)
n
3 Ts

Using (2), ILp,peak
= 1.05 A. ILp,rms is calculated to be

/
0.22 A. Peak current through the parallel inductor = ILp,peak
n = 0.26 A.
Using (37) and (40), ILs,rms = 3.8 A. Peak current through
Ls is, ILs,peak = Iin + ILp,peak = 10.15 A. Maximum voltage across Ls = Vo /n = 87.5 V. Maximum voltage across
Lp = Vo = 350 V.
6) Switch current ratings: RMS current through the main
switches Isw,rms can be calculated by (36). RMS current
through the auxiliary switches is given by



[(1 D)/24]1/2 . (42)
Iauxsw,rms = Iin + 2ILp,peak

The values of Isw,rms and Iaux,rms are calculated to be

6.3 A and 1.03 A, respectively.
Peak currents through main switches Isw,peak = 3Iin /2 +

= 14.7 A and auxiliary switches Iaux,peak = Iin /2 +
ILp,peak

= 5.6 A.
ILp,peak
Average current through auxiliary switches as well as antiparallel diodes is given by



Iin
(1 D)

+ ILp,peak
Iauxsw,av =
.
(43)
2
4
Here, Iauxsw,av = 0.28 A. Average current through the main
switches Isw,av = Iin /2 = 4.55 A.
7) Auxiliary capacitor: Substituting in (3), Vin = 22 V and
D = 0.8, VCa = 88 V. The value of auxiliary capacitor Ca is

ICa,peak 2(1 D)/3
Ca =
.
(44)
4 fs VCa

Peak current through Ca is ICa,peak = Iin /2 + ILp,peak
=

5.6 A. For a ripple voltage of VCa = 2 V, Ca = 1 F.

RMS current through auxiliary capacitor is


2
(1 D) .
(45)
ICa,rms = ICa,peak
3

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Fig. 5. Simulation waveforms at Vin = 22 V and full load: (a) voltage vAB ,
series inductor current iLs , and parallel inductor current iLp and (b) main
switches currents iM 1 + iD1 and iM 2 + iD2 , auxiliary switches currents
iM a1 + iDa1 and iM a2 + iDa2 .

Here, ICa,rms = 2.05 A. Auxiliary capacitor carries a current

of 200 kHz (twice the switching frequency).
8) Output rectifier diodes: Average rectifier diode current is
given by
IDR,avg = Po /(2Vo ).

(46)

Here, IDR,avg
= 0.3 A. Voltage rating of rectifier diodes,
VDR = Vo = 350 V.
9) Output capacitor: Value of output filter capacitor Co is


(I0 ) T2s TDR
Co =
(47)
Vo
where Vo = Allowable ripple in output voltage. Co = 2 F
for Vo = 0.75 V. Its voltage rating is=Vo = 350 V.
10) Snubber design: The equation for the calculation of
snubber capacitors is given by



tf Iin
2 + ILp,peak
V 
(C1 + Ca1 ) =
.
(48)
in

Fig. 6. Simulation waveforms at Vin = 41 V and 10% load: (a) voltage vAB ,
series inductor current iLs , and parallel inductor current iLp and (b) main
switches currents iM 1 + iD1 and iM 2 + iD2 , auxiliary switches currents
iM a1 + iDa1 and iM a2 + iDa2 .

0.18 , Coss = 430 pF, tf = 36 ns), the calculated values of

snubber capacitors are C1 = 0.603 nF, Ca1 = 1.84 nF. Snubber
capacitors voltage rating is equal to switch voltage rating,
given by (4) or (31) and is=110 V.
11) ZVS Conditions: (A) To achieve ZVS of auxiliary
switches, in interval 2, the dead-gap between the main switch
gating signal GM 1 and auxiliary switch gating signal GM a1
(Fig. 2) should be of sufficient duration to allow charging and
discharging of the snubber capacitors C1 and Ca1 , respectively,
by the boost inductor current Iin /2. The value is given by
Tdg1

(C1 + Ca1 )
=
Iin /2

Vin
1D


.

(49)

(B) For ZVS of main switches, in interval 5 the charging

of and discharging of the snubber capacitors Ca1 and C1 ,
respectively should be done by the series inductor current in
a quarter of the resonant period and is equal to the dead-gap
between the auxiliary switch gating signal GM a1 and main
switch gating signal GM 1 and is given by

1D

Here, tf = fall time of the switches during turn-off. C1 =

Coss,M 1 ; Ca1 = (C1 + Ca1 ) Coss,M 1 .
For the selected main switches IRFP260N (Vds = 200 V,
ID = 50 A, Rdson = 40 m, Coss = 603 pF, tf = 48 ns) and
auxiliary switches IRF640 (Vds = 200 V, ID = 18 A, Rdson =

Tdg2 =


Ls (C1 + Ca1 )
2

(50)

where Tdg1 = 60 ns and Tdg2 = 156 ns. Identical dead-gaps

Tdg1 = Tdg2 = 156 ns is provided between the main and auxiliary gating signals.

RATHORE et al.: WIDE RANGE ZVS ACTIVE-CLAMPED L-L TYPE CURRENT-FED DC/DC CONVERTER

481

TABLE II
C OMPARISON OF A NALYTICAL , S IMULATED AND E XPERIMENTAL R ESULTS FOR THE D ESIGNED C ONVERTER AT fs = 100 K H Z AND Vo = 350 V

(C) To achieve ZVS of main switches, the energy stored in

the series inductor Ls at t = t4 must be sufficient to charge Ca1
and discharge C1 . It gives

2
Ls ILs,peak
(C1 + Ca1 )

Vin
1D

2
.

(51)

For the given specifications and the calculated values of

components, theoretically, the converter is able to maintain
ZVS till 12% load at 22 V and 5% load at 41 V.
IV. S IMULATION AND E XPERIMENTAL R ESULTS
The designed converter rated at 200 W was first simulated
using PSIM 6.0.1 and then built in the laboratory to verify the
analysis, design and performance of the converter. Simulation
results for two extreme operating conditions of Vin = 22 V,
full load and Vin = 41 V, 10% load are presented in Figs. 5
and 6, respectively. The components values obtained in design
section above are used as simulation parameters.
Simulation waveforms coincide with the theoretical operating waveforms shown in Fig. 2. When both the main switches
are on, vAB = 0, iLp is flowing through iLs and are constant.
Whenever, one main switch is off, vAB appears across the
transformer and the current iLs and iLp change direction. At
higher voltage and light load condition (Fig. 6), the duty cycle
is low and therefore vAB appears for longer time. It makes the
currents iLs and iLp to be constant for a very small duration
and their appearance look like triangular. Figs. 5 and 6 show
that the anti-parallel diodes of the switches (main and auxiliary)
conduct prior to the conduction of corresponding switches
causing zero voltage turn-on. It is also clear that the series
inductor current iLs is continuous unlike its basic standard
converter. It should be noticed that with increase in input
voltage and/or reduction in load current, the duty cycle of main
switches reduces, therefore causing increase in peak value of
parallel inductor current, which adds to series inductor current
to achieve ZVS of main switches at such wide variation. At light
load condition, increased anti-parallel body diode conduction
time can be noticed due to parallel inductor current, assuring
ZVS of main switches.
To obtain the simulation results for given input voltage
(22 V in Fig. 5 and 41 V in Fig. 6) and for given load condition
(612.5 at full load in Fig. 5 and 6125 at 10% load in Fig. 6)

simulation is run for several HF cycles until the state variables

reach a steady-state. Duty cycle used for each case is given in
Table II. The devices/components used are ideal.
The details of the experimental converter are as follows.
IRFP260N (main switches); IRF640 (auxiliary switches);
MUR160 (rectifier diodes); HF transformer: PC40ETD49-Z
ferrite core, primary turns = 7, secondary turns = 28, leakage
inductance (reflected to primary side)= 0.5 H, magnetizing
inductance (secondary side)= 4.8 mH; series inductor: Gapped
core used PC40RM14Z-1Z-A250, number of turns = 5, measured inductance= 3.6 H, parallel inductor: A-254168-2,
120 turns, Lp = 2.4 mH; boost inductors: MPP Powder core,
A-438281-2, 34 turns, L1 = L2 = 350 H. Gating signals
for the switches have been generated using Spartan-3 FPGA
board. IR2110 driver ICs are used for gating the MOSFETs. A
variable dc voltage source (for input) is obtained from a threephase (208 line-line RMS, 60 Hz) ac source through a threephase auto-transformer (variac) that is rectified and filtered with
L-C filter to provide a stiff dc voltage input to the converter.
Load is made of several resistance boxes connected in series
and parallel with on/off switches to get various load values
(612.5 for full load, 1225 for half-load and 6125 for 10%
load). The converter has been tested for input voltages of 22 and
41 V at full load and 10% load, respectively. The experimental
results are shown in Figs. 710. Parts (b)(d) of Figs. 710
clearly confirm the ZVS of main and auxiliary switches over
wide variation in fuel cell voltage and load. In waveforms
shown in part (b) of Figs. 710, gating signals (vGS ) are applied
to main switches after voltage across them (vDS ) reaches
zero. The ZVS turn on of main switches is also confirmed by
part (c) of Figs. 710 since anti-parallel diode is conducting
before the switch starts conducting. Similarly, in part (d) of
Figs. 710, anti-parallel diode of the auxiliary switches is
conducting first causing ZVS turn-on of the auxiliary switches.
Voltage across the transformer vAB and the series inductor
current iLs confirm ZCS of rectifier diodes (negligible ringing),
as shown in part (a) of Figs. 710.
Table II shows a comparison of various parameters for the
proposed converter. The simulation and theoretical values are
nearly the same as they follow the same assumptions that verify
the accuracy of the analysis. Theoretical/simulation and experimental values are in reasonably good agreement. The difference
comes due to the voltage drop and power loss across various
devices that exist in the experimental converter, while neglected

482

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 1, JANUARY 2012

Fig. 8. Experimental waveforms at Vin = 41 V and full load: (a) vAB

(100 V/div) and iLs (5 A/div), (b) main switch voltage vDS (100 V/div)
and vGS (10 V/div), (c) main switch current iM 1 + iD1 (4 A/div),
(d) iM a1 + iDa1 (2.5 A/div), and (e) parallel inductor current iLp (0.4 A/div).

Fig. 7. Experimental waveforms at Vin = 22 V and full load: (a) Voltage

vAB (100 V/div) and series inductor current iLs (10 A/div), (b) main switch
voltage vDS (100 V/div) and gate voltage vGS (10 V/div), (c) main switch
current iM 1 + iD1 (10 A/div), (d) auxiliary switch current iM a1 + iDa1
(5 A/div), and (e) parallel inductor current iLp (0.4 A/div).

in simulation/analysis assuming ideal components. Differences

are larger for 10% load since the constant losses dominate over
the conduction losses, while in simulation, constant losses are
neglected. Some ringing is noticed during measurements and
capturing waveforms due to stray inductances present owing to

RATHORE et al.: WIDE RANGE ZVS ACTIVE-CLAMPED L-L TYPE CURRENT-FED DC/DC CONVERTER

483

Fig. 10. Experimental waveforms at Vin = 41 V and 10% load: (a) vAB
(100 V/div) and iLs (2.5 A/div), (b) vDS (100 V/div) and vGS (10 V/div),
(c) iM 1 + iD1 (2 A/div), (d) iM a1 + iDa1 (2.5 A/div), and (e) iLp (0.4 A/div).
Fig. 9. Experimental waveforms at Vin = 22 V and 10% load: (a) vAB
(100 V/div) and iLs (2.5 A/div), (b) main switch voltage vDS (100 V/div)
and vGS (10 V/div), (c) iM 1 + iD1 (2 A/div), (d) iM a1 + iDa1 (2.5 A/div),
and (e) iLp (0.4 A/div).

wiring connections and device capacitances. The peak parallel

inductor current increases with increase in input voltage. This
helps in achieving ZVS at light load conditions. Full load
efficiencies at Vin = 22 V and 41 V are 93.7% and 93.5%,
respectively. With reducing load and increasing input voltage,
switch rms current decreases, maintaining higher efficiency.
With Vin = 22 V at full load, the proposed topology has
93.7% efficiency, while the standard topology has 94.5%. On

the other hand, with Vin = 22 V at 10% load, the proposed

topology has 87% efficiency, while the standard topology
has 81.8%. Due to soft-switching at light load condition, the
proposed converter maintains higher efficiency than its basic
standard converter, which is hard-switched now. At full load,
there is a compromise in efficiency of 0.8%, to achieve wide
range soft-switching and better part-load efficiency.
The calculated efficiency curve for several load conditions
with some experimental efficiency data points for input voltages
of 22 V and 41 V are plotted in Fig. 11. In brackets (C) and (E)
stand for calculated and experimental values, respectively.

484

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 1, JANUARY 2012

Fig. 11. Plots of efficiency versus output power obtained from calculations
(C) and experiments (E) for different load conditions with Vin = 22 V and
41 V for the experimental converter.

It is observed from these curves that the experimental values

coincide with the calculated values. The experimental waveforms (Figs. 710) and the efficiency curves (Fig. 11) illustrate
that the converter maintains ZVS for all switches over the
complete range of load variation for wide input voltage range
(22 to 41 V) while maintaining high efficiency.
Under light load conditions, due to the constant losses in the
converter, efficiency drops to a low value. It is lower below
10% load and the fuel cell stack voltage rises to higher value
(41 V). It asks for higher fuel (H2 ) supply reducing the overall
efficiency of the system and resulting in its poor utilization.
Therefore, usually, such a lower load operation (<10%) on fuel
cell is not to be preferred. To take care of transients, we assume
that ultra capacitors are used at the input. In case of change in
load, for example, full load to lower load, the ultracapacitors are
smoothly discharged using average current control. The current
command is generated by input based mainly on fuel flow. The
fuel flow decides the power transfer capacity. The fuel cell
response time is slow and can be matched by proper bandwidth
selection in the controller design [38].
V. S UMMARY AND C ONCLUSION
To achieve ZVS for wide variation in input voltage and
load while maintaining high efficiency has been a challenge,
especially for low voltage higher current input applications. A
ZVS L-L type active-clamped current-fed converter has been
proposed in this paper. The external parallel inductor increases
the series inductor current at light load and therefore, the energy
stored in series inductor to maintain ZVS. Proposed design
is simple and without any resonant circuit, popularly used in
voltage-fed resonant converters. Because of high Lp /Ls ratio,
the circulating current through the components is very low
compared to voltage-fed converters, which reduces the current
stress on the components. Conventional converters lose softswitching at light load and higher input voltage, resulting in
lower light load efficiency. Proposed converter maintains softswitching over wide range of load and supply voltage while
maintaining high efficiency. The proposed topology with wide
range ZVS results in better part load efficiency resulting in

less fuel (hydrogen) demand or in other words in better fuel

utilization, which further reduces the cost of energy due to fuel
savings. Detailed operation, analysis and design procedure of
the converter with a design example are presented. Experimental results verify the accuracy of the analysis and show that the
proposed configuration is able to maintain ZVS of all switches
over a wide range of load and input voltage variation due to the
variation in fuel flow and stack temperature. Theoretically, the
converter is able to maintain ZVS till 12% load at 22 V and 5%
load 41 V. But due to losses at light load condition, the input
current and the peak series inductor current is higher than its
theoretical value, and maintains ZVS at loads lighter than the
theoretical values for a very wide input voltage range. It should
be noted that design example of a 200 W converter is given only
for illustration purpose. In an actual implementation, target is a
5-kW converter realized by interleaving five 1-kW converters.
Design of each 1-kW cell follows the same procedure discussed
in this paper. Small signal analysis and design of closed loop
control system (based on two-loop average current control) of
the proposed converter for stable operation has been presented
in [36] and [38].
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485

Akshay K. Rathore (S03M07) received the B.E.

degree in electrical engineering from Maharana
Pratap University of Agriculture and Technology,
Udaipur, Raj., India, in 2001, M.Tech. degree in electrical machines and drives from Institute of Technology, Banaras Hindu University (ITBHU), Varanasi,
Uttar Pradesh, India, in 2003 and Ph.D. degree
in power electronics from University of Victoria,
Victoria, BC, Canada, in 2008.
He was awarded Gold Medal for securing highest
academic standing among all the electrical engineering specializations. He received Ph.D. degree in power electronics from
University of Victoria, BC, Canada, in 2008. He was a recipient of Ph.D.
fellowship and Thouvenelle Graduate Scholarship during his Ph.D. Previous
to joining Ph.D., he was a Lecturer in electrical engineering at College of
Technology and Engineering, Udaipur and Mody Institute of Technology and
Science, Lakshmangarh, India, from February 2003 to July 2004. He was also
a sessional lecturer with Department of Electrical and Computer Engineering,
University of Victoria, BC, Canada, from MayDecember 2007. He has held
postdoctoral appointments with Electrical Machines and Drives Laboratory,
University of Wuppertal, Germany, from September 2008August 2009 and
University of Illinois at Chicago, from September 2009September 2010.
Currently, he is an Assistant Professor at Electrical and Computer Engineering
Department, National University of Singapore, Singapore since November
2010. His research interests mainly include soft-switching, high-frequency
power conversion, distributed generation, renewable integration, optimal modulation, and control of electrical drives.
Dr. Rathore was listed in Marquis Whos Who in Science and Engineering
in 2006, Whos Who in the World, and Whos Who in America in 2008. He is
a reviewer of IEEE T RANSACTIONS, Institute of Engineering and Technology,
and Elsevier.
Ashoka K. S. Bhat (S82M85SM87F98) received the B.Sc. degree in physics and math from
Mysore University, Mysore, India, in 1972. He received the B.E. degree in electrical technology and
electronics and the M.E. degree in electrical engineering, both with distinction from the Indian Institute of Science, Bangalore, India, in 1975 and 1977,
respectively. He also received the M.A.Sc. and Ph.D.
degrees in electrical engineering from the University
of Toronto, Toronto, ON, Canada, in 1982 and 1985,
respectively.
From 1977 to 1981, he worked as a Scientist in the Power Electronics Group
of the National Aeronautical Laboratory, Bangalore, India, and was responsible
for the completion of a number of research and development projects. After
working as a Postdoctoral Fellow for a short time, he joined the Department
of Electrical and Computer Engineering, University of Victoria, Victoria, B.C.,
Canada, in 1985, where he is currently a Professor of Electrical Engineering
and is engaged in teaching and conducting research in the area of power
electronics. He was responsible for the development of the Electromechanical
Energy Conversion and Power Electronics courses and laboratories in the
Department of Electrical Engineering at the University of Victoria. He received
the Excellence in Teaching Award from the Faculty of Engineering during
the year 2008 and the Wighton Fellowship for the year 2010.
Dr. Bhat is a Fellow of the Institution of Electronics and Telecommunication
Engineers (India), and a registered Professional Engineer in the province of
British Columbia, Canada.
Ramesh Oruganti (S83M85SM01) received
the B.Tech. and M.Tech. degrees from the Indian Institute of Technology, Chennai, India, and the Ph.D.
degree from Virginia Polytechnic Institute and State
University, Blacksburg, in 1987.
He worked for several years in India in the area
of power conversion. He was with the Corporate Research and Development Division, General Electric
Company, U.S., where he was involved in research
on advanced power converter systems. Since 1989,
he has been with the Department of Electrical and
Computer Engineering, National University of Singapore, Singapore, where he
is currently an Adjunct Associate Professor. He was also a Visiting Academic
in the School of Electrical Engineering and Telecommunications, University
of New SouthWales, Sydney, N.S.W., Australia. His research interests include
several areas of power electronics and renewable energy applications of power
electronics. He has authored or coauthored several papers in power electronics.
He holds a patent on dc-dc converters.
Dr. Oruganti is a co-recipient of two IEEE Prize Paper Awards.