Arise'14 Ijert

International Journal of Engineering Research & Technology (IJERT)
ARISE' 14 Conference Proceedings
Watermarking of Compressed imageswithImproved

Encryption
Deepa L C
Meerakrishna G H
Department of Computer Science, CUSAT

TKM Institute of Technology
Kollam,Kerala,India
deepa08111989@gmail.com
Department of Computer Science, CUSAT

TKM Institute of Technology
Kollam,Kerala,India
meerakrishna1410@gmail.com
require decompression or decryption, and also preserves the

confidentiality of the content because it doesnt need
decryption at the time of watermark embedding.A V
Subramanyam (2012) [1] proposed a robust watermarking
algorithm to watermark jpeg2000 compressed encrypted
images.The technique here used was spread spectrum. But the
problem was that this technique has only low number of bit
capacity. GaoHai-ying, Liu Guo-qiang, and XuYin(1993) [2]
proposed a new robust watermarking algorithm for JPEG2000
images. Here the watermark information is embedded by
modifying the wavelet coefficients in pairs after quantization of
the original image. The main problem of this work was image
quality degradation and the lack of ability to resist attacks. To
overcome this problem Kan Li and Xiao-Ping Zhang(2001) [3]
proposed a robust adaptive watermarking scheme .It was a
compression degree adaptive method .Here the watermark will
be embedded in to the middle frequency wavelet coefficients
after quantization. But this approach couldnt overcome the
security problems. Roland Schmitz (2006) [4] proposed a
commutative watermarking encryption method. It was
designed by combining histogram based watermarking scheme
with a permutation cipher. Here the permutation cipher is used
toencrypt the multimedia data. The disadvantage of this work
was that it was not a secure method. Zhi Li and Yong Lian
(2007) [5] introduced a method for content dependent
watermarking and authentication. It had been proposed as a
solution to overcome the potential estimation attack aiming to
recover and remove the watermark from the host signal. A
watermarking scheme based on TCQ quantization scheme was
proposed by D.Goudia(2009) [6]. The main contribution is that
this system allows both quantization of wavelet coefficients
and watermark embedding by using the same quantization
module.
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AbstractMedia data generally Handles In compressed and

encrypted form. It is necessary To watermark these compressed
encrypted media
Items in the compressed encrypted
domainitselffortamperdetectionorownershipdeclaration
orcopyrightmanagement purposes. It is a challenge to watermark
this media data in compressed and encrypted domain because of
security and visual quality problems. The watermarking in
encrypted domain gives double security. Thus it is necessary to
choose a watermark embedding and encryption scheme for
maintaining both security and visual quality. In this work, a
robust approach for watermarking images in compressed and
encrypted domain is presented. The encryption algorithm here
used is Rijndael encryption algorithm. While the proposed
technique embeds watermark in the compressed-encrypted
domain, the extraction of watermark can be done in the decrypted
domain. The watermark embedding technique used is Rational
Dither Modulation (RDM).
Keywords Compressed and Encrypted domain watermarking,
copyright, Visual cryptography, RDM
I. INTRODUCTION
Watermarking has an important role in the digital media
content distribution. It is necessary to watermark these
compressed encrypted media items in the compressed
encrypted domain itself for tamper detection or ownership
declaration or copyright management purposes. Digital Right
management system is an example, where the owner of
multimedia content, distribute it in a compressed and encrypted
format to consumers through multilevel distributor network,
each distributor sometime needs to watermark the content for
media authentication, traitor tracing or proving the
distributorship. Watermarking has an important role in DRM
systems. It helps publishers; copyright protectors etc to keep
track their digital data after sale. It helps the developers to
transfer the media data securely in this domain. In DRM
systems there are multiple levels of distributers and consumers.
The distributors dont have access to the plain text. This paper
focus on the watermarking of compressed encrypted images,
where the encryption refers to the ciphering of complete
compressed stream. Watermarking in compressed-encrypted
content saves the computational complexity as it does not
In this paper we focus on watermarking of compressedencryptedimages, where the encryption refers to the ciphering
of images in compressed stream. The aim of watermarking is to
provide the digital media content creator with the ability to
keep track of their media data after sale. Watermarking is a
data hiding method. This technique is mainly used in one to
many communications. Watermarking can be done in
encrypted domain or compressed domain. The problem of
watermarking in encrypted domain is that changing a single bit
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may lead to random decryption and there is no strong security

in compressed domain. So here we choose the compressed and
encrypted domain. In our algorithm the watermark embedder
only have compressed encrypted content. Also the watermark
embedders do not have the key to unencrypt and get the plain
text compressed values. However the proposed system faces
the following challenges.
1) Compressed Domain Watermarking: A small
modification in the compressed data may lead to the
degradation of decoded image. Thus we have to find the place
for embedding the data very carefully, so we can reduce the
visual quality degradation.
2)
Encrypted Domain Watermarking and Watermark
Retrieval: In an encrypted piece of content, changing even a
single bit may lead to a random decryption; therefore the
encryption should be such that the distortion due to embedding
can be controlled to maintain the image quality. It should also
be possible to detect the watermark correctly even after the
content is decrypted. Also, the compression gain should not be
lost as encryption may lead to cipher text expansion.
then reduced by a constant to make it symmetric around zero

and finally a multi-component transform is performed. In the
second stage, the discrete wavelet transform (DWT) is applied
followed by quantization in the third stage. Multiple levels of
DWT gives a multi-resolution image. The lowest resolution
contains the low-pass image while the higher resolutions
contain the high-pass image. These resolutions are further
divided into smaller blocks known as code-blocks where each
code-block is encoded independently. Further, the quantizedDWT coefficients are divided into different bit planes and
coded through multiple passes at embedded block coding with
optimized truncation (EBCOT) to give compressed byte stream
in the fourth stage. The compressed byte stream is arranged
into different wavelet packets based on resolution, precincts,
components and layers in the fifth and final stage. Thus, it is
possible to select bytes generated from different bit planes of
different resolutions for encryption and watermarking.
B. Encryption Algorithm
The encryption method we are using here is Visual
cryptography&Rijndael. The secret image will be divided into
two shares
This paper is organized as follows. Section II describes the

proposed scheme. In section III we discuss the encryption
algorithm, watermark embedding and extraction algorithm .The
experimental results are discussed in Section IV. Section V
concludes the paper. The theoretical analysis and derivations
are given in the Appendix.
Overview
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II. PROPOSED SCHEME
Share 1
At first blue region detection is performed on input image

using HSV color space.Secondly cover image is transformed
in frequency domain. (DWT) This is performed by DWT on
image leading to four subbands.Then payload (number of bits
in which we can hide data) is calculated. Then secret data
embedding is performed in one of the high frequency subband by tracingblue area pixels in that band.Then extract it.
Plain Text ( In form of Image)
Share2
Stacking the shares reveals the secret.

Fig 1:Visual cryptography
Encryption ( Creating shares)
Channel (Cover image , Dither Modulation)
Visual cryptography scheme in computer representation using

nm matrix is as follows:
Extraction
Decryption
A. Image Compression
The image compression is divided into five stages. In the
first stage the input image is preprocessed by dividing it into
non-overlapping rectangular tiles, the unsigned samples are
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Orginalpixel :
Share 1 (S1)
Share 2 (S
subband coefficients the highest texture energy subband is

selected. On this subband apply DWT to obtain the second
level decomposition. From this again select a subband having
hightexture energy. Before embedding the watermark into
selected subbands, the watermark image is split into two shares
by applying (2, 2)V CS scheme using AOD . Out of these two
shares one share is embedded into selected subband and other
share is kept secret.
C..Embedding Algorithm
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Using the permutated basis matrices, each pixel from the secret
image will be encoded into two sub pixels on each participant's
share. A black pixel on the secret image will be encoded on the
ith participant's share as the ith row of matrix S1, where a 1
represents a black sub pixel and a 0 represents a white sub
pixel. Similarly, a white pixel on the secret image will be
encoded on the ithparticipant's share as the ith row of matrix
S0.
The details of the algorithm is as follows:

Algorithm: Watermark Embedding Algorithm.
Input : Cover (Color) image, Watermark (gray-scale) image.
Output : Watermarked color image.
1) Read the cover (color) image I of size N N and watermark
(gray-scale)imageWof size M M
2) Decompose the color image into Luminance (Y ), Intensity (I)
and Hue (Q) channels of size M M
3) Split the watermark by applying V CS using AOD is kept
secret and S1 is used for embedding.
4) Apply DWT on Luminance (Y ) channel to get subband
coefficients (LL1, LH1, HL1 and HH1).
5) Extract the texture property Energy for each subband
coefficient
6) Select the subband frequency coefficients (LL1 or LH1 or
HL1 or HH1 ) which is having high energy.
7) Apply the DWT on selected subband to get second level
decomposition (LL2, LH2, HL2 and HH2).
8) Extract the vector of texture property Energy for each
subband of second level decomposition
9) Select the subband which is having high energy from second
level decomposition (LL2,orLH2 or HL2 or HH2).
10) Embed the share S1 produced in Step 3 into the selected
subband coefficients of Step 9 using following steps.
fori= 1 to M do
forj= 1 to M do
Y_(i, j) = (|Y (i, j)| + )S1(i, j)
end for
end for
The embedding algorithm uses color image as cover and

grayscale image as watermark. The color image is decomposed
into Luminance, Intensity and Hue channels. The DWT is
applied on the Luminance channel of color image, which
produces the frequency subband coefficients. From these
Where Y_(i, j) represents the modified frequency coefficient of

subband, Y (i, j) represents the original frequency coefficient of
subband, represents the watermark scaling factor.
11) The value of is adjusted such that the texture properties
of embedded subband are changed by negligible value
12) Replace the modified subband coefficients into its initial

location and apply twice inverse DWT to get the watermarked
Luminance channel.
13) Combine the watermarked Luminance (Y ) channel with
Intensity (I) and Hue (Q) to get watermarked color image.
D. Extraction Algorithm
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Extraction algorithm is of type blind extraction which uses

only watermarked color image as input. The watermarked color
image is decomposed into Luminance, Intensity and Hue
channels. The DWT is applied on the Luminance channel of
watermarked color image, which produces the frequency
subband coefficients. From these subband coefficient the
highest texture energy subband is selected. On this subband
apply DWT to obtain the second level decomposition. From
this againselect a subbandhaving high texture energy. The
watermark is extracted from these selected subband
coefficients. After extracting the watermark, the watermark
image is superimposed with secret share using V CS scheme as
explained in Section 3. The output of superimposition produces
the extracted watermark. The details of the extraction
algorithm are explained below.
Algorithm: Watermark Extraction Algorithm.
Table 1 : Algorithm comparison

Algorithm
Key Size
Rijndael
128,192,256
bits
Twofish
128,192,256
bits
128
Blowfish
32-448 bit
RC4
Variable
RC2
8- 128 bit
TripleDES
112 or 168
bits
56 bits
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Input : Watermarked (Color) image.

Output : Extracted watermark.
1) Read the watermarked color image I of size N N
2) Decompose the watermarked color image into Luminance
(Y ), Intensity (I) and Hue (Q) channels of size M M
3) Apply DWT on Luminance (Y ) channel to get subband (LL1,
LH1, HL1 and HH1).
4) Extract the texture property Energy for each subband
coefficients.
5) Select the subband frequency coefficients (LL1 or LH1 or
HL1 or HH1 ) which is having high energy.
6) Apply the DWT on selected subband to get second level
decomposition subbands(LL2, LH2, HL2 and HH2)
7) Extract the texture property Energy for each subband of
second level decomposition.
8 Select the subband frequency coefficients which is having
high energy from second level (LL2,orLH2 or HL2orHH2).
9) Extract the share S1 from selected subbandcoefficientsof
Step 9 using following steps.
fori= 1 to M do
forj= 1 to M do
ifY _ _ 0 then
S1(i, j) = 1;
else
S(i, j) = 0;
end if
end for
end for
10) Superimpose extracted share S1with secret share S0using V
CS
diffusion is improved by several simple steps in the round:

integer multiplication, the quadratic equation, and fixed bit
shifting. The data-dependent rotations are improved, as the
rotation amounts are determined from the high-order bits in f(x),
which in turn are dependent on the register bits. The security
has been evaluated to possess an adequate security margin;
this rating is given with familiarity of theoretical attacks, which
were devised out of the multiple evaluations. The AES-specific
security evaluations provide ample breadth and depth to how
RC6 security is affected by the simplicity of the cipher.
DES
Block
size
128
Algorithm
structure
Substitutio
n ,permutat
ion
Feistel
Network
Rounds
64
Feistel
Network
16
Varia
ble
64
Stream
Unkno
wn
16
64
64
Heavy
Fiestel
Network
Feistel
Network
Feistel
Network
10,12 or
14
16
48
16
Existing
cracks
Side channel
attacks
Truncated
differential
cryptanalysis
Second order
differential
attacks
Weak
key
schedule
Related key
attacks
Theoritically
possible
Brute force
attacks
IV. CONCLUSION
This paper provides double security through encryption and
watermarking. Encryption provides security by hiding the
content of secret information; while watermarking hides the
existence of secret information. Earlier works were
concentrated on encrypted or compressed domain only.The
proposed system helps to embed a robust watermark in the
compressed encrypted images using the watermarking scheme
spread spectrum. The algorithm is simple to implement as it is
directly performed in the compressed-encrypted domain, i.e., it
does not require decrypting or partial decompression of the
content. This scheme also preserves the confidentiality of
content as the embedding is done on encrypted data. The
homomorphic property of the cryptosystem is exploited, which
allows us to detect the watermark after decryption and control
the image quality as well.
III. RESULTS AND DISCUSSION

Security of Encryption Algorithm
To verify the effectiveness of the proposed scheme, a series of
experiments were conducted. By keeping the cipher structure
simple, it becomes accessible to a larger set of people for
evaluation. The simplistic structure also plays a part in
performance and security. The security of the cipher is
amplified by the simple structure. For instance, the rate of
ACKNOWLEDGEMENT
This workwassupportedin
partbythe
Departmentof
ComputerScience&Engineering,
TKMIT,andKollam.We
wouldliketoshow
ourgratitudetoProfP.Mohamed
Shameem&Asst.Prof.Meerakrishna
G
Hfortheirvaluable
guidance.
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REFERENCES
[2]
[3]
[4]
[5]
A.V.Subramanyam,SabuEmmanuel,Robustwatermarkingof
compressed encrypted JPEG 2000images, IEEEtransactions on
multimedia, vol. 14, no.3, june 2012.
Guo-quang,LiuGuo-qiang and Xuyin,A New Robust watermarking
algorithm for JPEG2000 images,.
KanLiand Xiao-Ping Zhang, Reliable Adaptive Watermarking
Scheme Integrated with JPEG2000,Proceedings of the 3rd
International Symposium on Image and Signal Processing and Analysis
(2003).
S. Lian, Z. Liu, R. Zhen, and H. Wang, Commutative watermarking
and encryption for media data, Opt. Eng., vol. 45, pp. 13, 2006.
Z. Li, X. Zhu, Y. Lian, and Q. Sun, Constructing secure content
dependent watermarking scheme using homomorphic encryption, in
Proc. IEEE Int. Conf. Multimedia and Expo, 2007, pp. 627630.
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[1]
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3D IMAGERY IN ROCKETRY
Soumya V. S
M.Tech , Dept of ECE
Marian Engineering College
Subha Varier
Scientist/Engineer SG
Indian Space Research Organization (ISRO)
Thiruvananthapuram.
The sensation of realism can be achieved by visual

presentations that are based on three-dimensional (3D)
im-ages. To generate even more vivid and realistic
informa-tion, it is possible to use two or more cameras
placed at slightly different view-points. This allows the
production of multiview sequences.
The Multi-view video structure consists of several video
sequences, which are captured by closely located cameras
in most of the applications. The close location of cameras in
these applications results in a high redundancy between the
sequences from different cameras.
3D video provides a visual experience with depth perception through the usage of special displays that re- pro-ject
a three-dimensional scene from slightly different dir-ections
for the left and right eye. Such displays include stereoscopic
displays, which typically show the two views that were
originally recorded by a stereoscopic camera system. Here,
glasses-based systems are required for mul-tiuser
audiences. Especially for 3D home entertainment, newer
stereoscopic displays can vary the baseline between the
views to adapt to different viewing distances. In addi-tion,
multi-view displays are available, which show not only a
stereo pair, but a multitude of views (typically 20 to more
than 50 views) from slightly different directions. Each user
still perceives a viewing pair for the left and right eye.
However, a different stereo pair is seen when the viewing
position is varied by a small amount. This does not only
improve the 3D viewing experience, but allows the
perception of 3D video without glasses, also for multi-user
audiences. As 3D video content is mainly produced as stereo
video content, appropriate technology is required for
generating the additional views from the stereo data for this
type of 3D displays. For this purpose, different 3D video
formats or representations have been considered.
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Abstract - 3-D video will become one of the most

significant video technologies in the next-generation. In
rocketry bandwidth is an essential requirement. Due to
the ultra high data bandwidth requirement for 3-D
video, effective compression technology becomes an
essential part in the infrastructure. Thus multiview video
coding (MVC) plays a critical role. MVC is an extended
version of H.264/AVC that improves the performance of
multiview videos. The entire image is divided into
macro blocks. The size of macroblock depends on
codec used. Multi-view video coding (MVC) is an
ongoing standard in which variable size disparity
estimation (DE) and motion estimation (ME) are both
employed to select the best coding mode for each
macroblock (MB). A multidirectional spatial prediction
method is also employed for each macroblock to
reduce spatial redundancy. The multi-view video plus
depth (MVD) coding will give 3D video (3DV).
Index Terms- 3D video coding (3DVC), multi-view
video plus depth (MVD), H.264/AVC, multiview video
coding (MVC).
I. INTRODUCTION
ITH the development of the technology of 3DTV
and free viewpoint TV (FTV), MVC attracts more and more

attention. In recent years, MVC technology is now being
standardized by the Joint Video Team (JVT) as an extension
to H.264 [1].
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A straight forward method to encode the multi-view

se-quences is simulcast coding, in which each view is
en-coded independently with the state-of-art
H.264/AVC co-dec. Though the H.264/AVC can
achieve a very high cod-ing efficiency for each single
view, statistical results show that there are still
correlations left between different views [2].

stereo views. The prediction structures are presented

in Section IV. Here to obtain 3D view it requires a 3-D
depth impression of the observed scenery. Section V
ex-plains the depth coding approaches. Finally,
Section VI concludes this paper.
II. REQUIREMENTS
Fig 1: Overall structure of an MVC system
III. CODING OF STEREO VIEWS
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Stereoscopic vision is based on the projection of an object

on two slightly displaced image planes and has
an extensive range of applications, such as 3-D television, 3-D
video applications, robot vision, virtual machines, medical surgery
and so on. Two pictures of the same scene taken from two nearby
points form a stereo pair and con-tain sufficient information for
rendering the captured scene depth. The above demanding
application areas re-quire the development of more efficient
compression tech-niques of a stereo image pair or a stereo image
sequence. In a monoscopic video system the compression is based
on the intra-frame and inter-frame redundancy. Typically the
transmission or the storage of a stereo image sequence re-quires
twice as much data volume as a monoscopic video system.
Nevertheless, in a stereoscopic system a more effi-cient coding
scheme may be developed if the in-ter-sequence redundancy is
also exploited.
H.264 is the newest international video coding standard.
Compared to prior video coding standards, H.264 mostly enhances
the coding efficiency. So its more possible to resolve the problem of
stereoscopic storage and transmis-sion using coding based on
H.264.Since the multi video approach creates large amounts of data
to be stored or transmitted to the user, efficient compression
techniques are essential for realizing such applications. The
straight-forward solution for this would be to encode all the video
signals independently using a state-of-the-art video codec such as
H.264/AVC [2][4]. However, multiview video contains a large
amount of inter-viewstatistical dependen-cies, since all cameras
capture the same scene from differ-ent viewpoints. These can be
exploited for combined tem-poral/inter-view prediction, where
images are not only predicted from temporally neighboring images
but also from corresponding images in adjacent views, referred to
as Multiview Video Coding (MVC). The overall structure of MVC
defining the interfaces is illustrated in Fig. 1.
In this paper, a typical stereoscopic video compression scenario
is mainly studied. The essential requirements are described in
Section II. Section III investigates coding of
The central requirement for any video coding standard is high

compression efficiency. In the specific case of MVC, this means
a significant gain compared to inde-pendent compression of
each view. Compression effi-ciency measures the tradeoff
between cost (in terms of bit-rate) and benefit (in terms of video
quality), i.e., the qual-ity at a certain bit-rate or the bit-rate at a
certain quality. However, compression efficiency is not the only
factor un-der consideration for a video coding standard. Some
re-quirements of a video coding standard may even be contradictory such as compression efficiency and low delay in some
cases. Then a good tradeoff has to be found. General
requirements for video coding such as minimum resource
consumption (memory, processing power), low delay, er-ror
robustness, or support of different pixel and color res-olutions,
are often applicable to all video coding standards.
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The main difference between classic video coding and

multiview video coding is the availability of multiple camera views of the same scene. As coding efficiency of hybrid video coding depends on the quality of the prediction
signal to a great extent, a coding gain can be achieved for
MVC by additional inter-view prediction. If there is no
such gain, independently encoding each camera view
with temporal prediction would already provide the best
pos-sible coding efficiency.
A. Disparity-Compensated Prediction
The distance between two points of a superimposed
ste-reo pair that correspond to the same scene point is
called disparity. Disparity compensation is the process
that es-timates this distance (disparity vector or DV),
predicts the right image from the left one and produces
their difference or residual image (disparity compensated
difference or DCD).
As a first coding tool for dependent views, the concept of
disparity-compensated prediction (DCP) has been ad-ded as
an alternative to motion-compensated prediction (MCP).
Here, MCP refers to inter-picture prediction that uses already
coded pictures of the same view at different time instance,
while DCP refers to inter-picture prediction

that uses already coded pictures of other views at the same

time instance.
B. Motion Homogeneity Determined
A region with homogeneous motion means that the mo-tions in
the region have homogenous spatial property, and the
corresponding motions in a spatial window are with consistence. A
uniform motion vector field at 4x 4 block level can be generated for
the calculation of motion homo-geneity in each MB. A Block
Matching Algorithm is a way of locating matching blocks in a
sequence of digital
video frames for the purposes of motion estimation. The purpose
of a block matching algorithm is to find a match-ing block from a
frame i in some other frame j, which may appear before or after i.
This can be used to discover tem-poral redundancy in the video
sequence, increasing the ef-fectiveness of the interframe video
compression and television standards conversion. Block matching
algorithms make use of an evaluation metric to determine whether a
given block in frame j matches the search block in frame i.
IV. PREDICTION STRUCTURES
The Diagonal inter-view prediction test mode. (b) Nor mal inter-view prediction test mode. (c) Simulcast test
But for the structure of DIP in Figure 2(a), the two views
can be decoded simultaneously, as the DIP reference pictures are always been decoded at the previous time slot.
When the number of views becomes very large, the NIP
will cause large decoding delay. As a result, the DIP or
the Simulcast coding mentioned above is a good structure
on the point of decoding delay removing and parallel
comput-ing.
Besides the fast algorithm described above, the

motion estimation process in the prediction stage can
be further speed up based on the motion correlation of
different frames. By considering two consecutive
frames of same view motion estimation can be done.
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To the fact that current existing prediction structures lack have

low coding efficiency a Diagonal Interview Pre-diction (DIP) is
presented in this paper, which performs the interview prediction
from the reference pictures of dif-ferent time slots to the encoding
picture. By introducing the DIP, a MVC prediction structure can
support the 3d view of rocketry, while raising the coding efficiency.
In comparison, the traditional interview prediction, in which the
reference picture of the coding picture, is noted as Normal Interview
Prediction (NIP). Figure 2 gives ex-amples of different prediction
structures.
Figure 2(a) shows a simple DIP case, in which the en-coding
picture is predicted from two reference pictures of the previous time
slot, in which one is a temporal refer-ence picture, and another one
is an spatial reference picture. Figure 2(b) shows a NIP case, in
which the encod-ing picture is then predicted from a temporal
reference picture and a spatial prediction reference picture but at
the same time slot to the encoding picture. In figure 2(c), the coding
picture is predicted from only one temporal refer-ence picture, and
views are encoded independently, such a coding structure is called
Simulcast coding.
Figure.2 Diagonal Inter-View Prediction Test Mode. (a)
In Figure 2(b) structure, the decoding of the current view has

one picture decoding delay compared with the reference view,
i.e. the decoding of picture (T,V) has to wait until the decoding of
picture (T,V-1) is finished.
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V. DEPTH PERCEPTION
In the MVC reference software JMVC, different mode
sizes including 16 16, 16 8, 8 16, 8 8, 8 4, 4 8,
and 4 4 are used in the prediction procedures. Large
sizes are usually selected for the macroblocks (MB) in the
regions with homogeneous motion, while small sizes are
selected for the MBs with complex motion. This technique
achieves the highest possible coding efficiency, but
results in extremely large encoding time which obstructs it
from practical use.
A depth map represents a relative distance from a camera to an object in the 3D space, it can be regarded as a
grayscale image using dark and bright values to represent far
and close object, and the object depth not only repres-ents
the physical object position in 3D space but also in-dicates
the motion activity of the object itself on the image plane.
Under the condition that cameras are set up in a close
parallelized structure, the depth maps are correlated to the
texture video motion fields.
People can see depth because they look at the 3D world
from two slightly different angles (one from each eye). Our
brains then figure out how close things are by determ-ining
how far apart they are in the two images from our

eyes. The idea here is to do the same thing with a com-puter.

The algorithm is based on Segment-Based Stereo Matching
Using Dissimilarity Measure.
The first step is to get an estimate of the disparity at each
pixel in the image. A reference image is chosen, and the other
image slides across it. As the two images slide over one
another we subtract their intensity values. Addi-tionally, we
subtract gradient information (spatial derivat-ives). We record
the offset at which the difference is the smallest, and call that
the disparity.
Next we combine image information with the pixel dis-parities
to clean up the disparity map. First, we segment the reference
image .Then, for each segment, we look at the associated pixel
disparities. Here assign each segment to have the median
disparity of all the pixels within that segment. This gives depth.
VI. CONCLUSION
In rocketry bandwidth is an essential requirement. To
achieve good coding efficiency redundancy within a frame
and redundancy between views are exploited. Here DE is
utilized to exploit inter-view dependencies in MVC.
REFERENCES
ISO/IEC/JTC1/SC29/WG11, Multiview Coding Us-ing
AVC, Bangkok, Thailand, Jan. 2006.
[1] U. Fecker,and A. Kaup, Statistical Analysis of
Multi-Reference Block Matching for Dynamic Light
Field Cod-ing, Proc. 10th International Fall Workshop
Vision, Mod-eling, and Visualization, pp. 445-452,
Erlangen, Germany, Nov. 2005.
[2] Advanced Video Coding for Generic Audiovisual
Services, Version 3, ITU-T Rec. & ISO/IEC 1449610 AVC, 2005.
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Although temporal prediction is on average the most efficient

mode in MVC system, there are many reasons for using both DE
and ME to achieve better predictions than using only ME. One
main reason is due to complex motion. In general, the temporal
motion cannot be char-acterized in an adequate way, especially
when there is non-rigid motion (such as zooming, rotational
motion, and deformations of non-rigid objects) or motion edge.
For the former, the ME based on the translational rigid motion
model of blocks fails for zooming, rotational motion and
deformation of non-rigid objects, and thus it produces poor
prediction results. For the latter, the re-gion with motion edges is
usually predicted using small block sizes with large motion
vectors and high residual energy, and thus it has low coding
efficiency. On the other side, usually the disparity which is mainly
determ-ined based on the relative positions of the objects and
cameras is more structured than the temporal motion in complex
motion region. MBs in region with complex motion are more likely
to choose the inter-view predic-tion mode. Thus, the

region with homogeneous motion is more likely to select
temporal prediction mode where inter-view prediction is
not needed, and the region with complex motion is more
likely to select inter-view pre-diction mode. The
comparative experimental results show that the proposed
algorithm not only significantly reduces the complexity of
MVD coding while improves the coding performance, but
also maintain the rendering quality.
www.ijert.org
[3] T. Wiegand, G. J. Sullivan, G. Bjntegaard, and A.

Lu-thra, Overview of the H.264/AVC video coding
standard, IEEE Trans. Circuits Syst. Video Technol.,
vol. 13, no. 7, pp. 560560, Jul. 2003.
[4] G. Sullivan and T. Wiegand, Video compression
From concepts to the H.264/AVC standard, Proc. IEEE,
Special Issue on Advances in Video Coding and
Delivery, vol. 93, no. 1, p. 18, Jan. 2005.

Enhanced Grid Synchronization of a DG system

based on Positive Sequence Estimation and Current
Control
S.Manoharan
Department of EEE,
K.L.N College of Engineering,
Madurai,Tamil Nadu, India
sharpmano@yahoo.com
Dr.K.Gnanambal
Department of EEE,
The grid synchronization techniques can be adversely

affected by the application of a disturbing influence (influence
quantity) on the electrical input signals. Due to the increase in
number of Distributed Generation (DG) Systems has lead to
complexity in control while integrating into grid. As a result
requirements of grid connected inverters have become stricter
to meet very high power quality standards.
Grid voltage conditions such as phase, amplitude and
frequency determine the proper operation of a grid connected
system. In such applications, a fast and accurate detection of
the phase angle, frequency and amplitude of the grid voltage is
essential. These factors, together with the implementation
simplicity and the cost are all important when examining the
credibility of a synchronization scheme. Therefore an ideal
phase-detection scheme must be used to promptly and
smoothly track the grid phase through various short-term
disturbances [3] [4] and long term disturbances to set the
energy transfer between the grid and the power converter.
One of the earliest methods used for tracking the phase
angle is Zero Crossing Detector (ZCD) method [5], but the
performance of ZCD is badly affected by power quality
phenomena [6]. The Linear PLL is mainly used to detect phase
for single phase supply. Use of voltage controlled oscillators
(VCOs) resulted in more rigid controllers such as the Phase
Locked Oscillator systems and the Charge-Pump PLLs.
However with the development of discrete devices such as
microcontrollers, various high performance synchronization
methods have been introduced.
The most recently proposed technique that can be used for
grid synchronization is the phase-locked loop (PLL); it is a
control system that generates an output signal whose phase is
related to the phase of an input "reference" signal [7].Some
significant applications are active power filters [8] [9],
uninterruptible power supplies [10], power-factor control [11],
[12], distributed power generation [13] and flexible ac
transmission systems [14]. Synchronous reference frame
phase-locked loops (SRF-s) are the most widely used systems
for synchronizing signals [15].
A fast and accurate estimation of fundamental positivesequence component [16] of grid voltage is essential for
different applications involving FACTS, power devices and
grid connected power converters. It is essential to estimate for
both monitoring and control in order to satisfy grid codes, and
to obtain high performance response.
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AbstractDistributed Generation (DG) System is a small

scale electric power generation which encompasses a wide
range of technologies such as wind energy, fuel cell, solar
power, micro turbines etc. Grid synchronization has been
identified as the most significant barrier to the control of
inverters connected to the grid. A Wind turbine based on
direct drive permanent magnet synchronous generator
(PMSG) is connected to the grid. The proper operation of grid
connected inverter system is determined by grid voltage
conditions such as phase, amplitude and frequency. A phaselocked loop (PLL) is used to track the phase angle in order to
improve the synchronization systems response in adverse grid
conditions. Using the enhanced synchronization structure the
fundamental positive-sequence component of grid voltages in
asymmetric and distorted three-phase systems is estimated.
The - stationary frame is used to obtain the pulsation for
grid inverter using a space vector pulse width modulation
(SVPWM) technique. The performance of the proposed
structure is verified through simulations using a grid set of
ideal and non-ideal grid conditions (three-phase voltage
unbalance, variation in frequency, variation in amplitude and
phase shift).The simulation results demonstrates that the
proposed method is very effective in digital structure
synchronization .
R.Girija
Department of EEE,
girija3.kln@gmail.com
KeywordsDistributed Generation (DG), permanent magnet

synchronous generator (PMSG), discrete phase-locked loop (PLL),
synchronization systems, positive-sequence component, SVPWM,
non-ideal grid conditions.
I.
INTRODUCTION
The Distributed Generation (DG) systems are highly

sporadic power generation system and their power output
depends heavily on the natural conditions. Wind power
generation based on direct drive permanent magnet
synchronous generator has received much attention due to its
self excitation capability and high efficiency operation [1].
Various grid code requirements must be met to connect the
DG systems with the utility grid. To ensure safe and reliable
operation of power system based on DG system [2], usually
power plant operators should satisfy the grid code
requirements such as fault ride through, power quality
improvement, grid synchronization, grid stability and power
control etc.
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10

This paper proposes an enhanced synchronization structure

based on PLL and fundamental positive-sequence components
which is used to synchronize the component of grid voltages in
three-phase systems that can include distorted and asymmetric
voltage terms. Finally, the performances of the digital
synchronization structure are investigated in the presence of
both ideal and non-ideal grid conditions such as amplitude
variation, frequency variation, phase jump and improper phase
shift. The analysis is carried out in MATLAB/SIMULINK
environment and the obtained results are discussed for
effectiveness of the study.
II.
OVERVIEW OF PROPOSED SYSTEM
A. Wind Turbine based DG

The PMSG-based wind turbine is fed to an ac-dc-ac
converter so as to maintain the ac output voltage at specified
frequency and amplitude. One of the main challenges is to
provide inverter control to present the customers with
balanced supply voltage. The wind speed is maintained
constant so as to keep the modulation index 1 in the load side
inverter.
D. Space vector pulse width modulation:

It is used for the control of pulse width modulation. To
implement space vector modulation a reference signal is
sampled with fundamental frequency. The reference signal
needed is generated from the Clarke transformation from three
phase voltage source.
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B. Synchronous reference frame based PLL

A phase-locked loop is a control system that generates an
output signal whose phase is related to the phase of an input
"reference" signal [6]. Frequency is the time derivative of
phase. Keeping both the input and output phase in lock step
implies keeping the input and output frequencies in lock step.
Consequently it can track an input frequency or it can generate
a frequency that is a multiple of the input frequency.
At present Synchronous Reference Frame PLL (SRF-PLL)
is the one of the most employed PLL topology. If the singlephase voltage input V, is an internally generated signal that is
a 90 degrees shifted version of V .The transformation blocks
changes the reference frame, bringing the voltages system
from an - stationary reference frame to a d-q rotating
synchronous reference frame.
The feedback loop controls the angular position of this d-q
reference frame. In particular the utility voltage vector is
totally lined up to the q-axis. In this way it coincides with all
its q-component; consequently the d-component is made equal
to zero. The q-component describes the voltage vector
amplitude course.
After studying the various Phase Locked Loop schemes
used today in modern power system, we observe that the
Synchronous Reference Frame PLL method provides a simple
yet effective way to measure the phase angle. In case of a
single phase system we obtain the quadrature signal by
delaying the available sinusoid or adopting some other similar
structure, however in 3 phase system this problem is greatly
reduced due to the availability of three phase shifted signals.
Hence by using arithmetic manipulation we obtain the
required orthogonal signal necessary for SRF-PLL
implementation.
response which will produce an output until it matches the

value of reference. There are two actions to be performed
namely proportional and integral action in the controller. The
proportional term control action is to simply proportional to
the control error. The proportional term output is given by
multiplying the error by a constant Kp(0.08) which is called
the proportional gain constant. The integral term objective in
PI controller is to eliminate control error in steady state. It
calculates and accumulates a continuous sum of the error
signal. The accumulated error is then multiplied by constant
Ki(200) which is called the integral gain constant and gives
the integral control output.
C. Current control with PI Regulator:

The PI controller is a linear controller and one of the most
common controllers used in control system. It is based on the
principal of control loop feedback. The error of the measured
and reference output signal is the function of the control
Fig. 1. Synchronization sytem structure
III.
PROBLEM FORMULATION
The operation of the proposed synchronized structure is

implemented by considering three phase supply voltage source
Va, Vb and Vc. In order to track the phase angle a discrete
three phase PLL is used. It controls the internal voltage
source. The output consists of estimated phase synchronous
angle and (sin , cos ) for the dq transformation blocks. In
steady state sin will be in phase with the fundamental
positive sequence of the -component. The PLL also measures
the frequency and generates a signal t locked on the variable
frequency of system voltage. The sin , cos values estimated
using the PLL are used to obtain d, q and zero components
using Park transformation.
I d 2 / 3( I a sin t I b sin(t 2 / 3) I c sin(t 2 / 3))
(1)
Iq 2 / 3( I a cos t I b cos(t 2 / 3) I c cos(t 2 / 3))
(2)
I 0 1/ 3( I a I b I c )
(3)
The current control is usually performed in a d-q synchronous
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11

reference frame. A distortion free, balanced, constant

magnitude three-phase voltage has d components only, while
the q and 0 components will be zero. Hence a reference
current for Iq is set zero. The controller gains calculated for
the PI regulator are Kp=0.08 and Ki=200. The output obtained
is again converted into Iabc using Park transformation. The
dq0_to_abc Transformation is commonly used in three-phase
electric machine models. It transforms three quantities such as
direct axis, quadratic axis and zero-sequence components. It is
also expressed in a two-axis reference frame back to phase
quantities. The following transformation is used:
I a I d sin(t ) I q cos(t ) I 0
2
2
I b I d sin(t ) I q cos(t ) I 0
3
3
2
2
I c I d sin(t ) I q cos(t ) I 0
3
3
Case test-5: Improper phase-shift is produced by having

constant frequency but not the proper phase shift of 120
relative to each other. A phase shift of 5 variation is applied
to the balanced three phase voltage. If you have an odd
number of affiliations, the final affiliation will be centered on
the page; all previous will be in two columns.
(4)
(5)
(6)
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Fig. 3. Simulated results for PLL output, grid voltage and current.
Fig. 2. Simulation model for positive sequence estimation and current

control.
A SVPWM is used to obtain the pulsation for the DC-AC

inverter with U and U as the reference signal obtained by
using Clark transformation.
(7)
U 2 / 3 * (Va 0.5Vb 0.5Vc )
U 2 / 3 * ( 3 / 2 * Vb
IV.
3 / 2 * Vc )
(8)
RESULT AND DISCUSSION
To verify the effectiveness of the proposed synchronization

system structure, some significant cases have been simulated
are performed using Matlab-Simulink software.
The main objective is to estimate the fundamental positivesequence component from the three phase supply voltages
which contains distortion asymmetries. The fundamental grid
frequency is 50 Hz and the sampling frequency used is 5 kHz.
1) Case test-1: The proposed structure is initially tested
with ideal condition without considering any distortion. The
grid positive sequence amplitude is set as 380V.
2) Case test-2: A three-phase voltage unbalance is applied
with a voltage reduction of 50V in each phase.
3) Case test-3: A three-phase frequency unbalance is
produced by a variation of 5Hz from the fundamental grid
frequency of 50Hz.
4) Case test-4: The amplitude is varied by 50V in phase-A
of the grid supply voltage.
Fig. 4. Simulated results for current control.
Waveforms presented in Figs. 5-9 show the simulated

output for the cases described. All of the cases first include
(top plot) the V and V that corresponds to the grid voltages
in the - frame. The central plots show the fundamental
positive sequence grid voltages V+ and V+ in the -
frame. The bottom plots show the phase angle of the
fundamental positive sequence of grid voltages.
Fig. 5. Simulated result for case 1 (ideal condition).
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12

Different non-ideal conditions were simulated and most

were handled well by the system. Unbalances in the three
phase input signals were overall handled well by the system.
The estimation of fundamental positive sequence component
and phase angle tracking was performed well by the system.
Although the system could handle the non-ideal cases fairly
well it was sometimes slow.
V.
Fig. 6. Simulated results for case 2 (Three phase voltage unbalance).
CONCLUSION
A PLL can be used to obtain magnitude, frequency and

phase information for estimation of fundamental positivesequence component of grid voltage. Accurate and fast
estimation of these quantities can be used for control and
protection of the system. Overall the wind turbine integrated
grid synchronization system based on positive-sequence
estimation is able to handle non-ideal conditions well. The
positive-sequence phase angle is tracked within acceptable
margins and therefore the PLL system as given with the
positive sequence estimation could indeed operate in a real life
application.
ACKNOWLEDGMENT
The authors are grateful to the principal and management of
K.L.N college of Engineering, Sivagangai for providing all
facilities for the research work
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Fig. 7. Simulated results for case 3 (Three phase frequency unbalance).
REFERENCES
C.N. Bhende, S.Mishra and Siva Ganesh Malla, Permanent magnet

synchronous generator-based standalone wind energy supply system,
IEEE Transactions on Sustainable Energy, vol. 2, no. 4, October 2011.
[2] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, Overview
of control and grid synchronization for distributed power generation
systems, IEEE Trans. Ind. Electron., vol. 53,no. 5, pp. 1398-1409,Oct.
2006.
[3] J. Svensson, Synchronisation methods for grid-connected voltage
source converters, Proc. Inst. Elect. Eng., vol. 148, no.3, pp.229235,May 2001.
[4] M. Karimi-Ghartemani and M. Iravani, A method for synchronization
of power electronic converters in polluted and variable-frequency
environments,IEEE Trans. Power syst., vol.19, no. 3,pp. 1263-1270,
Aug.2004.
[5] F. M. Gardner, Phase Lock Techniques. New York:Wiley, 1979.
[6] Francisco D. Freijedo, Jesus Doval-Gandoy, Oscar Lopez, Carlos
Martinez-Penalver, Alejandro G. Yepes, Pablo Fernandez-Comesana,
Andres Nogueiras, JanoMalvar, Nogueiras, Jorge Marcos and Alfonso
Lago, Grid-synchronization methods for power converters, Proc. Of
IEEE 35th Annual Conference on Industrial Electronics, IECON 2009,
pp. 522-529.
[7] FANG Xiong, WANG Yue, LI Ming, WANG Ke and LEI Wanjun,A
novel PLL for grid synchronization of power electronic converters in
unbalanced and variable-frequency environment, Proc. of IEEE
International Symposium on Power Electronics for Distributed
Generation Systems: pp. 466-471, 2010.
[8] C. Lascu, L. Asiminoaei, I. Boldea, and F. Blaabjerg, High
performance current controller for selective harmonic compensation in
active power filters, IEEE Trans. Power Electron., vol. 22,no. 5,pp.
1826-1835,Sep. 2007.
[9] M. Routimo, M. Salo, and H. Tuusa, Comparison of voltage-source
and current-source shunt active power filters, IEEE Trans. Power
Electron.,vol. 22, no. 2,pp. 636-643, March 2007.
[10] J. M. Guerrero, L. Hang, and J. Uceda, Control of dis tributed
uninterruptible power supply systems, IEEE Trans. Ind. Electron., vol.
55, no. 8,pp. 2845-2859, Aug. 2008.
[1]
Fig. 8. Simulated results for case 4(voltage unbalance).
Fig. 9. Simulated results for case 5(Improper phase shift).
www.ijert.org
13

[15] A. Timbus, M. Liserre, R. Teodorescu, P. Rodriguez, and F. Blaabjerg,

Evaluation of current controllers for distributed power generation
systems, IEEE Trans. Power Electron., vol. 24,no. 3,pp. 654-664,Mar.
2009.
[16] Pedro Roncero-Sanchez, Xavie del Toro Garcia, Alfonso Parreno
Torres, and Vinvente Feliu, Fundamental positive-and negativesequence estimator for grid synchronization under highly disturbed
operating coditions, IEEE Trans. Power Electronics., vol. 28, no.8,
August. 2013.
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[11] A. I. Maswood and F. Liu, A unity-power-factor converter using the

synchronous-reference-frame-based hysteresis current control, IEEE
Trans. Ind. Appl., vol. 43,no. 2, pp. 593-599, Mar./Apr. 2007.
[12] B.Wang, G. Venkataramanan, and A. Bendre, Unity power factor
control for three-phase three-level rectifiers without current sensors,
IEEE Trans. Ind. Appl., vol. 43, no. 5,pp.1341-1348, Sep./Oct.2007.
[13] T. Ahmed, K. Nishida, and M. Nakaoka, A novel stand-alone induction
generator system for AC and DC power applications, IEEE Trans. Ind
Appl., vol. 43, no. 6, pp. 1465-1474, Nov./Dec.2007.
[14] H. Awad, J. Svensson, and M. J. Bollen, Tuning software phase-locked
loop for series-connected converters, IEEE Trans. Power Del., vol. 20,
no. 1,pp. 300-308, Jan.2005.
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14

Reduction of Lower Order Harmonics in a Gridconnected Single-phase PV Inverter Using Adaptive

Harmonic Compensation Technique
#1
#2
Ananda Raj. A.J

Final Year Student,Department of EEE,
Valliammai Engineering College,
Chennai, India
Anandrajaj9@gmail.com
Pratheebha. J,
Assistant Professor,Department of EEE,

Valliammai Engineering College,
Chennai, India
pratheebha87@gmail.com
The objective of the paper is to mitigate the lower order

harmonics in this system. The system will not have any lower
order harmonics in the ideal case. However, harmonics are
generated due to the following aspects: distorted magnetizing
current drawn by the transformer due to the nonlinearity in the
BH curve of the transformer core, the dead time introduced
between switching of devices, on-state voltage drops on the
switches, distortion in the grid voltage etc.
Harmonics have a negative impact on distribution networks
and influence the behaviour of system components and loads:
For example, conductors suffer from losses and skin effects,
eddy current losses can have detrimental effects on
transformers, with consequent equipment overheating,
capacitors may be affected by resonance phenomena with
potential breakdown, and machines can suffer from vibration
phenomena.
These harmonics need to be mitigated so that the PV
inverter meets standards such as IEEE 519-1992 and IEEE
1547-2003. This paper focuses on the design of an inverter
current control to achieve a good attenuation of the lower
order harmonics.
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Abstract This paper proposes a novel inverter current control

method to mitigate lower order harmonics in a single-phase gridconnected photovoltaic (PV) inverter. The circuit under
consideration is composed of a PV array, a boost section, a singlephase inverter with an inductive filter and a step-up transformer
interfacing the grid or the load. The lower order harmonics,
which may be caused by non-ideal factors such as distorted
magnetizing current in transformer due to core saturation, dead
time of inverter, on-state voltage drops in switching etc., need to
be eliminated in order for the PV inverter to meet IEEE
standards. An inverter current control technique, wherein a
modification to the conventional PR controller (proportionalresonant controller) is done is put forward. This novel controller,
named as proportional-resonant-integral (PRI) controller,
eliminates the dc component in the control system, which
introduces even harmonics in the grid current. An adaptive
harmonic compensation technique, which makes use of an LMS
adaptive filter to eliminate a particular harmonic component in
the output current, is proposed for the lower order harmonic
compensation. The complete design has been validated with
simulation results and the THD of the output voltage/ current
waveforms has been found to be in conformance with the IEEE
standards.
Keywordsodd and even harmonics, MPPT algorithm, boost
converter, PRI controller, THD
I.
INTRODUCTION
In recent years, distributed generation (DG) systems have

started making use of renewable energy sources owing to the
depletion of conventional energy sources. Distributed
generation allows collection of energy from many sources and
may give lower environmental impacts and improved security
of supply. In this paper, a system utilizing solar energy as the
source and a photo-voltaic inverter to supply the power
generated to the grid is elucidated. The topology of the solar
inverter system[1] consists of the following three power circuit
stages:
1) a boost converter stage to perform maximum power
point tracking (MPPT)
2) a low-voltage 2-bridge VSI inverter
3) an inductive filter and an RL load
Fig.1: Schematic diagram of the circuit

Fig.1 shows the circuit block diagram of a single phase grid
connected PV inverter. The DC output from the solar array is
boosted using MPPT scheme. The goal of MPPT technique is
to automatically find the voltage VMPP or current IMPP at which
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15

a PV array should operate to obtain the maximum power

output PMPP under a given temperature and irradiance. The
boost converter stage employs duty ratio control during
MPPT.
Fig. 2 Power Circuit Topology of single-phase PV System
1) Odd Harmonics: The following are the primary causes for

the lower order odd harmonics:
Distorted magnetizing current drawn by the
transformer due to the nonlinear characteristics of the
BH curve of the core
Inverter dead time[2] (proportional to the dead time,
switching frequency, and the dc bus voltage)
Semiconductor device voltage drops
Distortion in the grid voltage
Voltage ripple in the dc bus
2) Even Harmonics: The system is susceptible to the presence
of dc offset in the inverter terminal voltage. The dc offset is
caused by one or more of the following factors:
Varying power reference given by a fast MPPT block
Offsets in the A/D converter and the sensors.
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Fig.2 shows the power circuit topology of a single-phase

PV inverter connected to a grid. The controller employed here
is a PRI (proportional-resonant-integral) controller. This is a
modification to the conventional PR (proportional-resonant)
controller wherein any dc offset in a control loop will
propagate through the system and results in drawing of even
harmonics from the grid. Thus, an integral block is used along
with the PR controller to ensure that there is no dc in the
output current of the inverter. This would automatically
eliminate the even harmonics. The complete scheme is
verified experimentally and the results show a good
correspondence with the analysis.
The organization of this paper is as follows: Section II
discusses the sources of lower order harmonics in the system.
Section III explains the MPPT algorithm used, Section IV
about the design of fundamental current control using a PRI
controller. In Section V, design of the system using MATLAB
and the simulation results are elucidated. In Section VI, the
hardware details are provided. Conclusions are given in
Section VII.
They occur as integral multiples of the fundamental frequency.

As the frequency increases, the magnitude decreases
gradually, thus making the lower order harmonics the most
predominant and harmful.
For instance, the third harmonic causes a sharp increase
in the zero sequence current, and therefore increases the
current in the neutral conductor. This effect can require special
consideration in the design of an electric system to serve nonlinear loads.
The origin of odd and even harmonics is discussed below:
II.
C.Evaluation of harmonics:
Harmonics can be quantified using the Fourier series. It
provides a mathematical analysis of distortions to a current or
voltage waveform. Based on Fourier series, harmonics can
describe any periodic wave as summation of simple sinusoidal
waves which are integer multiples of the fundamental
frequency.
The harmonic voltage amplitude for a hth harmonic can
be expressed as
where
LOWER ORDER HARMONICS
A. Harmonics
Harmonics are electric voltages and currents that appear
on the electric power system as a result of non-linear electric
loads. When a non-linear load is connected to the system, it
draws a current that is not sinusoidal. These result in
distortions, termed as harmonics. Harmonic frequencies in the
power grid are a frequent cause of power quality problems.
Some of the major effects of power system harmonics are:
increases the current in the system.
causes poor power factor
transformer and distribution equipment overheating
sensitive equipment failure
B. Lower order harmonics
Harmonics are steady-state distortions to current and
voltage waves and repeat every 50 hertz or 60 hertz cycle.
td is the dead time,

Ts is the device switching frequency, and
Vdc is the dc bus voltage
III.
MPPT ALGORITHM
Maximum power point tracking (MPPT) is a technique

that grid connected inverters, solar battery chargers and
similar devices use to get the maximum possible power from
one or more photovoltaic devices, typically solar panels. Solar
cells have a complex relationship between solar irradiation,
temperature and total resistance that produces a non-linear
output efficiency which can be analyzed based on the I-V
curve. It is the purpose of the MPPT system to sample the
output of the cells and apply the proper resistance (load) to
obtain maximum power for any given environmental
conditions. MPPT devices are typically integrated into
an electric power converter system that provides voltage or
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IV.
DESIGN OF PRI CONTROLLER
This controller uses three blocks- a proportional controller,

a resonant controller and an integral controller.
A proportional
control system
is
a
type
of
linear feedback control system. In the proportional control
algorithm, the controller output is proportional to the error
signal, which is the difference between the set point and
the process variable. In other words, the output of a
proportional controller is the multiplication product of the
error signal and the proportional gain.
The addition of a resonant block results in a PR controller.
For low order harmonic compensation, PR controllers are
good alternatives to PI(proportional-integral) controller,
especially in grid-connected distributed generation systems.
PR filters can be used for generating the harmonic command
reference precisely in an active power filter and for
implementing selective harmonic compensation.
Yet another development has been made in the controller
by the inclusion of an integral block. If the main controller
used is a PR controller, any dc offset in a control loop will
circulate through the system and the inverter terminal voltage
will have a nonzero average value. The integral block ensures
that there is no dc in the output current and eliminates the even
harmonics.
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current conversion, filtering, and regulation for driving various

loads.
Tracking the maximum power point (MPP) of a
photovoltaic (PV) array is a crucial part of a PV system. Many
MPP tracking (MPPT) algorithms have been developed and
implemented. In this paper, the Perturb and Observe (P&O)
algorithm is made use of. That is, in this system, a PV array is
connected to a power converter. Thus, perturbing the duty
ratio of power converter perturbs the PV array current and
consequently perturbs the PV array voltage.
The graphical representation of the algorithm is shown in
Fig 3. It is clear from the graph that incrementing the voltage
increases the power when operating on the left of the MPP
(maximum power point) and decreases the power when on the
right of the MPP. Therefore, if there is an increase in power,
the subsequent perturbation should be maintained to reach the
MPP and if there is a decrease in power, the perturbation must
be reversed.
Fig. 3: P&O algorithm graphical representation
The process is repeated periodically until the MPP is

reached. The system then oscillates about the MPP. The
oscillation can be minimized by reducing the perturbation step
size.The block of MPPT used in the MATLAB simulink is
shown in Fig.4
Fig.5: Block diagram of the fundamental current

control with the PRI controller.
The transfer function of the PR controller is:
The plant transfer function is formed as
Fig. 4: MPPT block in MATLAB
where Vdc is the gain of inverter to the voltage reference

generated by the controller impedance (Rs + sLs ) is the
impedance offered by the controller given in s-domain.
Rs and Ls are the net resistance and inductance referred to the
primary side of the transformer, respectively.
Ls includes the filter inductance and the leakage inductance of
the transformer.
Rs is the net series resistance due to the filter inductor and the
transformer.
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17

First, a PR controller is designed for the system assuming

that the integral block is absent, i.e., KI = 0. Design of a PR
controller is done by considering a PI controller in place of the
PR controller.
V.
SIMULATION RESULTS
TABLE I
PV INVERTER PARAMETERS
With the PI controller as the compensator block in Fig. 4 and

without integral block, the forward transfer function will be
Parameter
Meaning
Value
Vdc
1:n
DC bus voltage
Transformer turns ratio
Bandwidth of current
controller
Net series resistance referred
to primary
Net series inductance referred
to primary
40 V
1:15
wbw
Rs
The closed-loop transfer function for Fig. 4 is given by
Ls
Without the integral block, the closed-loop transfer function

would be
S1-S4, Sboost
Power MOSFETs
Cdc
fsw
Kp
Kr
KI
DC bus capacitance
Device switching frequency
Proportional term
Resonant term
Integral term
Gain in harmonic
compensation block
Time constant
Kadapt
Ta
where
M = Vdc/Rs and T=Ls/Rs
0.28
1.41 mH
IRF
Z44(VDS,max=60V,
ID,max=50A)
6600 F, 63V
40 kHz
3
594
100
25.6
0.03s
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Now the plant transfer function is,
84.8 X 103 rad/s
The model of PRI controller used in the simulation is

shown in Fig.6.A discrete virtual PLL controller is used in
addition to the PRI controller for the sinusoidal waveform.
The circuit topology was built in laboratory for a max

power rating of 150W. The various power circuit and control
circuit parameters are listed in Table II. All the design related
plots and the simulation result have the parameters as listed in
Table II.
Fig.7. shows the grid connected single-phase PV inverter
using MATLAB Simulink
Fig.7. Grid connected single-phase PV Inverter

Fig.6: PRI Controller block using MATLAB
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18

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From the simulation the output voltage waveform from

the solar panel is shown in Fig.8.And by implementing the
Maximum Power Point Tracking Techinque the output voltage
from the inverter is boosted to the maximum voltage and is
shown in Fig.9.
Fig.10. AC output voltage with the load connected to

grid.
Fig.8. PV voltage with the load .This is the dc output

voltage from the solar panel.
A. FFT Analysis with load

This is the fast fourier transform analysis for the
given circuit. Here it is seen that the harmonics value is
reduced and the THD is only 1.30%
Fig 9. Boosted output DC voltage waveform.

This boosted (i.e.,) Maximum power is passed to the filter
to remove the harmonic content. Harmonic of high frequency
will be eliminated using the filter. The ac voltage from the
transformer is shown in Fig.10.The r.m.s voltage of the output
voltage is 230V .is connected to the grid.This voltage is free
from lower order harmonics.
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19

Fig 12. Hardware setup
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Fig. 11: FFT Analysis of output voltage.
The above Fig.11 shows the FFT analysis for the output
voltage waveform in the grid where the load is connected. The
Total Harmonic Distortion is found to be 1.30% for 5 cycles
and this is within the IEEE standard. Thus the quality of
power is improved and the lower order harmonics are reduced.
VI.
A. Specifications
Transformer
MOSFET switches
Inductor
Capacitors
PN junction diodes
Microcontroller
Voltage sensors
Current sensors
MOSFET driver&
Optocoupler
Fig 13. Output Voltage waveform

VII. CONCLUSION
HARDWARE DETAILS
230/15v step-down transformer

IRF840 (400v, 5A)
47microH, 10mH, 100microH
1000F, 2200 F, 10 F, 0.01 F
1N4007
dsPIC33FJ64MC802
15v/5v (potential divider type)
ACS714(hall effect sensor)
IRS2110
B. Hardware snapshots
The hardware setup of a single-phase PV inverter
connected to RL load is shown in Fig. 12. The MOSFET
IRF840 of voltage rating 400V and current rating 5A is taken.
Peripheral Integral Controller of 33FJ64 family is used. In the
driver circuit, IRS2110 has been used. The value of the
resistance is 50 Ohm and inductor 1 mH respectively. The
output voltage across the load RL is shown in Fig. 13.
Modification to the inverter current control for a grid

connected single-phase photovoltaic inverter has been
proposed in this paper, for ensuring high quality of the current
injected into the grid. For the power circuit topology
considered, the dominant causes for lower order harmonic
injection are identified as the distorted transformer
magnetizing current and the dead time of the inverter. It is also
shown that the presence of dc offset in control loop results in
even harmonics in the injected current for this topology due to
the dc biasing of the transformer. A novel solution is proposed
to attenuate all the dominant lower order harmonics in the
system. The estimated current is converted into an equivalent
voltage reference using a proportional controller and added to
the inverter voltage reference. The design of the gain of a
proportional controller to have an adequate harmonic
compensation has been explained. To avoid dc biasing of the
transformer, a novel PRI controller has been proposed and its
design has been presented. The interaction between the PRI
controller and the adaptive compensation scheme has been
studied.
It is shown that there is minimal interaction between
the fundamental current controller and the methods
responsible for dc offset compensation and adaptive harmonic
compensation. The PRI controller and the adaptive
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20

compensation scheme together improve the quality of the

current injected into the grid. The complete current control
scheme consisting of the adaptive harmonic compensation and
the PRI controller has been verified experimentally and the
results show good improvement in the grid current THD once
the proposed current control is applied.
The transient response of the whole system is studied
by considering the startup transient and the overall
performance is found to agree with the theoretical analysis. It
may be noted here that these methods can be used for other
applications that use a line interconnection transformer
wherein the lower order harmonics have considerable
magnitude and need to be attenuated.
REFERENCES
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[1] S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, A review of

single-phase grid-connected inverters for photovoltaic
modules, IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 1292
1306, Sep./Oct. 2005.
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compensation of deadtime effects in PWM inverters, IEEE
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[4] A. R.Munoz and T. A. Lipo, On-line dead-time
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[5] A. C. Oliveira, C. B. Jacobina, and A. M. N. Lima,
Improved dead-time compensation for sinusoidal PWM
inverters operating at high switching frequencies, IEEE
Trans. Ind. Electron., vol. 54, no. 4, pp. 22952304, Aug.
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[6] L. Chen and F. Z. Peng, Dead-time elimination for
voltage source inverters,IEEE Trans. Power Electron., vol.
23, no. 2, pp. 574580, Mar. 2008.
[7] IEEE Recommended Practices and Requirements for
Harmonic Control in Electrical Power Systems, IEEE
Standard 519-1992, 1992.
[8] IEEE Standard for Interconnecting Distributed Resources
With the Electric Power System, IEEE Standard 1547-2003,
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[9] T. Esram and P. L. Chapman, Comparison of photovoltaic
array maximum power point tracking techniques, IEEE
Trans. Energy Convers., vol. 22, no. 2, pp. 439449, Jun.
2007.
[10] R. Kadri, J.-P. Gaubert, and G. Champenois, An
improved maximum power point tracking for photovoltaic
grid-connected inverter based on voltage-oriented control,
IEEE Trans. Ind. Electron., vol. 58, no. 1,pp. 6675, Jan.
2011.
[11] T. Kitano, M. Matsui, and D. Xu, Power
sensorlessMPPT control scheme utilizing power balance at
DC linkSystem design to ensure stability and response, in
Proc. 27th Annu. Conf. IEEE Ind. Electron. Soc., 2001, vol. 2,
pp. 13091314.
[12] Y. Chen and K. M. Smedley, A cost-effective singlestage inverter with maximum power point tracking, IEEE
Trans. Power Electron., vol. 19, no. 5, pp. 12891294, Jun.
2004.
[13] Q. Mei, M. Shan, L. Liu, and J. M. Guerrero, A novel
improved variable step-size incremental-resistance MPPT
method for PV systems, IEEE Trans. Ind. Electron., vol.
[14] A. K. Abdelsalam, A. M. Massoud, S. Ahmed, and P. N.
Enjeti, High-performance adaptive perturb and observe
MPPT technique for photovoltaic-based microgrids, IEEE
Trans. Power Electron., vol. 26, no. 4, pp. 10101021, Apr.
2011.
[15] P. Mattavelli, A closed-loop selective harmonic
compensation for active filters, IEEE Trans. Ind. Appl., vol.
37, no. 1, pp. 8189, Jan./Feb. 2001.
[16] X. Yuan, W. Merk, H. Stemmler, and J. Allmeling,
Stationary-frame generalized integrators for current control
of active power filters with zero steady-state error for current
harmonics of concern under unbalanced and distorted
operating conditions, IEEE Trans. Ind. Appl., vol. 38, no. 2,
pp. 523532, Mar./Apr. 2002.
[17] J. Allmeling, A control structure for fast harmonics
compensation in active filters, IEEE Trans. Power Electron.,
vol. 19, no. 2, pp. 508514, Mar. 2004.
[18] C. Lascu, L. Asiminoaei, I. Boldea, and F. Blaabjerg,
High performance current controller for selective harmonic
compensation in active power filters, IEEE Trans. Power
Electron., vol. 22, no. 5, pp. 18261835, Sep. 2007.
[19] D. De and V. Ramanarayanan, A proportional +
multiresonant controller for three-phase four-wire highfrequency link inverter, IEEE Trans. Power Electron., vol.
25, no. 4, pp. 899906, Apr. 2010.
[20] R. Cardenas, C. Juri, R. Penna, P.Wheeler, and J. Clare,
The application of resonant controllers to four-leg matrix
converters feeding unbalanced or nonlinear loads, IEEE
Trans. Power Electron., vol. 27, no. 3, pp. 1120 1128, Mar.
2012.
[21] A. G. Yepes, F. D. Freijedo, O . Lopez, and J. DovalGandoy, Highperformance digital resonant controllers
implemented with two integrators, IEEE Trans. Power
Electron., vol. 26, no. 2, pp. 563576, Feb.2011.
[22] A. G. Yepes, F. D. Freijedo, J. Doval-Gandoy, O. Lopez,
J. Malvar, and P. Fernandez-Comesana, Effects of
discretization methods on the performance of resonant
controllers, IEEE Trans. Power Electron., vol. 25, no. 7, pp.
16921712, Jul. 2010.
[23] P. Mattavelli and F. P.Marafao, Repetitive-based control
for selective harmonic compensation in active power filters,
IEEE Trans. Ind. Electron., vol. 51, no. 5, pp. 10181024,
Oct. 2004.
[24] R. Costa-Costello, R. Grino, and E. Fossas, Oddharmonic digital repetitive control of a single-phase current
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10601068, Jul. 2004.
[25] S. Jiang, D. Cao, Y. Li, J. Liu, and F. Z. Peng, LowTHD, fast-transient, and cost-effective synchronous-frame
repetitive controller for three-phase UPS inverters, IEEE
Trans. Power Electron., vol. 27, no. 6, pp. 29943005, Jun.
2012.
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21

Rapid Tracking of MPPT with Buck-Boost

Converter
#1
#2
Subash.T,
Department of EEE, Paavai Engineering College,
Namakkal, Tamilnadu,India
1
subash.trk.@live.com
solar panel has to be modeled by having the constant values like

Energy gap(Eg), Boltzmann constant (K), Electron charge(q) ,
by having the values of these constant the solar panel has been
programmed by giving the temperature and luminance the
current has been obtained as output , by having the
PowerElectronic circuit the voltage is obtained and is given
back to the Solar panel. The solar panel has to be placed in such
a way that the maximum area of the panel exposed to sunlight.
II. MANUSCRIPTS
A. Characteristics of Photovoltaic Arrays
Solar cells are basically p-n junction semiconductors which
transform solar energy into electricity directly. Figure .1 shows
an equivalent circuit of a solar cell , in which Rshand Rsare the
intrinsic shunt and serial resistances of the cell, respectively. A
current source Iphrepresents the cell photocurrent, which is a
function of irradiation Si and PV array temperature (T), and
can be expressed
IJE
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Abstract The power obtained from the sun through the solar
panel is the research work performed in this paper, to extract the
power effectively i.e up to the benchmark of the solar panel
capacity, the effective maximum power point technique (MPPT)
needs to be implemented. there are three types of algorithms
available they are Po, Incremental conductance algorithm . In
this proposed work, a combination of linear approximation and
PO Algorithm to achieve maximum-power-point tracking (MPPT)
for PV arrays is proposed. The LA is based on that the
trajectories of maximum power point varying with temperature
are approximately linear. With theLA a maximum power point
can be determined very closer. Moreover,. In the paper a
corresponding LA is made by coding in the panel design which is
simple. As a result, the proposed circuit is cost-effective and can
be with PV arrays easily. Therefore the fluctuations in the steady
state can be minimized .And by using Buck-Boost converter the
voltage has been maintained in the desired level, by having both
combination of step-up and step-down process. The proposed
MPPT method has advantages of faster tracking fewer fluctuation
and higher accuracy over the conventional methods.
Thinesh.S,
Department of EEE, Paavai Engineering College,
Namakkal, Tamilnadu,India
Key words:PVarray,MPPT, LA, Buck-Boost Converter, Mosfet
I. INTRODUCTION
Photovoltaic is the technology that uses solar cells or an array
of them to convert solar energy directly into electricity .The
power produced by the array of depends directly from the
factors that are not controlled by the human being as the cell
temperature and solar irradiance. Usually the energy generated
by the cell is used to provide electricity to a load and
remaining energy is saved into batteries. An efficient
Maximum Power Point Tracking (MPPT) algorithm is
important to increase the output efficiency of a photovoltaic
(PV) generate system. The conventional method have some
problems in that it is impossible to quickly acquire the
generation power at the maximum power (MP) point, i.e., the
efficiency of electric power generation is very low, and the
amount of electric power generated by solar cell is always
changing with weather conditions. Normally, the different
solar cells have different diode factor (n) and reverse saturation
current 0 . MPPT refers to maximum power point technique
where the maximum power can be
extracted. Here the
technique adopted is combination of LA & PO algorithm.
The MPPT maximizes the energy that can be transferred from
the array to an electrical system. Its main function is to adjust
the panel output voltage to a value at which the panel supplies
the maximum energy to the load. Most current designs consist
of three basic components: a switch-mode dcdc converter, a
control, and tracking section. The Solar panel has been designed
with proper selection of number of series and parallel cells the
no of cells to be used is calculated as per the ratings by which
= + /100
Where
is the short-circuit current at reference temperature
and reference irradiation (100mW/
is temperature coefficient of the short-circuit current
represents the reversed saturation
expresses the p-n junction of a solar cell

is its nonlinearresistance.
exp
where
Irris the corresponding reversed saturation current at Tr
is the band-gap energy of the semiconductor in the cell
q is charge of an electron (1.61019 C)
k is Boltzmanns constant (1.38 1023 J/ K )
A is the ideality factor of the p-n junction
characteristic of PV arrays can be represented by the following

equations
= - exp
=
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22

B.Proposed Block Diagram
Fig.1Proposed Block Diagram
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The Proposed Block diagram denotes the operation of the

work proposed in this paper, which is having the details of the
components used.The Solar Panel from which the power has to
be extracted is modeled as per the requirement; but
unfortunately the entire power up to the benchmark of the Solar
panel will not be extracted .to extract the power completely, the
MPPT Technique has been used. To have the MPPT
Design ;the voltage and current from the solar panel has been
measured ,by having the voltage and current as the reference
the MPPT algorithmwhich is namely Perturbation &
Observation has been designed as a programming and from the
algorithm, has been obtained . and given to PWM as a
Signal and from the PWM the gate Pulses has been given to the
Mosfet of the Buck-Boost Converter, according to the gate
pulse applied the mosfet will work.
Then, the difference I between PV output current and First,

the approximated line of MPPs can be determined from the electrical
parameters of PV arrays. The reference command of current can
be determined according to the approximated line and the measured
PV voltage and current. can be calculated to modulate the duty-cycle
Dnew of gate-driving signal. When the magnitude of I is small
enough, it means the OP is very close to the actual MPP. The control
algorithm switches to the P&O method with fine perturbation-steps so
that the OP can dynamically track the accurate MPP. If there are
rapidly climate changes occurring, the magnitude of I will become
large again. Therefore, the control algorithm needs to switch back to
the LA method.
TABLE I
DESIGN SPECIFICATION FOR PROPOSED METHOD
S.No
1
Particular
Value
Maximum Power (Pmpp)
49 W
Voltage at Maximum power (Vmpp)
17.3 V
Current at Maximum power (Impp)
4.41 A
Open - Circuit Voltage (Voc)
21.4 V
Short Circuit Current (Isc)
4.96 A
Fig 3:Flow Chart of Combined Linear Approximation And Perturbation and

Observation Method
C. Combined L A & PO Method
D.Simulation Results
The flowchart for the proposed MPPT algorithm is shown in Fig3,

which is the combination of LA and P&O methods.First, the
approximated line of MPPs can be determined from the electrical
parameters of PV arrays. The reference command of current Iref can
bedetermined according to the approximated line and the measured
PV voltage and current.
Fig 4 shows the waveforms of PV output voltage, currentand power,

while the proposed system operates at theconditions of 60mW/cm2
and 50oC. It can be seen that thecorresponding MPP can be rapidly
and exactly achieved, whichreally proved the feasibility of the
proposed MPPT method.
The graphs obtained at Various temperatures are displayed
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23

I..References
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Fig 4 PV output voltage, currentand power, while the proposed

system operates at theconditions of 60mW/cm2 and 50oC.
[1] Chien-Hsuan Chang, Chun-An Cheng, Hung-Liang Cheng, FangYing Liu, and Ping-Feng Lee[2013]Design and Implementation of
the Improved MPPT Method with Rapidly TrackingFeature
[2] Emil.A.Jimenez Brea, EduradoI.Oritz-Rivera [2007] Dynamic
Maximum Power Point Tracker using Sliding Mode Control
[3] Emil.A.Jimenez Brea, Edurado I.Oritz-Rivera [2010] Simple
Photovoltaic Solar cell using sliding mode controlled Maximum
Power Point tracker for Battery charging Application
[4] Guan-Chyun,Hung-IHseih, Cheng-Yaun Tsai [2012] Photovoltaic
Power-Increment-Aided Incremental Conductance Mppt With TwoPhased Tracking
[5] Hanju Cha, Sangohey Lee [2008]Design and Implementation of
Photovoltaic Power Conditioning System using a Current based
Maximum Power Point Tracking
[6] SachinJain, Vivek Agarwal [2007]A Single Stage Grid
Connected Inverter Topology for Solar PV Systems With Maximum
Power Point Tracking
[7] KK.Tse, M.T.HO, Henry S. [2002] A Novel Maximum Power
Point Tracker for PV Panels Using Switching Frequency Modulation
[8] A.Yazidi, F.Betin[ 2006]Low Cost two axis Solar tracker with
High precision positioning
[9] Numerical Methods with Program in C
T.Veerarajan.
T.Ramachandram TataMcGraw Hill Education Private Limited
[10]. Power Electronics Circuits, Devices and Applications
Muhammad H.Rashid Third Edition
Pearson Prentice Hall
Publication
[11] M. A. G. de Brito, L. Galotto, L. P. Sampaio, G. de Azevedo e
Melo, and
C. A.Canesin, Evaluation of the Main MPPT Techniques for
Photovoltaic Applications, IEEE Trans. Ind. Electron., vol. 60, no.
3,pp. 1156--1167, Mar. 2013.
[12] A. Pandey, N. Dasgupta, and A. K. Mukerjee, A simple singlesensor MPPT solution, IEEE Trans. Power Electron., vol. 22, no. 6,
pp. 698-- 700, Mar. 2007.
[13] W. Li, Y. Zheng, W. Li, Y. Zhao, and X. He, A smart and
simple PV charger for portable applications, in Proc. Applied Power
ElectronicsConference and Exposition (APEC), 2010, vol. 25, pp.
20802084.
[14] N. Femia, G. Petrone, G. Spagnuolo, and M.Vitelli,
Optimization of Perturb and observe maximum power point tracking
method, IEEETrans. Power Electron., vol. 20, no. 4, pp. 963--973,
Jul. 2005.
[15] T. Esram and P. L. Chapman, Comparison of photovoltaic array
Maximum Power Point Tracking Techniques, IEEE Trans.
EnergyConverse., vol. 22, no. 2, pp. 439--449, Jun. 2007.
[16] A. K. Abdelsalam, A. M. Massoud, S. Ahmed, and P.N.Enjeti,
High-performance adaptive perturb and observe MPPT technique for
Photovoltaic-based micro grids, IEEE Trans. Power Electron., vol.
26, no. 4, pp. 1010--1021, Apr. 2011.
[17] C.-L. Shen, Y.-E. Wu, and F.-S. Liu, A double-linear
approximation algorithm to achieve maximum-power-point tracking
for PV arrays, inProc. International Conference on Power
Electronics and Drive Systems,(PEDS), 2009, pp. 758763.
Fig 5: PV output voltage, currentand power, while the proposed

system operates at the conditions of 80mW/cm2 and 25oC
Fig 6: PV output voltage, currentand power, while the proposed

system operates at the conditions of 60 mW/cm2 and 50oC
E. Conclusion
The proposed work has been done by using an improved LA and
PO methods for photovoltaic system .The LA method rapidly takes
the operation point to a rough MPP, and then the P&O method
continuously tracks the exact MPP with fine perturbation steps The
proposed MPPT method has the advantage of faster tracking fewer
fluctuations, and higher accuracy over the conventional methods. By
replacing the Boost Converter with Buck-Boost converter the output
voltage of the PV array which is dependent of temperature may
produce higher or lower voltages, so to have both step-up and stepdown processes are done
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24

An Improved Transformerless High Step-Up

DC-DC Converter Using a 4 Level Stacked Voltage
Multiplier
#1
#2
U.Sam Richards,
C.Saravanan,
#Department of EEE, Paavai Engineering College,

Namakkal.
2
saravananchinnusamypec@paavai.edu.in
Abstract-This
paper
proposes
animproved
Transformerless high step-up dc-dc converterusing a 4
level stacked voltage multiplier. The multiplying of
voltage is done using stacked voltage multiplier; the low
DC voltage has been multiplied to obtain high DC
voltage. The Stacked cascaded voltage multiplier is a two
4 stage voltage multiplier which is designed and
implemented based upon the Cockcroft Walton voltage
multiplier. Two independent frequencies are used for the
control strategy, one high frequency is used to minimize
the size of the inductor and one low frequency is used
according to the desired output voltage. The high voltage
is obtained from a very low DC voltage. The obtained
output is given to a DC motor. The voltage ripples
produced during the motor operation is reduced in this
proposed method. The Simulated motor output of the
proposed converter is compared with the conventional
converter, the results illustrates that the stacked
cascaded voltage multiplier gives better dynamic
performance and it can be used for high voltage
industrial applications.
uninterruptible power supplies [9]. Theoretically, the

conventional boost dc-dc converter can provide a very high
voltage gain by using an extremely high duty cycle.
However, practically, parasitic elements associated with the
inductor, capacitor, switch, and diode cannot be ignored,
and their effects reduce the theoretical voltage gain [10].
The proposed circuit, which focused on improving
efficiency and reducing voltage stress, were presented to
achieve high ripple free voltage without extremely high duty
cycle.
The first section gives the introduction about the paper.
The second section of the paper discuss about the Improved
Transformerless High Step-Up DCDC Converter using
Stacked Cockcroft-Walton Voltage Multiplier. Ripple
reduction and output voltage gain is discussed in the third
section. The fourth section deal with the proposed system
simulation output using MATLAB. The fifth section is
about the results, discussions and the conclusion.
IJE
RT
#Department of EEE, Paavai Engineering College,

Namakkal.
1
samlikers@gmail.com
Keywords:Stacked cascaded voltage multiplier, voltage

multiplier, DC motor, Transformerless, High DC voltage,
step up dcdc converter, Cockcroft Walton (CW).
I. INTRODUCTION
In recent years, the need and demand for electrical
energy has increased due to the extensive use of electrical
equipment and the technology development, and this trend
is constantly growing. Consequently, researchers and
governments worldwide have realized that the future relies
on renewable energy due to the environmental concerns as
the non-renewable energy sources are getting depleting [1],
[2]. Among various renewable energy sources, the
photovoltaic (PV) cell and fuel cell have been considered
attractive choices [3][5]. However, without extra
arrangements, the output voltages generated from both of
them are with rather low level [6], [7]. A high step up dc-dc
converter is used in the power conversion systems
corresponding to these two energy sources for various
applications [8].
In addition to the mentioned applications, a high stepup dc-dc converter is also required by many industrial
applications, such as high-intensity discharge lamp ballasts
for automobile headlamps and battery backup systems for
II. PROPOSED CONVERTER BLOCK DIAGRAM
The proposed converter shown in Fig.1 consists of

several components in it such as DC source, improved boost
converter, stacked Cockcroft Walton voltage multiplier, pi
controller. The low dc source is provided to the improved
boost converter where the low voltage is boosted to a certain
amount according to the input voltage.
Fig.1 Proposed Converter Block Diagram

The boosted voltage is given to the voltage multiplier
and the voltage multiplier is stacked to improve the output
voltage. Due to the stacking of the voltage multiplier the
low input voltage is multiplied to obtain a high output
voltage without a transformer. The high output voltage is
given to a load due to which the output voltage get voltage
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25

The proposed converter shown in Fig.2 consists of four

switches in the boost converter named as switches Sm1, Sm2,
Sc1, and Sc2, in which switches Sc1 and Sc2 are used to
produce an ac source to provide for the stacked cockcroft
walton voltage multiplier and the switch Sm1 and Sm2 are
used to obtain a boost performance by controlling the
inductors energy. The proposed converter is supplied by a
low-level dc source. The proposed converter consists of one
boost inductor Ls and one parallel inductor Lp, four and
stacked Cockcroft Walton voltage multiplier.
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ripples which is controlled by the parallel inductor in the

boost converter. The output voltage is controlled by using a
pi controller by varying the gate pulse given to the
switching devices present in the boost converter. The
proposed converter can be used in renewable energy
systems where usually low input voltages (12Vdc to 48Vdc)
are involved or in uninterrupted power supply systems to
avoid going for a step-up transformer.
III. PROPOSED CONVERTER CIRCUIT DIAGRAM
Fig.2 Circuit Diagram of the Proposed Converter

operation as positive conducting interval [t0, t1] for i 0
and negative conducting interval [t1, t2] for i 0. At some
The stacked CW voltage multiplier is constructed using
point in positive conducting period, only one of the even
capacitors and diodes by a cascade of stages with each stage
diodes can conduct with the sequence D8-D6-D4-D2and D16containing two capacitors and two diodes and stacked to
D14-D12-D10, at some point in negative conducting period,
create stacked CW voltage multiplier. In the stacked CW
only one of the odd diodes can conduct with the sequence
voltage multiplier both capacitors and diodes are divided
D7-D5-D3-D1 and D15-D13-D11-D9. Some assumptions are
into odd group and even group according to their suffixes.
made as follows.
Switches Sm1 (Sc1) and Sm2 (Sc2) operate in opposite mode,
and the operating frequencies of switches Sm1 and Sc1 are
defined as fsm and fsc, respectively. For ease, fsm is
1) All the circuit elements present are ideal so there is
denoted as modulation frequency, and fsc is denoted as
no power loss in the system.
alternating frequency. In theory, these two frequencies
2) The proposed converter is operating in CCM and in
should be as high as possible so that smaller inductor and
the steady-state condition.
capacitors can be used in this circuit. The fsm is set much
3) Some safe commutation states are ignored.
higher than fsc, and the output voltage is controlled by
4) When the inductor transfers the storage energy to
controlling the duty cycle of Sm1 and Sm2, while the output
the stacked CW circuit, only one of the diodes in
voltage ripple is controlled by the capacitor filter and the
the stacked CW circuit will be conducting.
parallel inductor and can also be adjusted by fsc.
According to the polarity the operation of the proposed
A. Operation
converter can be divided into two parts as positive
conducting interval [t0, t1] for i 0 and negative conducting
interval [t1, t2] for i 0. The circuit operation of the
The circuit operation of the proposed converter as
proposed converter is explained using Fig.2. During positive
shown in Fig.2 is analysed with a three-stage stacked CW
conducting interval, only one of the even diodes can
voltage multiplier. The operation of the proposed converter
conduct with the sequence D8D6D4D2-D16D14-D12-D10,
can be separated into two parts depending on the polarity of
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26

while during negative conducting interval, only one of the

odd diodes can conduct with the sequence D7D5-D3-D1D15D13-D11-D9. Moreover, during positive conducting
interval, there are four circuit states.
Fig.3 Circuit Diagram of the Proposed Converter for 4

levels for Closed Loop
The stacked Cockcroft Walton voltage multiplier is
provided by a sinusoidal ac source with line frequency is
used to analyse the behaviour of the stacked CW circuit
through simulation using Fig.3. One inductor is connected
between the ac source and the stacked CW voltage
multiplier for smoothing the current i. During positive half
cycle, that only one of the even diodes is conducted with the
sequence D8D6D4D2-D16D14-D12-D10and with the aim
of the even and odd capacitors are charged discharged
through the conducting diodes. Similar behaviour occurs
during the negative half cycle, while the odd diodes are
conducted with the sequence D7D5-D3-D1-D15D13-D11D9and the odd and even capacitors are charged and
discharged.
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1) State I: Sm1 and Sc1 are turned on, and Sm2, Sc2,
and all stacked CW diodes are turned off. The
boost inductor is charged by the input dc source,
the even group capacitors C6, C4, C2, C12, C10 and
C8 supply the load, and the odd-group capacitors
C5, C3, C1, C11, C9 and C7 are floating.
2) State II: Sm2 and Sc1 are turned on, Sm1 and Sc2
are turned off, and the current i is positive. The
boost inductor and input dc source transfer energy
to the stacked CW voltage multiplier through
different even diodes. State II-A, D6 is conducting;
thus, the even-group capacitors C6, C4, C2, C12, C10
and C8 are charged, and the odd-group capacitors
C5, C3, C1, C11, C9 and C7 are discharged by i. State
II-B, D4 is conducting. Thus, C4 and C2 are
charged, C3 and C1 are discharged by i, C6
supplies load current, and C5 is floating. State II-C,
D2 is conducting. Thus, C2 is charged, C1 is
discharged by i, C6 and C4 supply load current,
and C5 and C3 are floating.
3) State III: Sm2 and Sc2 are turned on, and Sm1, Sc1,
and all stacked CW diodes are turned off. The
boost inductor is charged by the input dc source,
the even group capacitors C6, C4, C2, C12, C10 and
C8 supply the load, and the odd group capacitors
C5, C3, C1, C11, C9 and C7 are floating.
4) State IV: Sm1 and Sc2 are turned on, Sm2 and Sc1
are turned off, and the current i is negative. The
boost inductor and input dc source transfer energy
to the CW voltage multiplier through different odd
diodes. State IV-A, D5 is conducting. Thus, the
even-group capacitors, except C6 which supplies
load current, are discharged, and the odd-group
capacitors C5, C3, C1, C11, C9 and C7 are charged by
i. State IV-B, D3 is conducting. Thus, C2 is
discharged, C3 and C1 are charged by i, C6 and C4
supply load current, and C5 is floating. State IV-C,
D1 is conducting. Thus, C1 is charged by i, all even
capacitors supply load current, and C5 and C3 are
floating.
Conferring to the conducting states dsc and dsm, the
differential equation of the inductor current is given by
and to parallel inductors. These form a two loop with two

switches at both sides with a common inductor to boost the
initial supply or source. The parallel inductors have mutual
inductance due to which it helps in reducing the sudden
increase in the output value. Here a capacitor is connected
across a switch and the source. This will increase the system
efficiency and increase the initial supply voltage to a certain
amount. The Cockcroft Walton voltage multiplier is formed
and another cascaded voltage multiplier is stacked to it and
the output is taken from the D8cathode and D16 anode. The
converter operates in continuous conduction mode, so the
switch stresses, the switching losses, and EMI noise can be
reduced as well.
di L
dt
1
Ls
Vin dsc dsm v
(1)
Where Vin is the input voltage, iL is the input current,

and v is the terminal voltage of the stacked Cockcroft
Walton voltage multiplier. In the proposed converter
switches Sc1 and Sc2 are used to generate an alternating
supply to feed into the CW voltage multiplier and switches
Sm1 and Sm2 are used to control the inductor energy to
obtain a boost performance. The diodes and capacitors are
connected in cascaded connection to form a voltage
multiplier. This is connected to the switches with a source
The DC voltage gives the required initial voltage for the

circuit to operate; the inductor stores the energy and boosts
the voltage and this voltage has to be passed through the
switches. The IGBT switches starts to operate as soon as it
gets the gate pulse from the pulse generator and due to the
varying in operation for individual IGBT the output gets
increased slightly. Thus this part produces a voltage little
higher than the input voltage. The parallel inductor helps in
reducing the sudden rise of voltage at output side during the
initial stage of the system. The capacitor connected across to
the source and the switch increases the output and the
system efficiency.
This voltage is given to the stacked voltage multiplier;
the voltage multiplier multiplies the give voltage to certain
times according to the number of stages used in the circuit.
Then the output voltage is given to load after filtering it
with a capacitive filter. The output voltage is taken as
www.ijert.org
27

feedback and compared with a reference voltage and the

resultant value is given to a PI controller and the pulse
generation for the IGBT switches is automatically adjusted
and the reference value can be set according to the load or
according to the requirement. The desired output is obtained
without any ripples and distortion with improved output
voltage, thus a high voltage is obtained using a low voltage
source.
due to the addition of capacitor and the stacking of the

circuit resulted in increase of voltage and the inductor and
capacitor acts as a filter and produces a stable output. Thus
the analysis of both converters shows that the proposed
converter is more efficient and can be used in all fields.
1000
IV. SIMULATION & EXPERIMENTAL RESULTS
The conventional converter is compared to the
proposed converter by producing the output by both
converters. Both the converters are simulated with and
without load, when the load is applied the conventional
converter showed more distortion in the output and the
output voltage of the converter too got reduced but the
proposed converter removed those distortion and produced a
distortion free output and the output voltage too increased
and maintained at a certain level.
Output Voltage
800
600
400
200
0
Existing System
A.Comparison of Proposed Output with Conventional

Converter Output
When the nonlinear load is applied to the conventional
converter Fig.4 the ripples obtained are too high and the
distortion is too high, it produces nearly 310v, but the
simulation output of the proposed converter Fig.5 shows
that it does not have too much ripples and distortion when a
nonlinear load is applied and it also obtains a voltage of
810v approximately.
Proposed System
Fig.6 Comparison Chart of Existing and Proposed System

Table.1 Comparison of Proposed and Existing Method
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INPUTVOLTAGE
EXISTING
METHOD
PROPOSED
METHOD
10 V
70 V
176 V
42 V
300 V
810 V
The Comparison gives us a clear idea about the

proposed converter which is can produce large output
without too much distortion, ripples and much more
efficient than the conventional converter.
Fig.4 Conventional Converter Output for 42v with

Load
REFERENCES
[1] B. K. Bose (2000), Energy, environment, and
advances in power electronics, IEEE Trans. Power
Electron., vol. 15, no. 4, pp. 688701.
[2] F. Blaabjerg, Z. Chen, and S. B. Kjaer (2004),
Power electronics as efficient interface in dispersed power
generation systems, IEEE Trans. Power Electron., vol. 19,
no. 5, pp. 11841194.
[3] Q. Li and P. Wolfs (2008), A review of the single
phase photovoltaic module integrated converter topologies
with three different dc link configurations, IEEE Trans.
Power Electron., vol. 23, no. 3, pp. 13201333.
Fig.5 Proposed Converter Output for 42v with Load

V. RESULTS
The comparison chart of existing and proposed system
output voltagesis shown Fig.6. The table 1 is the
comparison tables of the output voltage of proposed and
existing system. The Comparison gives us a clear idea about
the proposed converter which can produce large output
without too much distortion, ripples and much more
efficient than the conventional converter. This is obtained
[4] W. Li and X. He (2011), Review of nonisolated

high-step-up dc/dc converters in photovoltaic gridconnected applications, IEEE Trans. Ind. Electron., vol. 58,
no. 4, pp. 12391250.
[5] M. W. Ellis, M. R. Von Spakovsky, and D. J.
Nelson (2001), Fuel cell systems: Efficient, flexible energy
www.ijert.org
28

conversion for the 21st century, Proc. IEEE, vol. 89, no.
12, pp. 18081817.
[6] G. R. Walker and P. C. Sernia (2004), Cascaded
dc-dc converter connection of photovoltaic modules, IEEE
Trans. Power Electron., vol. 19, no. 4, pp. 11301139.
[7] J. Wang, F. Z. Peng, J. Anderson, A. Joseph, and R.
Buffenbarger (2004), Low cost fuel cell converter system
for residential power generation, IEEE Trans. Power
Electron., vol. 19, no. 5, pp. 13151322.
[8] L. S. Yang, T. J. Liang, and J. F. Chen (2009),
Transformerless dc-dc converters with high step-up voltage
gain, IEEE Trans. Ind. Electron., vol. 56, no. 8, pp. 3144
3152.
[9] N. Mohan, T. M. Undeland, and W. P. Robbins
(1995), Power Electronics, 2nded. New York: Wiley, pp.
172178.
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RT
[10] A. L. Rabello, M. A. Co, D. S. L. Simonetti, and J.

L. F. Vieira (1997), An isolated dc-dc boost converter
using two cascade control loops, in Proc.IEEE ISIE, vol. 2,
pp. 452456.
www.ijert.org
29

Dynamic Voltage Restorer for Mitigation of Voltage

Sags
S.Ganesh,
S.Muthukumar,
S.Vijaya kumar,
Assistant Professor,
Chandy College of engineering.
Tuticorin, Tamilnadu,
Gauti.ganeshs@gmail.com
UG Scholar,
Chandy college of engineering,
Tuticorin, Tamil nadu.
Muthukumar635@gmail.com
UG Scholar,
Chandy college of engineering,
Tuticorin, Tamil nadu.
Vijayakumarssrv@gmail.com
Abstract Voltage sags are the most common power quality

disturbance in the distribution system. It occurs due to the fault
in the electrical network or by the starting of a large induction
motor and this can be solved by using the custom power devices
such as Dynamic Voltage Restorer (DVR). DVR was a power
electronics device that was able to compensate voltage sags on
critical loads dynamically. The DVR consists of VSC, injection
transformers, passive filters and energy storage (lead acid
battery). By injecting an appropriate voltage, the DVR restores a
voltage waveform and ensures constant load voltage. The
simulation and experimental results of a DVR using MATLAB
software showed clearly the performance of the DVR in
mitigating voltage sags.
I.
Introduction
Carl N.M.Ho, Henery and S.H. Chaung proposed a method,

when a disturbance occurs (abnormal condition) and supply
voltage deviates from nominal value, DVR supplies voltage
for compensation of sag and is said to be in transient state. The
DVR is connected in series between the load and the supply
voltage [4].
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Keywords dynamic voltage restorer, voltage sags, power

quality, injection methods
Gosh and Ledwich, has been proposed the Dynamic

Voltage Restorer (DVR) to protect sensitive loads from such
voltage sags. The DVR is connected in series with the
sensitive load or distribution feeder and is capable of injecting
real and reactive power demanded by the load during voltage
sag compensation. The output of the DVR inverter is usually
provided with an output LC filter to attenuate the harmonic
contents appearing in injected voltage. The filter parameters
are designed according to certain design aspects such as depth
of the sag to be mitigated and the load voltage [3].
Power quality is a very important issue for electricity

suppliers, equipment manufactures and customers as sensitive
equipment and non-linear loads are becoming common in both
the industrial sectors and the domestic environment. So, both,
electric utilities and end users of electrical power are
becoming concerned about the quality of electric power.
Power quality problems are related to voltage as well as
current. The major power quality problems in the power
system are poor load power factor, DC offset on load voltages,
harmonic contents in loads, voltage sag & voltage swell.
These power quality problems cause malfunctioning of
sensitive equipments; protection and relay system .Faults at
either the transmission or distribution level may cause
transient voltage sag or swell in the entire system or a large
part of it. Also, under heavy load conditions, a significant
voltage drop may occur in the system. Voltage sag is one of
the most common power quality problems faced nowadays.
Voltage sag is a decrease of the normal voltage level between
10 and 90% of the nominal rms voltage at the power
frequency, for durations of 0.5 cycle to 1 minute[1].
Sabin presents voltage deviations, commonly in the form of
voltage sags, can cause severe process disruptions and result
in substantial production loss. Several recent surveys attribute
that 92% of the all disturbances in electrical power distribution
systems are due to voltage
sags[2].
Kasuni Perera, Daniel Salomon son and Arulampaiam

presented a DVR basically supplies the voltage difference
(difference between the pre sag and sag voltage) to
transmission line and maintains the pre sag values condition in
the load sides [5].
Yun Wei Li.Poh Chiang Loh et al. proposed a use of DVR
is proposed in low and medium voltage distribution network to
protect sensitive load from sudden voltage dips/sag [6].
V.K.Ramachandramurthy et al. presents a pulse width
modulated inverter is used to vary the amplitude and the phase
angle of the injected voltages, thus allowing the control of
both real and reactive power exchange between the
distribution system and the load [7].
D.Mahinda et al. proposed a method for proper voltage sag
compensation, it is necessary to derive suitable and fast
control scheme for inverter switching. The general
requirement of a control scheme is to obtain an ac waveform
with minimum total harmonic distortion (THD) and best
dynamic response against supply and load disturbance when
the DVR is operated for voltage sag compensation [8].
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II.
Dynamic Voltage Restorer
30

Among the power quality problems (sags, swells,

harmonics etc) voltage sags are the most severe disturbances.
In order to overcome these problems the concept of custom
power devices is introduced recently. One of those devices is
the Dynamic Voltage Restorer (DVR), which is the most
efficient and effective modern custom power device used in
power distribution networks. DVR is a recently proposed
series connected solid state device that injects voltage into the
system in order to regulate the load side voltage. It is normally
installed in a distribution system between the supply and the
critical load feeder at the point of common coupling (PCC).
Other than voltage sags and swells compensation, DVR can
also added other features like: line voltage harmonics
compensation, reduction of transients in voltage and fault
current limitations [9]. DVR consists of rectifier, energy
storage device, PWM inverter, filter and injection transformer.
D. Filter
Filter circuit is used to remove the unwanted noise signals
or harmonics in the generated voltage from the PWM inverter.
The LC filter is used in the DVR to improve the quality of
power.
E. Injection Transformer
The injection transformer is connected with the transmission
line in series. When the voltage level is decreased in the
transmission line then the transformer inject the voltage with
required magnitude and frequency. The supply to the
transformer is given from the filter circuit.
III.
Injection Methods
Voltage injection or compensation methods by means of a

DVR depend upon the limiting factors such as; DVR power
ratings, various conditions of load, and different types of
voltage sags. Some loads are sensitive towards phase angel
jump and some are sensitive towards change in magnitude and
others are tolerant to these. Therefore the control strategies
depend upon the type of load characteristics. There are four
different methods of DVR voltage injection which are
Fig. 1 Block diagram of DVR
Pre-sag compensation method

In-phase compensation method
In-phase advanced compensation method
Voltage tolerance method with minimum energy
injection
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A.
B.
C.
D.
A. Pre-Sag/Dip Compensation:
A. Rectifier
The process of converting AC supply into DC supply is
known as rectification. A device which is used for rectification
is known as rectifier. The AC voltage cannot be able to store
directly in a storage device. Hence, the rectifier circuit is used
in the DVR.
B. Energy Storage Device
The pre-sag method tracks the supply voltage continuously

and if it detects any disturbances in supply voltage it will
inject the difference voltage between the sag or voltage at
PCC and pre-fault condition, so that the load voltage can be
restored back to the pre-fault condition. Compensation of
voltage sags in the both phase angle and amplitude sensitive
loads would be achieved by pre-sag compensation method. In
this method the injected active power cannot be controlled and
it is determined by external conditions such as the type of
faults and load conditions [10].
Energy storage device stores the converted DC voltage from

the rectifier. It is very important device in the DVR. The
energy storage device is DC capacity, batteries, supercapacitor, super conducting magnetic energy storage and
flywheels.
C. PWM inverter
The DC supply from the storage device is passed to the
PWM inverter. The PWM inverter generates the voltage with
required magnitude and frequency. It converts the DC voltage
into AC voltage. The PWM inverter is connected between the
energy storage device and filter circuit.
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Fig. 2 Pre-Sag Compensation
31

B. In phase Compensation method:

This is the most straight forward method. In this method the
injected voltage is in phase with the supply side voltage
irrespective of the load current and pre-fault voltage. The
phase angles of the pre-sag and load voltage are different but
the most important criteria for power quality that is the
constant magnitude of load voltage are satisfied. One of the
advantages of this method is that the amplitude of DVR
injection voltage is minimum for certain voltage sag in
comparison with other strategies [10].
nominal state that will not disturb the operation characteristics

of loads. Both magnitude and phase are the control parameter
for this method which can be achieved by small energy
injection [10].
Fig. 5 Voltage tolerance method with minimum energy injection
IV.
Fig. 3 In-phase compensation method
C. In Phase advanced compensation:
In this section the various results obtained after simulation

are analysed and discussed. The test system comprises of
580V distribution network and the system has been examined
under different fault conditions such as three phase fault,
single line to ground fault and line to line fault.
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In this method the real power spent by the DVR is decreased

by minimizing the power angle between the sag voltage and
load current. In case of pre-sag and in-phase compensation
method the active power is injected into the system during
disturbances. The active power supply is limited stored energy
in the DC links and this part is one of the most expensive parts
of DVR. Minimization of injected energy is achieved by
making the active power component zero by having the
injection voltage phasor perpendicular to the load current
phasor .In this method the values of load current and voltage
are fixed in the system so we can change only the phase of the
Results And Analysis Of The

Dvr Test Models
A.
Test Results
The simulation time for the model is taken as 0.5 sec. The
first simulation was done without creating any fault at the
network where supply is 580V with frequency 50 Hz. Fig.6
shows the waveforms of input voltage without fault. Y- Axis
shows the magnitude of voltage and X-axis shows the
simulation time. Fig.7 shows the waveform of load voltage
without fault. Hence from the input voltage is obtained to be
580V and it is found that the magnitude of both the input and
the load voltage is almost same.
sag voltage. IPAC method uses only reactive power and

unfortunately, not al1 the sags can be mitigated without real
power, as a consequence, this method is only suitable for a
limited range of sags [10].
Fig. 4 In-phase advance compensation method
D. Voltage tolerance method with minimum energy injection:

A small drop in voltage and small jump in phase angle can
be tolerated by the load itself. If the voltage magnitude lies
between 90%-110% of nominal voltage and 5%-10% of
www.ijert.org
Fig. 6 Simulation model without fault
32

Fig. 7 Input voltage without fault
Fig. 10 Input voltage with L-G fault
Fig. 8 Load voltage without fault
Fig. 11 Input voltage with L-L fault
The second simulation is done by applying three-phase to

ground fault with fault resistance of 4.6 for a time duration
of 100 ms i.e. from 0.2s to 0.3s and the ground resistance is
0.1. Supply is 580V, with frequency 50 Hz.
Fig. 12 Input voltage with three phase fault
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The third simulation is carried out at the same scenario as

above but the DVR is now introduced at the load side to
compensate the voltage sag occurred due to the three phase
fault applied. Fig.14 shows the injected voltage generated by
the dynamic voltage restorer to compensate the voltage sag.
The waveform obtained from the test model is shown in
Fig.15. It is clearly observed that the voltage waveform that is
obtained after connection of DVR in series is almost similar to
the supply voltage i.e. the DVR we installed is working
efficiently.
Fig. 9 Simulation model with fault
Waveforms for the load voltages (without

compensation) are given below. Fig.10 shows the waveform
of the input voltage with L-G fault and without DVR. Fig.11
shows the waveform of the input voltage with L-L fault and
without DVR. Fig.12 shows the waveform of the input voltage
with three phase fault and without DVR. Even after the fault is
created the input voltage remains almost same as before while
load voltage experiences a huge change. With the application
of the fault to the circuit the magnitude of the load voltage
decreases at the fault period from 580V to 250V. This voltage
dip is needed to be compensated to get the desired voltage at
the load.
Fig. 13 Test model of DVR
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33

[9]
Mohan Reddy, T. Gowrimanohar, Mitigation Of Interruption & Voltage

Sag, Swell Using A Cascaded Mli Based Dynamic Voltage Restorer,
International Journal Of Electrical And Electronics Engineering
Research (IJEEER), Vol. 3, Issue 2, Jun 2013, 153-170.
[10] S. S. Choi, J. D. Li and D. M. Vilathgamuwa, Dynamic voltage
restorating with minimum energy injection, IEEE Trans. on power sys.,
vol. 15, pp. 51-57, Feb 2000
Fig. 14 Injected voltage
Fig. 15 Compensated voltage by DVR
V.
Conclusion
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The modeling and simulation of a DVR using MATLAB

has been presented. The simulation results showed clearly the
performance of the DVR in mitigating voltage sags. The DVR
handled fault conditions without any difficulties and injected
the appropriate voltage to keep the load voltage balanced and
constant at the nominal value. In this study, the DVR has
shown the ability to compensate for voltage sags at the
distribution side; this can be proved through simulation and
experimental results. The efficiency and the effectiveness in
voltage sags compensation showed by the DVR makes it an
interesting power quality device compared to other custom
power devices.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
S.P.Awate, Enhancement of Voltage Profile Using Dynamic Voltage

Restorer, International Journal of Advanced Research in Electrical,
Electronics and Instrumentation Engineering, Vol. 2, Issue 12,
December 2013
Sabin, D.D., An assessment of distribution system power quality,
Electrical Power Research Institute, EPRI Final Report TR-106294-V2,
Palo Alto, CA. 1996
Gosh, A. and G. Ledwich, Compensation of distribution system voltage
using DVR. IEEE Trans. Power Deliv., 17, no 46880, 2002
Carl N.M.Ho, Henery and S.H. Chaung, Fast Dynamic Control Scheme
for Capacitor- Supported Dynamic Voltage Restorer: Design Issues,
Implementation and Analysis. IEEE, 2007..
Kasuni Perera, Daniel Salomon son and Arulampaiam, Atputharajah,
Sanath Alahakoon, Automated Control Technique for A Single Phase
Dynamic Voltage Restorer IEEE, 2006.
Yun Wei Li.Poh Chiang Loh, Frede Blaabje and D.Mahinda
Vilathgamuwa, Investigation and Improvement of Transient Response
of DVR at Medium Voltage Level. IEEE, 2006..
Y V.K.Ramachandramurthy,C.Fitzer,A.Arulampalm.,C.Zhan, M. Barnes
and N. Jenkins Control of Battery Supported Voltage Restorer, IEEE,
September 2002, Vol. 149 No.5
D.Mahinda, Vilathgamuwa, H.M.Wijekoon and S.S.Choi, Interline
Dynamic Voltage Restorer : A Novel and Economical Approach For
Multi-Line Power Quality Compensation IEEE 2003.
www.ijert.org
34

EFFICIENT DESIGN OF LOGICAL STRUCTURES USING QUANTUM

DOT CELLULAR AUTOMATA
P.SIVARAJ
Dept.of ECE
Mr.S.Manthandi PeriyannaSamy M.E.,(Ph.D)

Professor / ECE
VKS College of Engineering & Technology,
Karur, Tamilnadu, India

Sivaraj1904@gmail.com
Quantum cellular automata (QCA). First proposed 1 in 1994,

unlike conventional computers in which information is
transferred from one place to another by means of electrical
current, QCA transfers information by propagating a
polarization state [12, 11]. QCA is based upon the encoding of
binary information in the charge configuration within quantum
dot cells. Computational power is provided by the Coulombic
interaction between QCA cells. No current between cells and
no power or information is delivered to individual internal
cells. The local interconnections between cells are provided by
the physics of cell-to-cell interaction due to the rearrangement
of electron positions [12]. While there is still much work to be
done, early experimental results indicate that QCA may be an
extremely viable alternative to CMOS. QCA cells and a simple
QCA logical device have been successfully fabricated and
tested [3].
The rest of this brief is organized as follows: a brief background of the QCA technology II and III. QCA Standard
Functions existing adders designed in QCA is given in Section
IV, the novel adder design is then introduced in Section V, and
QCA Implementation and Tables VI finally, in Section VII
conclusions are drawn.
II. BACKGROUND
A QCA is a nanostructure having as its basic cell a square
four quantum dots structure charged with two free electrons
able to tunnel through the dots within the cell [1]. Because of
Coulombic repulsion, the two electrons will always reside in
opposite corners. The locations of the electrons in the cell (also
named polarizations P) determine two possible stable states that
can be associated to the binary states 1 and 0.
Although adjacent cells interact through electrostatic forces
and tend to align their polarizations, QCA cells do not have
intrinsic data flow directionality. To achieve controllable data
directions, the cells within a QCA design are partitioned into
the so-called clock zones that are progressively associated to
four clock signals, each phase shifted by 90.
This clock scheme, named the zone clocking scheme, makes
the QCA designs intrinsically pipelined, as each clock zone
behaves like a D-latch.
2.1 QCA Design Architecture
2.1.1 Basics of QCA:
The basic elements of QCA are QCA cell, Majority
gate and Invertor. These is important elements. In QCA cell
each cell is having four quantum dots and is having two free
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ABSTRACT--The area and complexity are the major issues

in circuit design. Here, we propose different types of adder
designs based on Quantum dot Cellular Automata (QCA)
that reduces number of QCA cells and area compare to
previous designs. The quantum dot cellular automata can
implement digital circuits with faster speed, smaller size
and low power consumption. The QCA cell is a basic
building block of nanotechnology that can be used to make
gates, wires and memories. The basic logic circuits used in
this technology are the inverter and the Majority Gate
(MG), using this other logical circuits can be designed. In
this paper, the adders such as half, full and serial bit were
designed and analyzed. These structures were designed with
minimum number of cells by using cell minimization
techniques. The techniques are using two cells inverter and
suitable arrangement of cells without overlapping of
neighboring cells. The proposed method can be used to
minimize area and complexity. These circuits were designed
by majority gate and implemented by QCA cells. Then, they
simulated using QCA Designer. The Simulated results were
verified according to the truth table. The performance
analyses of those circuits are compared according to
complexity, area and number of clock cycles and are also
compared with previous designs.
Index TermsAdders, nanocomputing, quantum-dot cellular
automata (QCA).
I.INTRODUCTION
1.1 An Introduction to the Problem
In 1965, Gordon Moore predicted that the number of
transistors that could be integrated into a single die would grow
exponentially with time. Moore's law has governed
microprocessor manufacturing processes, and consequently
microprocessor performance ever since. However, recent
studies indicate that during the next two decades, the laws of
nature will begin to govern microprocessor design and
fabrication. Today many integrated circuits are manufactured at
0.25-0.33 micron processes. As device sizes decrease to an
order of 0.05 microns (a technology that is currently
unrealizable), physical limitations of conventional electronics
including power consumption, Interconnect, and lithography
will become increasingly difficult [10].
1.2 An (Alternative) Solution
As an alternative to CMOS-VLSI, researchers have
proposed an approach to computing with quantum dots, the
Mr.C.Kavin Prakash M.E.,

Professor / ECE
www.ijert.org
35

electrons. The locations of the electrons determine the binary be impossible to implement a multiplexor, decoder, or adder in
QCA without a logical AND gate, OR gate, or inverter. It has
states.Fig.1 shows the QCA cell diagram.
been demonstrated that a value's complement can be obtained
simply by ripping it o_ a 45-degree wire at the proper location.
Implementing the logical AND and OR functions is also quite
simple. The logical function for the majority gate is:
Y = AB + BC + AC
Fig.1 QCA Cell Polarization.
Fig.2. Invertor
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2.1.2 QCA Cell:

A quantum-dot cellular automata (QCA) is a square
nanostructure of electron wells having free electrons. Each cell
has four quantum dots [2].The four dots are located in the four
corners .The cell can be charged with two free electrons. By
using the clocking mechanism, the electrons tunnel to proper
location during the clock transition. Thus there exist two
equivalent energetically arrangements of the two electrons in
the QCA cell as shown in Fig.1.These two arrangements can
represent logic 1 and logic 0 respectively so that binary
information can be encoded. Invertor is represented in Fig.2
and Majority gate in Fig.3.
The AND function can be implemented by setting one

value (A, B, or C) in equation to a logical 0. Similarly, the OR
function can be implemented by Setting one value (A, B, or C)
in equation to a logical 1. This result s in the equations:
AND = AB + B(0) + A(0) = AB
OR = AB + B(1) + A(1) = A + B
It is worth noting that because this property exists (i.e.
the ability to generate the AND and OR functions) and given
the fact that it is possible to obtain the inverse of a signal value,
the QCA logic set is functionally complete meaning that any
logical circuit can be generated with QCA devices. More
complex logical circuits (such as the multiplexor can then be
constructed from at least AND and OR gates if not clever
combinations of majority gates. QCA cells labeled anchored in
have their electron polarization frozen to successfully
implement AND and OR functions.
III. QCA STANDARD FUNCTIONS
The three variables A,B and C to facilitate the
conversion of a sum of-products expression to minimized
majority logic. Based on that to obtain the efficient majority
expression for any given three-variable Boolean function
amenable to QCA implementation. The simplified majority
expressions for some standard functions are given in the table.
The AND and OR gates are realized by fixing the polarization
to one of the inputs of the majority gate to either P = 1 (logic
0) or P = 1 (logic 1).
Fig.3. Majority gate

A QCA design permits two options for crossover, termed
coplanar crossover and multilayer crossover. While the
coplanar crossover uses only one layer but involves usage of
two cell types (termed regular and rotated), the multilayer
crossover uses more than one layer of cells (analogous to
multiple metal layers in a conventional IC). The multilayer
crossover is used in this paper for wire crossings since we can
effectively cross signals over on another layer and the extra
layers of QCA can be used as active components of the circuit.
Further, multilayer QCA circuits can potentially consume much
less area as compared to planar circuits. Moreover, some
studies indicate that coplanar crossover is difficult to fabricate
in the molecular implementation.
2.1.3 A Simple QCA Circuit
To implement more complicated logical functions, a
subset of simple logical gates is required. For example, it would
Fig. 4 .Layout of AND and OR gates.

The NAND function is the complement of AND
functions. It is realized by connecting AND gate (MG)
followed by an inverter. Similarly the NOR gate is realized by
connecting OR gate (MG) followed by an inverter. If the last
two cells are arranged as shown in the following figure then it
acts as an inverter. By using this 2cell inverter, the area
required and complexity can be minimized.
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Fig. 5 .Layout of NAND gate.

Fig.10. Layout of Ex-NOR gate
Fig. 6 .Layout of NOR gate
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The XOR is a logical operation on two operands that

results in a logical value of true if and only if one of the
operands, but not both, has a value of true. This forms a
fundamental logic gate in many operations to follow. The
realization is done making use of majority gates (MGs) and
following the equations as follows
IV EXISTING QCA ADDERS

In this section, we first existing a new QCA addition
algorithm and the corresponding one-bit QCA adder structure
that reduces the number of the majority gates and inverters
required by existing designs [5]-[6]. Then, we demonstrate that,
using this structure, we can obtain efficient carry look ahead nbit QCA adders.
4.1. Existing QCA Adders
We now introduce a new design of one-bit QCA adder
based on the proposed algorithm. The proposed one-bit QCA
adder consists of three majority gates and two inverters. It
results in reduced hardware compared to the original full adder
[5], [6] and retains the simple clocking scheme.
Fig.7.XOR schematic
It is noted that the bit-serial QCA adder [7] uses a

variant of the proposed one-bit QCA adder. To create an n-bit
adder, we arrange n proposed one-bit adders vertically in a
column. The clocking of the cells within the n-bit adder is
designed such that the carry will propagate down to the last bit
before the sum is calculated, thereby implementing a CLA
adder. The proposed QCA adder design requires fewer majority
gates and inverters while maintaining the same clocking
scheme and speed in comparison with existing QCA adders.
Compared to the bit-serial QCA adder, the proposed design is n
times faster, at the expense of being approximately n times
larger in area. Furthermore, the complicated feedbacks control.
Fig.8. Layout of XOR gate
Fig 11: Existing one-bit QCA full adder
Fig.9.Ex-NOR schematic.
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V. NOVEL QCA ADDER

VI. QCA IMPLEMENTATION AND TABLES
To introduce the novel architecture proposed for
implementing ripple adders in QCA, let consider two n-bit 6.1 Implementation of Adders using QCA
addends A = an1, . . . , a0 and B = bn1, . . . , b0 and suppose
that for the I th bit position (with i = n 1, . . . , 0) the auxiliary
propagate and generate signals, namely pi = ai + bi and gi = ai
bi , are computed. ci being the carry produced at the generic
(i1) bitposition, the carry signal ci+2, furnished at the (i+1)th
bit position, can be computed using the conventional CLA logic
reported in (2). The latter can be rewritten as given in (3), by
exploiting Theorems 1 and 2 demonstrated in [15]. In this way,
the RCA action, needed to propagate the carry ci through the
two subsequent bit positions, requires only one MG.
Conversely, conventional circuits operating in the RCA
fashion, namely the RCA and the CFA, require two cascaded
MGs to perform the same operation.
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Fig.13 Design of Half Adder using QCA
Fig.14. Design of Full adder using two half adder in QCA
Fig 12: Novel 2-bit basic module.

In other words, an RCA adder designed as proposed
has a worst case path almost halved with respect to the
conventional RCA and CFA is exploited in the design of the
novel 2-bit module shown in Fig. 1 that also shows the
computation of the carry ci+1 = M(pi gici ). The proposed n-bit
adder is then implemented by cascading n/2 2-bit modules.
Having assumed that the carry-in of the adder iscin = 0, the
signal p0 is not required and the 2-bit module used at the least
significant bit position is simplified.
Fig.15. Design of Full adder using QCA.
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Fig 17.Graph comparing different adders.
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Fig.16. Design of 8-bit Ripple Carry Adder using QCA.
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VII. CONCLUSION
A new adder designed in QCA was presented. It
achieved speed performances higher than all the existing QCA
adders, with an area requirement comparable with the cheap
RCA and CFA demonstrated in [13] and [16]. The novel adder
operated in the RCA fashion, but it could propagate a carry
signal through a number of cascaded MGs significantly lower
than conventional RCA adders. In addition, because of the
adopted basic logic and layout strategy, the number of clock
cycles required for completing the elaboration was limited. A
64-bit binary adder designed as described in this brief exhibited
a delay of only nine clock cycles, occupied an active area of
18.72 m2, and achieved an ADP of only 168.48.
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P.SIVARAJ, Master of Engineering in VLSI-DESIGN from

VKS COLLEGE OF ENGINEERING AND TECHNOLOGY
IN KARUR. Bachelor of Engineering in ECE from
DHANALAKSHMI SRINIVASAN ENGG COLLEGE in
PERAMBALUR.
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International Journal of Engineering Research & Technology (IJERT)

ARISE' 14 Conference Proceedings

Watermarking of Compressed imageswithImproved

Department of Computer Science, CUSAT

Department of Computer Science, CUSAT

require decompression or decryption, and also preserves the

AbstractMedia data generally Handles In compressed and

International Journal of Engineering Research & Technology (IJERT)

may lead to random decryption and there is no strong security

then reduced by a constant to make it symmetric around zero

This paper is organized as follows. Section II describes the

II. PROPOSED SCHEME

At first blue region detection is performed on input image

Stacking the shares reveals the secret.

Encryption ( Creating shares)

Channel (Cover image , Dither Modulation)

Visual cryptography scheme in computer representation using

International Journal of Engineering Research & Technology (IJERT)

subband coefficients the highest texture energy subband is

The details of the algorithm is as follows:

The embedding algorithm uses color image as cover and

Where Y_(i, j) represents the modified frequency coefficient of

12) Replace the modified subband coefficients into its initial

International Journal of Engineering Research & Technology (IJERT)

Extraction algorithm is of type blind extraction which uses

Table 1 : Algorithm comparison

Input : Watermarked (Color) image.

diffusion is improved by several simple steps in the round:

III. RESULTS AND DISCUSSION

International Journal of Engineering Research & Technology (IJERT)

International Journal of Engineering Research & Technology (IJERT)

The sensation of realism can be achieved by visual

Abstract - 3-D video will become one of the most

ITH the development of the technology of 3DTV

and free viewpoint TV (FTV), MVC attracts more and more

A straight forward method to encode the multi-view

International Journal of Engineering Research & Technology (IJERT)

stereo views. The prediction structures are presented

Fig 1: Overall structure of an MVC system

III. CODING OF STEREO VIEWS

Stereoscopic vision is based on the projection of an object

The central requirement for any video coding standard is high

The main difference between classic video coding and

International Journal of Engineering Research & Technology (IJERT)

that uses already coded pictures of other views at the same

IV. PREDICTION STRUCTURES

Besides the fast algorithm described above, the

To the fact that current existing prediction structures lack have

Figure.2 Diagonal Inter-View Prediction Test Mode. (a)

In Figure 2(b) structure, the decoding of the current view has

International Journal of Engineering Research & Technology (IJERT)

eyes. The idea here is to do the same thing with a com-puter.

Although temporal prediction is on average the most efficient

to choose the inter-view predic-tion mode. Thus, the

[3] T. Wiegand, G. J. Sullivan, G. Bjntegaard, and A.

International Journal of Engineering Research & Technology (IJERT)

Enhanced Grid Synchronization of a DG system

The grid synchronization techniques can be adversely

AbstractDistributed Generation (DG) System is a small

KeywordsDistributed Generation (DG), permanent magnet

The Distributed Generation (DG) systems are highly

International Journal of Engineering Research & Technology (IJERT)

This paper proposes an enhanced synchronization structure

OVERVIEW OF PROPOSED SYSTEM

Arise'14 Ijert

Arise'14 Ijert