ECET105Digital Fundamentals

Lab #7 Detailed Directions

I.

OBJECTIVES

1. To test the operation of a 74LS74 D flip-flop and compare the operation with the
predicted behavior
2. To test the operation of a 74LS112 J-K flip-flop and compare the operation with the
predicted behavior
3. To measure propagation delays of a 74LS112 J-K flip-flop
4. To build and test an enhanced adder-subtractor
II.

PARTS LIST
Equipment:
IBM PC or Compatible with Windows 2000 or Higher
Quartus II Design SoftwareVersion 9.1
Frequency Generator
Oscilloscope
Parts:
2 330 resistors, W
1 74LS74 dual D flip-flop
1 74LS112 dual J-K flip-flop
1 eSOC III FPGA Board

III.

2 Red LEDs
1 Green LED
1 SPDT Switch, DIP configuration

PROCEDURE

A. Test the 74LS74 D Flip-Flop

1. Build the D flip-flop circuit shown in Figure 7.1. The LEDs are wired as active-LOW
since the flip-flop can supply more current in a low state than in a high state. This means
that the green LED is on when Q is HIGH and the red LED indicates Q is HIGH.
Remember to attach VCC to pin 14 and ground to pin 7.

Course Number: ECET105

Laboratory Number: 7

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Figure 7.174LS74 D Flip-Flop Test Circuit

The pin out of 7474 is shown below:

2. Using the circuit, verify that the operation follows the truth table for this device.

Course Number: ECET105

Laboratory Number: 7

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Theoretical Truth Table:

The circuit construction is shown below (if you are not able to find a similar SPDT switch in
your parts and tools box as shown in the circuit diagram, try to use a jumper wire to switch
between Vcc and the Ground)

The circuit operation should reflect the theoretical truth table. You need to show some
photos here to demonstrate the circuit operations.

Course Number: ECET105

Laboratory Number: 7

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Important aspects to pay attention:

The clock input signal from the function generator should be obtained from the Pulse
Generator of your trainer box as shown below.

You can use the scope to measure clock signal generated. Adjust the signal as necessary.

Course Number: ECET105

Laboratory Number: 7

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Use DMM to measure voltage points when checking the circuit and performing
troubleshooting.

Remember to connect all ground points together.

3. What happens when both PRE and CLR are set low?
Ground pins 1 and 4 and Observe the output LEDs status.
__________________________________________________________________

B. Test the 74LS112 J-K Flip-Flop

1. Build the J-K flip-flop circuit shown in Figure 7.2. Remember to attach VCC to pin 16
and ground to pin 8.

Course Number: ECET105

Laboratory Number: 7

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Figure 7.274LS112 J-K Flip-Flop Test Circuit

74112 pin out is shown below.

2. Using the circuit, verify that the operation follows the truth table for this device.

Theoretical Truth Table:

Find out the theoretical truth table and make sure you understand the concept and operation
of NGT (negative going transition) and PGT.

Course Number: ECET105

Laboratory Number: 7

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The circuit construction is shown below:

The circuit operation should reflect the theoretical truth table.

for inputs J=0, K=1; J=1, K=0; and
Check Q and Q
for both J=K=1. For clock input, turn frequency down, you should
Check Q and Q
observe the toggling on LEDs.
Important aspects to pay attention:

The clock input from the function generator (refer to the previous discussion and
photo)

Use DMM to measure voltage points when check the circuit the doing
troubleshooting

Remember to connect all ground points together

3. Increase the pulse generator output to 1.0 MHz. Set the switches so that all of the flipflop inputs are high and remove the LEDs and resistors. Using the oscilloscope, measure
the propagation times for the Q output from the active clock edge. Record the value
below.

Course Number: ECET105

Laboratory Number: 7

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If you are not able to get 1 MHz from your pulse generator, you may try to get a lower
frequency (lets say 450 KHz) as shown below.

See screen prints from the scope as follows.

On this screenshot, Channel 1 is the input clock signal (upper signal). Channel 2 is the
output signal at Q (lower signal).

Course Number: ECET105

Laboratory Number: 7

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The signal below shows the delay time between input signal and output signal. You can run
the stop mode on the scope, decease the time scale to have better view of the signals. Review
the concepts of and how to measure t pLH and t pHL (if they are not clear in the lecture or
in the textbook, there are good websites explaining them). Check datasheet for the
theoretical range and your measurements should be within it.

tPHL = ______________________

Course Number: ECET105

tPLH = ________________

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C. Enhanced Adder-Subtractor
1. The adder-subtractor circuit built in Lab 5 has a fundamental weakness. Whenever any of
the inputs is changed, the output changes. This would present a significant problem in
building a calculator since the user only wants the selected operation to occur when the
equal button is pressed. We can modify the circuit from Lab 5 to operate in this way by
adding in flip-flops to store the outputs only on the activation of a clock signal.
2. Using Quartus II, modify the circuit from Lab 5 as shown in Figure 7.3 by adding three
7474 D-flip-flip chips. Note that a clear function has been added and that the flip-flop
presets are inactive since they are tied to +5V (labeled VCC).

Make sure your circuit is wired correctly. It is easy to make a simple mistake and you need to
double check. One wiring error is going to cost you a lot of troubleshooting effort.

Figure 7.3Enhanced Adder-Subtractor

3. Perform a simulation to verify the correct operation of the circuit. Note that in this case
(for the actual eSoc board), the CLOCK signal is not a periodic signal; the CLOCK signal
is a discrete signal occurring on a switch closure.

Course Number: ECET105

Laboratory Number: 7

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This picture shows the waveforms of successfully executed simulation results.

For the above waveforms Case 1: from time duration 0-1000 ns:
A=0011; B=0001; ADDSUB = 1 (meaning performing subtraction); the SUM output
S4S3S2S1=0010; and Carry COUT=1 (meaning positive result). You dont need to perform
2s complement for positive result.
The waveform verifies that in Base-10, its: 3-1=+2
Case 2: from time duration 1000-2000 ns:
A=0010; B=0101; ADDSUB = 1 (meaning performing subtraction); the SUM output
S4S3S2S1=1101; and Carry COUT=0 (meaning negative result).
2s complement for SUM = 0011
The waveform verifies that in Base-10, its: 2-5= -3

Course Number: ECET105

Laboratory Number: 7

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Case 3: from time duration 2000-3000 ns:

A=0010; B=0101; ADDSUB = 0 (meaning performing addition); the SUM output
S4S3S2S1=0111; and Carry COUT=0 (meaning no carry out for this addition operation).
The waveform verifies that in Base-10, its: 2+5= 7

4. Assign pins to the inputs and outputs. Use the DIP switches for your inputs (0-3 for A, 811 for B, 7 for CLEAR, 15 for ADDSUB), one of the debounced pushbuttons for
CLOCK and the red LEDs for outputs (RD0-4).
The pin planner map is shown below.

5. Download your program to the eSOC III board and test the operation of the circuit.
6. Photograph your final circuit for submission (online) or demonstrate your circuit to your
professor (onsite or blended).

Photos below show the circuit after the program is successfully downloaded and executed.
Below demonstrate Case 1: A=0011; B=0001; ADDSUB = 1 (meaning performing
subtraction); the SUM output S4S3S2S1=0010; and Carry COUT=1 (meaning positive
result).

Course Number: ECET105

Laboratory Number: 7

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The waveform verifies that in Base-10, its: 3-1=+2

Below shows Case 2: A=0010; B=0101; ADDSUB = 1 (meaning performing subtraction);

the SUM output S4S3S2S1=1101; and Carry COUT=0 (meaning negative result).
2s complement for SUM = 0011
The waveform verifies that in Base-10, its: 2-5= -3

Course Number: ECET105

Laboratory Number: 7

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Case 3 is shown in the following photo: A=0010; B=0101; ADDSUB = 0 (meaning

performing addition); the SUM output S4S3S2S1=0111; and Carry COUT=0 (meaning no
carry out for this addition operation).
The waveform verifies that in Base-10, its: 2+5= 7

Note to students: Direct copy and paste of any photo in

this document to your project report is prohibited and will
be considered as plagiarism. Your project report must
show photos of addition and subtraction operations using
values different from the examples shown in this
document to verify your own work.

Course Number: ECET105

Laboratory Number: 7

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