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The NM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM). It is manufactured using Fairchilds proprietary CMOS AMG EPROM technology for an excellent combination of speed and economy while
providing excellent reliability.
Features
High performance CMOS
90 ns access time
Fast turn-off for microprocessor compatibility
Block Diagram
Data Outputs O0 - O7
VCC
GND
VPP
OE
CE/PGM
Output
Buffers
..
Y Decoder
524,288-Bit
Cell Matrix
.......
A0 - A15
Address
Inputs
X Decoder
DS010834-1
AMG is a trademark of WSI, Inc.
www.fairchildsemi.com
July 1998
A16
A16
A16
A15
A15
A15
A15
VPP
A12
A12
A12
A12
A12
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A0
O0
O1
A0
O0
O1
A0
O0
O1
A0
O0
O1
A0
O0
O1
O2
O2
O2
O2
O2
GND
GND
GND
GND
GND
DIP
NM27C512
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
VCC
A14
A13
A8
A9
A11
OE/VPP
A10
VCC
CE/PGM
O7
O6
O5
O4
O3
VCC
XX/PGM XX/PGM
XX
A17
A14
A14
A14
VCC
VCC
A18
A18
A17
A17
A14
A14
A13
A8
A13
A13
A13
A8
A8
A8
A9
A9
A11
A9
A11
A11
A11
A9
A11
OE
A10
OE
A10
OE
A10
OE
A10
CE/PGM
CE
CE
O7
O6
O7
O6
O7
O6
O7
O6
O7
O6
O5
O5
O5
O5
O5
O4
O3
O4
O3
O4
O3
O4
O3
O4
O3
A13
A8
A9
OE/VPP
A10
CE/PGM CE/PGM
DS010834-2
Compatible EPROM pin configurations are shown in the blocks adjacement to the NM27C512 pins.
Pin Names
A0A15
Addresses
NM27C512 Q, N, V 90
90
CE/PGM
Chip Enable/Program
NM27C512 Q, N, V 120
120
OE
NM27C512 Q, N, V 150
150
O0O7
Parameter/Order Number
Output Enable
Outputs
NC
PLCC
120
150
A7
A12
A15
NC
VCC
A14
A13
Parameter/Order Number
A6
A5
A4
A3
A2
A1
A0
NC
O0
1 32 31 30
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
A8
A9
A11
NC
OE/VPP
A10
CE/PGM
O7
O8
O1
O2
GND
NC
O3
O4
O5
14 15 16 17 18 19 20
DS010834-3
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Connection Diagrams
Storage Temperature
ESD Protection
(MIL Std. 883, Method 3015.2)
>2000V
-65C to +150C
Operating Range
-0.7V to +14V
Range
-0.6V to +7V
-0.6V to +7V
Temperature
VCC
Tolerance
Commercial
0C to +70C
+5V
10%
Industrial
-40C to +85C
+5V
10%
Read Operation
DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Max
Units
VIL
-0.5
0.8
VIH
2.0
VCC +1
VOL
0.4
VOH
IOH = -2.5 mA
ISB1
CE = VCC 0.3V
100
ISB2
CE = VIH
mA
ICC1
CE = OE = VIL
40
mA
ICC2
CE = GND, f = 5 MHz
Inputs = VCC or GND, I/O = 0 mA
C, E Temp Ranges
35
mA
IPP
VPP = VCC
10
VPP
ILI
ILO
IOL = 2.1 mA
3.5
f = 5 MHz
VCC - 0.7
VCC
-1
-10
10
150
Max
Units
AC Electrical Characteristics
Symbol
Parameter
90
Min
tACC
Max
Min
120
Max
Min
90
120
150
tCE
CE to Output Delay
90
120
150
tOE
OE to Output Delay
40
50
50
tDF
Output Disable to
Output Float
35
25
45
tOH
ns
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Parameter
Conditions
Typ
Max
Units
CIN1
Input Capacitance
except OE/VPP
VIN = 0V
12
pF
COUT
Output Capacitance
VOUT = 0V
12
pF
CIN2
OE/VPP Input
Capacitance
VIN = 0V
20
25
pF
AC Test Conditions
Output Load
0.45V to 2.4V
0.8V and 2V
0.8V and 2V
AC Waveforms (Notes 6, 7)
ADDRESS
2V
0.8V
CE
2V
0.8V
Address Valid
t CF
(Note 4, 5)
OE
OUTPUT
t CE
2V
0.8V
2V
t OE
t DF
(Note 3)
(Note 4, 5)
Hi-Z
0.8V
Hi-Z
Valid Output
t ACC
t OH
(Note 3)
DS010834-4
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC tOE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE .
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 F ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 A. CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
tAS
tOES
OE Setup Time
tDS
tVCS
tAH
tDH
tCF
tPW
45
tOEH
OE Hold Time
tDV
tPRT
50
ns
tVR
IPP
ICC
TR
Temperature Ambient
20
VCC
VPP
tFR
VIL
VIH
2.4
tIN
0.8
0.8
tOUT
OE = VIL
0
50
60
ns
105
s
s
OE = VIL
250
CE = VIL
OE = VPP
ns
30
mA
50
mA
25
30
6.25
6.5
6.75
12.5
12.75
13
0.45
ns
V
V
Programming Waveforms
Program
Addresses
2.0V
0.8V
Program Verify
Address N
t AS
2.0V
Data
t DS
OE/VPP
2.0V
Hi-Z
Data In Stable
ADD N
0.8V
t DH
0.8V
t DV
t CF
12.75V
0.8V
tPRT
t AH
t OES
t PW
t OEH
t VR
t VPS
CE/PGM
t VCS
VCC
6.25V
DS010834-5
Note 10: Fairchilds standard product warranty applies to devices programmed to specifications described herein.
Note 11: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 12: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 F capacitor is required across VCC to GND to suppress spurious voltage transients which
may damage the device.
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NO
DEVICE
FAILED
YES
n = 10?
FAIL
VERIFY
BYTE
PASS
LAST
ADDRESS
?
NO
INCREMENT
ADDRESS
n=0
YES
VERIFY
BYTE
FAIL
PASS
INCREMENT
ADDRESS
NO
PROGRAM ONE
50 s
PULSE
LAST
ADDRESS
?
YES
The standard National Semiconductor algorithm may also be used but it will take longer programming time.
DS010834-6
FIGURE 1.
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DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table1. It
should be noted that all inputs for the six modes are at TTL levels.
The power supplies required are VCC and OE/V PP. The OE/VPP
power supply must be at 12.75V during the three programming
modes, and must be at 5V in the other three modes. The VCC
power supply must be at 6.5V during the three programming
modes, and at 5V in the other three modes.
When the address and data are stable, an active low, TTL program
pulse is applied to the CE/PGM input. A program pulse must be
applied at each address location to be programmed.
The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a
series of 50 s pulses until it verifies good, up to a maximum of 10
pulses. Most memory cells will program with a single 50 s pulse.
(The standard National Semiconductor Algorithm may also be
used but it will have longer programming time.)
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE/PGM) is the power control and should be used for device
selection. Output Enable (OE/VPP) is the output control and should
be used to gate data to the output pins, independent of device
selection. Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE). Data is
available at the outputs tOE after the falling edge of OE, assuming
that CE has been low and addresses have been stable for at least
tACC tOE.
Standby Mode
The EPROM has a standby mode which reduces the active power
dissipation by over 99%, from 220 mW to 0.55 mW. The EPROM
is placed in the standby mode by applying a CMOS high signal to
the CE/PGM input. When in standby mode, the outputs are in a
high impedance state, independent of the OE input.
Program Inhibit
Programming multiple EPROMs in parallel with different data is
also easily accomplished. Except for CE/PGM all like inputs
(including OE/VPP) of the parallel EPROMs may be common. A
TTL low level program pulse applied to an EPROMs CE/PGM
input with OE/VPP at 12.75V will program that EPROM. A TTL high
level CE/PGM input inhibits the other EPROMs from being programmed.
Output Disable
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRISTATE).
Program Verify
Output OR-Typing
AFTER PROGRAMMING
This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active only
when data is desired from a particular memory device.
Programming
The Manufacturers Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for
NM27C512 is 8F85, where 8F designates that it is made by
Fairchild Semiconductor, and 85 designates a 512K part.
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Functional Description
are held at VIL. Address pin A0 is held at VIL for the manufacturers
code, and held at VIH for the device code. The code is read on the
eight data pins, O0 O 7 . Proper code access is only guaranteed
at 25C 5C.
ERASURE CHARACTERISTICS
SYSTEM CONSIDERATION
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of
2537. The integrated dose (i.e., UV intensity x exposure time) for
erasure should be minimum of 15W-sec/cm2.
The EPROM should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes which
should be removed before erasure
An erasure system should be calibrated periodically. The distance
from lamp to device should be maintained at one inch. The erasure
time increases as the square of the distance from the lamp (if
distance is doubled the erasure time increases by factor of 4).
Mode Selection
The modes of operation of the NM27C512 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are
TTL levels excepts for VPP and A9 for device signature.
CE/PGM
OE/VPP
VCC
Outputs
VIL
VIL
5.0V
DOUT
X (Note 13)
VIH
5.0V
High Z
VIH
5.0V
High Z
Programming
VIL
12.75V
6.25V
DIN
Program Verify
VIL
VIL
6.25V
DOUT
Program Inhibit
VIH
12.75V
6.25V
High Z
Mode
Read
Output Disable
Standby
A0
(10)
A9
(24)
07
(19)
06
(18)
05
(17)
04
(16)
03
(15)
02
(13)
01
(12)
00
(11)
Hex
Data
Manufacturer Code
VIL
12V
8F
Device Code
VIH
12V
85
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15
R 0.025
[0.635]
0.515-0.530
[13.081-13.462]
R 0.030-0.055
[0.762-1.397]
TYP
14
0.290-0.310
[7.366-7.874]
U.V. WINDOW
0.050-0.060
[1.270-1.524]
TYP
0.010 [0.254]
MAX
GLASS
SEALANT
0.590-0.620
[14.99-15.75]
0.180 [4.572]
MAX
0.225 [5.715]
MAX TYP
0.125 [3.175]
MIN TYP
0.060-0.100
[1.524-2.540]
TYP
0.090-0.110
[2.286-2.794]
TYP
86-94
TYP
0.015-0.021
[0.381-0.533]
TYP
0.033-0.045
[0.838-1.143]
TYP
0.015-0.060
[0.381-1.524]
TYP
90-100
TYP 0.008-0.012
[0.203-0.305]
TYP
+0.025
0.685 -0.060
+0.635
[17.399 -1.524 ]
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.030
Max
(0.762)
0.600 - 0.620
(15.24 - 15.75)
0.062 RAD
(1.575)
0.510 0.005
(12.95 0.127)
95 5
0.008-0.015
(0.229-0.381)
0.580
(14.73)
Pin #1
IDENT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1.393 - 1.420
(35.38 - 36.07)
+0.025
0.625 -0.015
(15.88 +0.635
(
-0.381
0.050
(1.270)
Typ
0.053 - 0.069
(1.346 - 1.753)
0.125-0.165
(3.175-4.191)
0.108 0.010
(2.540 0.254)
0.050 0.015
(1.270 0.381)
88 94
Typ
0.20 Min
(0.508)
0.125-0.145
(3.175-3.583)
0.018 0.003
(0.457 0.076)
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0.007[0.18] S B D-E S
0.449-0.453
[11.40-11.51]
-H-
Base
Plane
0.023-0.029
[0.58-0.74]
0.015
[0.38] Min Typ
-A0.045
[1.143]
60
0.007[0.18] S B D-E S
0.002[0.05] S B
0.000-0.010
[0.00-0.25]
Polished Optional
0.490-0530
[12.45-13.46]
0.400
-D4
( [10.16] )
30
0.541-0.545
[13.74-13-84]
29
5
0.549-0.553
[13.94-14.05]
0.015[0.38] S
D-E, F-G S
-G-
-B0.585-0.595
[14.86-15.11]
0.013-0.021
TYP
[0.33-0.53]
-FSee detail A
-J13
14
20
-E-
0.002[0.05] S A
0.007[0.18] S
0.007[0.18] S
A F-G S
A F-G S
0.118-0.129
[3.00-3.28]
0.010[0.25] L
0.007[0.18] M
21
B A D-E, F-G S
B
0.042-0.048
45X [1.07-1.22]
0.123-0.140
[3.12-3.56]
0.050
,
,
0.025
[0.64]
Min
0.007[0.18] S
0.019-0.025
[0.48-0.64]
H D-E, F-G S
D-E, F-G S
-C0.004[0.10]
0.020
[0.51]
0.005 Max
[0.13]
0.0100
[0.254]
0.045
[1.14]
0.025
[0.64] Min
Detail A
Typical
Rotated 90
0.021-0.027
[0.53-0.69]
0.030-0.040
[0.76-1.02]
0.065-0.071
[1.65-1.80]
0.053-0.059
[1.65-1.80]
0.031-0.037
[0.79-0.94]
0.006-0.012
[0.15-0.30]
0.026-0.032
Typ
[0.66-0.81]
0.078-0.095
[1.98-2.41]
0.027-0.033
[0.69-0.84]
Section B-B
Typical
Fairchild Semiconductor
Europe
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Tel:
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2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
10
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