A High Precision Multi-modulus Fractional-N

Divider for DAB Receiver

Yang Yang, Wang Zhigong, Tang Lu and Xu Jian
Institute of RF- & OE-ICs
Southeast University
Nanjing, 210096, China
Abstract- The implementation of a high precision fractional-N
divider, which is one of the components of a phase-locked loop
(PLL) fractional-N frequency synthesizer for Digital Audio
Broadcasting (DAB) and other modern communication systems,
is presented. Unconditionally stable - modulators of the third
order (namely MASH-1-1-1) are implemented in the frequency
synthesizer and they can provide a good average estimate for the
fractional-N dividers. By cooperating with a dual-modulus
prescaler, this divider can achieve a fractional frequency division
from 509.74 to 703.10 with the precision of 1/224. This divider has
been designed in a SMIC 0.18-m CMOS technology and by
using Artisan standard cell library. The chip area is 323m
323m. Simulation results show that it works correctly and can
realize a frequency division with a high precision.
Keywords- fractional-N frequency synthesizer, delta-sigmamodulator, DAB

I.

INTRODUCTION

With the development of modern communication

technology, PLL based frequency synthesizer is continuously
improved to meet the increasing demands of wireless systems.
For PLLs based on a synthesizer, the integer-N frequency
synthesizer is widely used during the early years. But its
output minimum-step is limited by the reference frequency
(Fref) [1]. To get smaller output change step, the integer
synthesizer must adopt smaller reference frequency, which
means larger division ratio and phase noise [2]. As a solution,
the fractional-N frequency synthesizer is proposed and it has
become more and more popular in recent years. A fractional-N
divider is realized by changing the divisor between two
adjacent integers; say N and N+1 or N1 and N, to get an
average fractional divisor. Normally the changing of divisor
will import excess spur and phase noise in the output of the
loop. The - modulation technique is proposed by Miller and
Conley in Ref. [3], and Riley, et al., in Ref. [4] in order to
shape the dynamic-divisor imported noise. Now this method
has gained a variety of applications ranging from accurate
frequency generation and timing in digital systems to direct
frequency modulation in radio-frequency analog front ends of
modern communication systems.
In implementing the --based fractional-N frequency
synthesizer, a close look at the hardware implementation of
the noise-shaping modulator is required. In section III, a

Corresponding author: zgwang@seu.edu.cn

detailed design description of the implementation of the

MASH-1-1-1 - modulator is given.
To achieve the benefits of high frequency communication
systems, high performance frequency synthesizers are
required. The design of a high precision fractional-N divider is
a challenge in future communication system. The simulation
and design of the divider in DAB receiver are described.
II. ARCHITECTURE OF FRACTIONAL-N FREQUENCY
SYNTHESIZER
As mentioned above, both higher frequency resolution and
lower phase noise result in the usage of a fractional division
ratio to satisfy the output VCO frequency and frequency step
of interest. Frequency synthesizers employing such fractional
dividers are called fractional-N frequency synthesizers. Fig. 1
shows a conventional fractional-N frequency synthesizer.
Early implementation of the fractional dividers employs a
digital accumulator [5] that controls a dual-modulus prescaler.
The synthesizer shown in Fig. 1 is termed first-order
fractional-N frequency synthesizer. The fractional divider is
composed of two parts: the integral part N and the fractional
part F and is often represented by N.Frac (e.g. 10.5 where N is
10 and 0.Frac is 0.5). The fractional part 0.Frac controls a
digital accumulator whose overflow controls a dual-modulus
prescaler N/(N+1). The size of the accumulator used depends
on the frequency error as well as the sampling frequency. The
output frequency is given by:
fout = fsamp N.Frac=fsamp (N+K/F)
The fractional part 0.Frac is usually represented by a
fraction whose integer numerator is called K and whose
integer denominator is called F. Since the overflow
controlling the DMP changes the value of the divider from
N+1 to N within the cycle, this resets the phase error at the
output of the PFD, generating signals that modulate the VCO
and appear at the output of the VCO. These signals are
deterministic in nature, can be predicted, and are often termed
fractional spurious signals [6]. These spurious signals appear
at fractional multiples of the reference and are difficult to
remove and hence are not used in commercially viable
solutions. However, fractional-N frequency synthesizers that
employ - modulators in place of the first-order digital
accumulator have recently gained popularity as they provide

excellent phase noise suppression [7].

Fig. 3 The structure of the fractional divider circuit

Fig. 1 A conventional fractional-N frequency synthesizer

A typical frequency synthesizer employing a - modulator

is shown in Fig. 2.

Fig. 2 A typical deltasigma (-)-based fractional-N frequency synthesizer

The typical --based fractional-N frequency synthesizer structure

is adopted in our design, and the - modulator of third order in this
structure will be described in the next section.
III. DESIGN OF MULTIMODULUS FRACTIONAL DIVIDER
The architecture of the multi-modulus fractional divider is
shown in Fig. 3.
The fractional divider circuit is composed of a -
modulator, an adder, a pulse counter, a swallow counter, and a
16/17 dual-mode divider. The 16/17 dual-mode divider is not
a part of this design. The fractional divider of Fig. 1 is
implemented using 34 bits representing the divider value, with
10 bits for integer part, and 24 bits for the fraction part. M is
an integer between 31 and 44, and A varies from 0 to 15. So,
M and A can be represented as 6-bit and 4-bit signals,
respectively.
The reason to select 24-bit control code for fractional part is
to ensure sufficient frequency precision. The average value of
3-bit output signal of the - modulator is K/224, and after
adding the control code N which represents the integer
division ratio, the average value N will be N K/224(N
16M A N (K/224), and 16M A is just the expression of
an integer frequency division ratio. So the average value of the
instantaneous integer frequency division ratio is NK/224,
which achieved the desired fractional.

The - modulator is the core of a fractional divider. In this

section, the structure of - modulator is described in details.
The design of the - modulator adopts the MASH1-1-1
structure; the circuit structure is shown in Fig. 4. The structure
has many advantages, such as simple, unconditionally stable,
high-speed and low-power by introduction of pipelined
operation. The structure is basically the same with the
traditional one, but a little improvement has been made on it.
The - modulator emulates the average fractional part of
the divider into instantaneous several integral levels. Those
vary in a random manner between -3 and 4 for this order of
modulator. From the preceding analysis, we know that the
spurious of fractional-N frequency synthesizer is due to
cyclical division ratio caused by the - modulator output
sequence. The spurious increases when the - modulator
output sequence cycle is short. Therefore, we should try to
increase the - modulator output sequence cycle. A
traditional accumulator-type first-order modulator has been
improved. The accumulator carry output signal is multiplied
by a coefficient a, and at the next cycle put back to its input,
which is called the HK-type first-order modulator [8], the
structure of the model shown in Fig.5. To further increase the
modulator output sequence, the modulator will be improved
by changing every order modulator to HK structure. This
approach can achieve a greater period compared with only the
first order being HK modulator.
y[i]

Error Cancellation Circuit

C3[i-1]

DFF

DFF

DFF

C1[i]
x[i]

First-order
Modulator
A1

DFF

C2[i]
-e1[i]

DFF

First-order
Modulator
A2

C3[i]
-e2[i]

First-order
Modulator
A3

Fig. 4 The circuit structure of MASH 1-1-1 modulator

-e3[i]

Fig. 5 HK-type first-order modulator

The feedback coefficients a of three first-order modulator

shown in Fig. 4 were a1, a2 and a3, for the N-bit accumulator,
if the (2N-a1), (2N-a2) and (2N-a3) are prime numbers with each
other (that means the common measure of them is 1). So the
maximum cycle of the output sequence is (2N-a1), (2N-a2) and
(2N-a3). Therefore, we only need to find a group of suitable
values, which can allow the modulator to maximize the output
sequence cycle. Several groups of a value are given in terms
of meeting the above N-bit MASH1-1-1 modulator in Table I
(N = 5 ~ 25).
TABLE I
THE VALUE OF FEEDBACK COEFFICIENTS A AT ALL LEVELS OF N-BIT
MASH1-1-1 MODULATOR
The bits of modulator (N)
5, 7, 13, 17, 19
6, 9, 10, 12, 14, 20, 22, 24
8, 18, 25
11, 21
16, 23
15

a1
1
3
5
9
15
19

a2
0
0
0
0
0
0

a3
3
1
1
1
1
1

In this work, N=24, a1=3, a2=0, a3=1. When a = 0, it is the

equivalent to no feedback, namely is a first-order modulator 24-bit
accumulator. When a =3 or 1, the digital realization of the circuit is
shown in Fig. 6.
C[i]
x[i]
24bit
Reg

X
-e[i]
X+Y

1bit

24bit
Reg

24bit

(a)
a=1
(b) a=3
Fig. 6 First-order modulator implementation circuit

As shown in Fig. 4, this modulator use error cancellation

circuit to fully offset the quantization noise generated by the
former two first-order modulator. And the noise transfer

function is a 3rd-order high pass filter function, error

elimination circuit performance function to be achieved as
follows:
y[i]=C1[i]+C2[i]- C2[i-1]+ C3[i]-2 C3[i-1]+ C3[i-2] 1
Where Ck [i] is the k-level first-order modulator carry output
(k 1, 2, 3). First of all, Ck [i 1] can be obtained through a
register (the trigger). Secondly, Equation (1) can be divided
into three parts, and calculated separately. Suppose A [2:0] =
C3 [i]-2 C3 [i-1] + C3 [i-2], B [2:0] = C2[i]- C2[i-1], then
y[i]=C1[i]+ A [2:0]+ B [2:0]. These expressions can be
implemented using combinational logic circuits. Table
indicates the output of the 3-bit MASH 1-1-1 modulator and
its corresponding decimal output.
TABLE II
3-BIT MODULATOR OUTPUT AND THE CORRESPONDING DECIMAL NUMBER
y[2 : 0]
the decimal output

101
-3

110
-2

111
-1

000
0

001
1

010
2

011
3

100
4

From previous analysis, the implementation of high-speed

accumulators is the most important part in the implementation
of the modulator. Accumulator consists of an adder and a
register which put the output back into the input. Not
considering other factors, a 24-bit adder is very easy to
implement, such as the use of the structure of a cascade of 24
full adders to complete, but the delay of this structure is very
large, this will greatly reduce the adder operating frequency.
To improve the speed, the 24-bit pipelined adder is
implemented using six-stage 4-bit carry look-ahead (CLA)
adders to achieve very high clocking speed [9].
IV. SIMULATION RESULTS
As the - modulator is the key to achieve fractional
division ratio, its performance directly determines whether the
fractional divider is good or bad. And the - modulator
simulations are as follows:
When the modulator input K is 8388605 and 1677720,
respectively (the corresponding values of fractional part were
close to 0.5 and 0.1). Fig. 7 shows the simulated waveform of
the - modulator output sequence. In which the signal CLK
is - modulator clock (in this system it is supplied by the
programmable divider output), and the signal OUT represents
the - modulator output sequence.

(a)

n=16777202240.099999900.1

(b)

n=83886052240.499999820.5

Fig.7 The - modulator output sequence

The - modulator output sequence of the first 10 clock

cycles are added together, you will find:
(a) 2+(-2)+3+(-3)+3+0+0+(-1)+2+(-3)=1,
The average value increasing equals 110=0.1
(b) 0+1+0+2+(-1)+1+0+2+(-1)+1=5,
The average value increasing equals 510=0.5
The results indicate that the cumulative average value is
close to the fractional division ratio. In order to verify its
function by increasing the accumulation clock cycles, we use
software Modelsim and Matlab to do co-simulation. Its output
sequence is transmitted to Matlab to do cumulative operation
relative to the clock. Fig. 8 shows the relationship between the
number of clock cycles and the cumulative value. Because
K=6021342, the fractional division ratio is equal to K/224, and
is close to 0.35889995. The simulation result shows that the
modulator has a high precision. As long as the number of
clock cycles is large enough, the error between the average
and the setting fractional division ratio can be negligible. [10]

instead of a circuit schematic. Multimode fractional divider

net list was obtained by the automatic placement and routing
tool. Before simulation the wire delay and the standard cell
delay should be marked back to the corresponding modules.
The simulation results are shown in Fig. 10.

Fig.10 The simulation result of the whole divider

V. CONCLUSION
A fractional frequency divider in which a - modulator
named MASH-1-1-1 was proposed to be utilized is
implemented in SMIC 0.18-m CMOS technology based on
standard cells. Simulation results indicate that the frequency
divider achieves the expected precision. Its operating
frequency is from 20 MHz to 50 MHz. The precision of the
fractional division ratio can reach 1/224. Finally, the PLL
frequency synthesis for DAB is designed and works well
when the frequency divider is mixed with the other modules
designed with the full custom method.
ACKNOWLEDGMENT
The authors acknowledge the support of the Specialized
Research Fund for the Doctoral Program of Higher Education,
China (No. 20090092120012), and the Science and
Technology Program of Southeast University (No. KJ2010402)
and the suggestions by the DAB project group.

Fig.8 The relationship between the number of clock cycles and the cumulative
value (K= 6021342)

The frequency divider is designed using SMIC 0.18-m

CMOS technology and standard cells. Fig. 9 is its layout with
a 323m323m area.

Fig.9 Physical layout of the fractional-N divider

For the convenience of simulation, the dual-mode divider

was described in Verilog language and used in simulation

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