Professional Documents
Culture Documents
Agenda
Introduction to design flow and Backend
Introduction to design planning
Floorplanning / Hierarchical design
Power
P
planning
l
i
Summary
Agenda
Introduction to design flow and Backend
Introduction to design planning
Floorplanning / Hierarchical design
Power
P
planning
l
i
Summary
Physical Design
Flow
GDSII
SDC constraints
Front End
Back End
P/G
Grid
Rings
Straps
Periphery
(I/O) area
RAM
IP
ROM
Verilog netlist
SDC constraints
How do we handle?
Die
size
IO / Hard-IP placement
Global clock distribution
Power
P
planning
l
i
Flat versus hierarchical design
Design Planning
Floorplanning
Determine die size
Shape and arrange hierarchical blocks
Integrate hard-IP efficiently
Predict and prevent congestion hotspots and critical timing
paths
Power planning
Create power distribution grid
Consider IR drop and Electromigration
Implement power saving techniques
Power gating
g
g
Multi-Voltage design / Voltage islands
Agenda
Introduction to design planning
Floorplanning
p
g
Setup/configuration
Die
size,
size utilization,
utilization metallization scheme
IO-ring and macro placement
Flat versus hierarchical design
Hierarchical design planning issues
Power planning
Summary
S t /
Setup/configuration
fi
ti
Read netlist
Read SDC
Read .lib files
Read footprint
p
for P&R
LEF : SOC encounter
Fram : Synopsys tools
Read technology file
Metal width (DRC
rules)
check netlist
High fanout
U i
Unique
Unconnected inputs
Standard cell area
Ch k titiming
Check
i without
ith t wire
i lload
d
Floorplanning Utilization
Low standard-cell
utilization
High standard-cell
tili ti
utilization
Floorplanning Utilization
Initialize Floorplan
Define globals (VDD1,VDD2,GND1,.)
Define
D fi core area : ((cells
ll + utilization
ili i ffactor))
[[Analog]
g] macro
IO
core
core
IO
congestion hotspots
Design
Fullchip Design
I/O Pad
IP Macro
Blk 1
P&R
Flow
Blk 2
P&R
Flow
Blk 3
P&R
Flow
Block / Tile
Hierarchical Design
Advantages
Disadvantages
Channels
Ch
l or abutment
b t
t
Rectilinear block shapes are possible
Channels
Rectilinear
Blocks
Abutment
Pin guide 1
Pin guide 2
Partition
IN1
Block Boundary
Clk
Clk
Original Netlist
Agenda
Introduction to design planning
Floorplanning
Power planning
Intro
Summary
Dynamic Power
Average Power
problem
p
ob e
Static Power
(Leakage Power)
Floorplan
+
Design of the grid
Fail
Power density
problem in the
Long run
Electromigration
(EM)
The drop in supply voltage over the length of the supply line
A resistance matrix of the power grid is constructed
The average
g current of each g
gate is considered
The matrix is solved for the current at each node, to determine
the IR-drop.
VDD Pad
VDD
Core
Standard Cells
Clock network
Macros
I/O
Separate supply ring
Often higher voltage
Fixed, no optimization
Agenda
Introduction to design planning
Floorplanning
Power planning
Intro
to p
power issues in IC design
g
Basic power grid creation
Multi-voltage design & power gating
Automated power grid design flows
Summary
Agenda
Introduction to design planning
Floorplanning
Power planning
Intro
to p
power issues in IC design
g
Basic power grid creation
Multi-voltage design & power gating
Automated power grid design flows
Summary
Agenda
Introduction to design planning
Floorplanning
p
g
Power planning
Intro
Summary
y
P
Power
Network
N t
k Analysis
A l i (PNA)
VDD
PNS : C
Create
t P
Power R
Routing
ti
After running
g trials,, an optimal
p
p
power g
grid can be chosen and the
actual rails can be laid out.
Virtual rails => actual rails
Outside main PNS : memory footprint + cpu time
Many options : eg. % Via penetration , order of routing
Check legal cell/pin placement (grid aligned ?)
Depending
p
g on the design
g p
phase
What cells, nets and layers
eg. First macros and pads, then high voltage areas,
Secondary
Seco
da y PG
G po
ports
ts o
on level
e e sshftrs,
t s, isol.
so ce
cells,
s, ret.
et Regs
egs
Later after placement during routing : same as the follow pins for
the normal vdd and gnd of the std cells.
PNS : Create
C t P
Power Routing
R ti
Summary
The g
goal of design
g p
planning
g is to arrange
g the chip
p so that the Place and
Route flow can converge quickly and easily.
Design experience is needed
Floorplan is driven by :
Power
P
Timing
Congestion
Minimum area
There is no 1 way to create a floorplan
Flat hierarchical
Regions,
g
,p
position of the macros
Order of placement IO versus macros versus core
This phase can take a significant portion of the complete backend design
time.
E l analysis
Early
l i off power grid
id iis essential
ti l ffor avoiding
idi major
j problems
bl
near
the end of the design cycle.
Automated power grid tools may help reduce necessary safety margins.
Placement
Design Specification
Logic Design and Verification
F
Front-End
d
Physical
Libraries
Netlist
Physical Design
Constraints
Floorplanning
Placement
Routing
Physical
Design
Stage
g
Ba
ack-End
Logic Synthesis
D fi iti off Pl
Definition
Placementt
Placement : Exact placement of the
modules (modules can be gates, standard
cells macros
cells,
macros).
) The general goal is to
minimize the total area and interconnect
cost.
cost
The quality of the attainable routing is highly
d t
determined
i db
by th
the placement.
l
t
Circuit placement becomes very critical in 90nm
and below technologies.
C tF
Cost
Function
ti for
f Placement
Pl
t
Cost components
Methods of consideration
Area
Wire length
Overlap
Timing
Congestion
Congestion-driven Placement
Clock
Clock Gating
Power
Placement Steps
p
Input information:
Netlist
Mapped and floorplanned design
Logical and physical libraries
Design constraints
Reading Gate
Gate-level
level netlists from synthesis
Global placement
D il d placement
Detailed
l
Placement optimization
Output information:
Physical layout information
Cell placement locations
Physical layout
layout, timing
timing, and technology information of reference libraries
Logical
Target
Placement
tool
Design libraries
Physical
Macro cell
Floorplanned
design
Technology file
Reference
Standard cell
Dimension
bounding box
VDD
Blockage
Symmetry
(X, Y, or 90)
;
;
;
;
reference point
(typically 0,0)
MACRO AN2D0
CLASS CORE ;
FOREIGN AN2D0 0.000 0.000 ;
ORIGIN 0.000 0.000 ;
SIZE 1.400 BY 2.520 ;
SYMMETRY x y ;
SITE core ;
PIN Z
ANTENNADIFFAREA 0.1680 ;
DIRECTION OUTPUT ;
PORT
LAYER M1 ;
RECT 1.300 0.640 1.330 1.675
RECT 1.190 0.640 1.300 1.780
RECT 1.140 0.640 1.190 0.900
RECT 1.140 1.520 1.190 1.780
END
END Z
PIN A2
ANTENNAGATEAREA 0.0704 ;
DIRECTION INPUT ;
PORT
LAYER M1 ;
RECT 0.610 0.975 0.770 1.545
END
NAND_1
GND
Abstract View
Pins
(direction, layer
and shape)
T h l
Technology
IInformation
f
ti
Ph i l T
Physical
Technology
h l
D
Data
t
LAYER M1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
OFFSET 0 ;
PITCH 0.280 ;
WIDTH 0.120 ;
MAXWIDTH 12.000 ;
AREA 0.058 ;
MINENCLOSEDAREA 0.200 ;
THICKNESS 0.240 ;
HEIGHT 0.765 ;
SPACINGTABLE
PARALLELRUNLENGTH
WIDTH
0.00
WIDTH
0.30
WIDTH
1.50
WIDTH
4.50
MINIMUMCUT
MINIMUMCUT
MINIMUMCUT
MINIMUMCUT
MINIMUMCUT
2
4
2
2
2
WIDTH
WIDTH
WIDTH
WIDTH
WIDTH
Example
.lefhdr
0.00
0.12
0.12
0.12
0.12
0.42
0.98
0.70
2.00
3.00
0.52
0.12
0.17
0.17
0.17
1.50
0.12
0.17
0.50
0.50
4.50
0.12
0.17
0.50
1.50
;
FROMABOVE ;
LENGTH 0.70 WITHIN 1.001 ;
LENGTH 2.00 WITHIN 2.001 ;
LENGTH 10.0 WITHIN 5.001 ;
MINIMUMDENSITY 15 ;
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 50 50 ;
DENSITYCHECKSTEP 50 ;
FILLACTIVESPACING 0.60 ;
Gl b l and
Global
dD
Detail
t il Pl
Placementt
Reading Gate-Level
Gate Level
Netlist from synthesis
Global Placement
Detailed Placement
Pl
Placement
t optimization
ti i ti
Gl b l Pl
Global
Placementt
Standard cells are placed into groups such
that the number of connections between
groups is minimized.
This is solved through circuit partitioning
partitioning.
Bad Placement
Good Placement
D t il Pl
Detail
Placementt : L
Legalization
li ti
H dM
Hard
Macro Pl
Placementt
S
Some
Guidelines
G id li
ffor Pl
Placementt (2)
RAM 1
RAM 2
RAM 3
RAM 4
RAM 5
RAM 6
Avoid
constrictive
channels
Avoid many pins in
the narrow
channel. Rotate for
pin accessibility
RAM 7
RAM 8
Use blockage
t improve
to
i
pin
i
accessibility
Methods of consideration
Area
Wire length
Overlap
Timing
Timing-driven Placement
Congestion
Congestion-driven Placement
Clock
Clock Gating
Power
Ti i D
Timing
Driven
i
Pl
Placementt
Critical p
paths are determined using
g static timing
g
analysis (STA).
Tool attempts to minimize wire length of critical
paths to meet setup timing.
Net RCs are based on Virtual
Routing (VR) estimates
Vi t l Route
Virtual
R t / Trial
T i l Route
R t
Manhatten geometry
Horizontal Vertical
NO diagonal routing
Virtual
Route
Congestion
hot spot
Detour
C
Congestion
ti M
Map
No need to use -congestion
unnecessarily
G
Gives
uniform
f
density
M dif i Ph
Modifying
Physical
i lC
Constraints
t i t
Modifying Physical Constraints:
Cell Density
Cell densityy can be up
p to
95% by default
x2 y2
x1 y1
M dif i th
Modifying
the Fl
Floorplan
l
Iterative p
placement trials should be
performed to find a balance between the
different tool options/settings.
p
g
Cl k T
Clock
Tree S
Synthesis
th i
CTS
CLK
Skew
Area (#buffers)
Power
Slew rates
71
S
Sources
off skew
k
Not p
perfectly
y balanced clock tree
Different levels of buffering
Different cells
Different load due to routing
Different RC delays
S
Setting
a skew constraint = 0 ps
Makes no sense
Insertion delay (latency) will increase
Power consumption will increase
Area will increase
Rule of thumb : skew values : 100 150 ps for 90 nm
Temperature variations
.
.
.
Ground plane
L effective
tox
73
Clock
gating
Logical
Clock Tree
Sequentials
((x,y)
,y)
Logic
Synthesis
Physical
Synthesis (Placement)
Clock
Buffering
Routing
Clock Nets
CTS
Sizing
Clock Buffers
Routing
R
Remove
unwanted
t db
buffering
ff i
CTS : Goals
Meeting the clock tree design rule
constraints
Maximum transition delay
Maximum load capacitance
Maximum fanout
defaults
Meeting the clock tree targets
Maximum skew
Min/Max insertion delay (latency)
Highest priority
77
Summary
Clock tree synthesis is one of the most
important steps of IC design and can have
a significant impact on timing
timing, power
power, area
area,
etc.
The
Th clocking
l ki strategy
t t
h
has tto b
be di
discussed
d
with the frontend people before CTS is
started
t t d
Clocks
identification
Clock dependencies
Clock balancing
Routing
Overview
Routing fundamentals / Advanced issues
intro
The routing flow
Special topics for 90nm and below
Additional routing considerations
Summary
Routing Fundamentals
Input :
Goal:
placed design
fixed number of metal/copper layers
routed design that is DRC clean and meets setup/hold timing
Vertical
routing
tracks
Horizontal
routing
tracks
Routing Fundamentals :
Advanced Issues
crosstalk
DFM / DFY
DRC
clean
Rule based versus Model based
85
Global Route
Vertical routing
capacity = 9 tracks
Horizontal routing
capacity = 9 tracks
X
Y
86
Global Route
Input:
Cell
Goal:
Perform
Wire length
Congestion
Timing
Noise / SI
Global Route
Global Route
Assigns nets to specific metal layers
and global routing cells (Gcells)
global route
virtual route
X
congested area
88
Global Route
Preroute
Global route
89
Detail Route
nets to tracks
Lay
L d
down wires
i
Connect pins to corresponding nets
90
Notch
Spacing
Notch
Spacing
Thin&Fat
Spacing
Mi
Min
Spacing
92
93
Speed Up
net 1
Aggressor
net 2
Victim
Delay
95
Aggressor
Extra clock cycle!
Functional Failure
Vdd
^
Clk
Victim
96
Noise depends on
Coupling
capacitance
Total net capacitance
Strength of the driver (Rd of the victim net)
Design optimization
Increase
drive strength
strength, often easier (only
local effect)
Buffer long nets
98
Spacing
Grounded shields
Shielding
Same layer (H)
Adjacent layers (V)
Net Ordering
99
Macro
Grounded shields
102
Before CTO
Short
path
Skew OK?
No
Postroute CTO
ECO Route
After CTO
Increased
delay
O ti
Options
for
f CPU effort
ff t
# processors
Routing
in parallel on # processors
Superthreading, multithreading
Some routers are better a threading than
others
Summary
SI
Aware Route
Small geometries make SI timing closure much
more difficult
DFM
Driven Route
/ DFY
DRC