ECE 171

DIGITAL CIRCUITS
ERIK JASTAD

10 NOV 2015
VERILOG PROJECT 1

Needed to create a circuit which gives the fewest coins possible for 25 cents in change composed of
nickels and dimes only. The circuit must recognize when it has no change to give and only dispense exact
change when it has 25 cents or more available to give. The circuit has a 2bit dime counter and a 3 bit nickel
counter for the inputs and outputs indicating the dimes and nickels to dispense, an additional output of NC
will be 1 if the circuit is unable to give change with the coins available, 0 otherwise.
I have generated a black box, truth table, k-map, reduced equations, behavioral dataflow, structural
description, test bench, and timing tables.
My first step to solving this logic circuit was to create a black box, after which I worked on the truth
table, k-map, reduced equations, coding. I spotted if I make the equation run off the NC output being a 1 or 0
I could make a lot of dont cares for the coins on the kmap allowing a simpler design.
While constructing this design I encountered two problems with the timing diagram, RN2 would have
errors until I changed the equation, also RN0 in the finished structural design with propagation delays would
spike when it was not supposed to and I had to place this output as a gate instead of the inverse of NC.
Black Box Design

My K-maps and Truth tables dont cares are derived from NC being a 1, due to this all equations are
anded with ~NC

Source Code Behavioral

module ChangeMaker(D1,D0,N2,N1,N0,NC,RD1,RD0,RN2,RN1,RN0); //ChangeMaker is the

module name and D1,D0,N2,N1,N0,NC,RD1,RD0,RN2,RN1,RN0 are arguments

input D1,D0;

//dimes available

input N2,N1,N0;

output NC;

//nickels available

//no change indicator

output RD1, RD0;

output RN2, RN1, RN0;

assign #6 NC = ~N1 & ~N0 & ~D1 & ~D0

//dimes to return (dispense)

//nickels to return(dispense)

//6 ns delay output NC

| ~N2 & ~N1 & ~N0

| ~N2 & ~D1 & ~D0
| ~N2 & ~N1 & ~D1
| ~N2 & ~N0 & ~D1;

assign #6 RD1 = D1 & ~NC;

assign #6 RD0 = ~D1 & D0 & ~NC;

//6 ns delay output RD1

//6 ns delay output RD0

assign #6 RN2 = ~D1 & ~D0 & N2 & N1 | N2 & N0 & ~D1 & ~D0; //6 ns delay output RN2

assign #6 RN1 = ~D1 & D0 & ~NC;

//6 ns delay output RN1

assign #6 RN0 = RD0 | RD1 | RN2;

//6 ns delay output RN0

endmodule

module ChangeMaker(D1,D0,N2,N1,N0,NC,RD1,RD0,RN2,RN1,RN0); //ChangeMaker is the module name and

D1,D0,N2,N1,N0,NC,RD1,RD0,RN2,RN1,RN0 are arguments
input D1,D0;
input N2,N1,N0;

//dimes available
//nickels available

output NC;
output RD1, RD0;
output RN2, RN1, RN0;

//no change indicator

//dimes to return (dispense)
//nickels to return(dispense)

wire w1,w2,w3,w4,w5,w6;
wire c1,c2;

//wires to connect to OR gate U4a

//wires to connect to OR gate U4b

wire d1b,d0b,n2b,n1b,n0b;
wire wnc,iwnc;

//wires for inverse input

//wires for NC output and inverce nc inputs

wire wrn1rd0,wrn2,wrd1;

//wire for RD1 output and RN0 output

/* Boolean Functions for the ChangeMaker

RN2 = ~D1*~D0*~wNC
RN1 = ~D1*D0*~wNC
RN0 = ~wNC
RD1 = D1*~wNC
RD0 = ~D1*D0*~wNC
NC = wNC

*/

not #(130.6)

//prop delay

U1a(n2b,N2),
U1b(n1b,N1),
U1c(n0b,N0),
U1d(d1b,D1),
U1e(d0b,D0);
and #(150,8)

//inverted N2 or ~N2
//inverted N1 or ~N1
//inverted N0 or ~N0
//inverted D1 or ~D1
//inverted D0 or ~D0
//prop delay

U2a(w2,n2b,n1b,n0b),
U2b(w3,n2b,d1b,d0b),
U2c(w4,n2b,n1b,d1b),
U3a(w5,n2b,n0b,d1b);
and #(165,9)

input inverses

wires for OR gate U6a and U6b

//gate for w2
//gate for w3
//gate for w4
//gate for w5
//prop delay

U4a(c1,N2,N1,d1b,d0b),
U4b(c2,N2,N0,d1b,d0b);

wires for OR gate U6c

//gate for c1
//gate for c2

and #(165,9)

//prop delay

U5a(w1,n1b,n0b,d1b,d0b);
or #(150,8)

wires for OR gate U4b

//w1 for OR gate U6a

//prop delay

U6a(w6,w2,w3,w1),
//gate cascade to U6b
U6b(wnc,w6,w4,w5),
//gate to wire wnc which is the output NC
U6c(wrn2,c1,c1,c2),
//gate for wire wrn2 which goes to RN2 output
U7a(RN0,wrn1rd0,wrn2,wrd1);
//gate for RN0 output
not #(130.6)
U1f(iwnc,wnc);

and #(150,8)

//prop delay

//inverted wNC or ~wNC wire for gates and the output RN0

//prop delay

U3b(wrn1rd0,d1b,D0,iwnc),
U3c(wrd1,D1,iwnc,iwnc);
assign
NC=wnc,
RN2=wrn2,
RN1=wrn1rd0,
RD0=wrn1rd0,
RD1=wrd1;
endmodule

input inverse

//gate for wire which goes to output RN1,RD0

//gate for wire wrd1 which goes to output RD1

//output assignments
//wire wnc to output NC
//wire wrn2 to output RN2
//wire wrn1rd0 to output RN1
//wire wrd1rd0 to output RD0
//wire wrd1 to output RD1

Sourcecode test bench

module ChangeMakerTest();
reg [4:0] A;
wire NC,RD1,RD0,RN2,RN1,RN0;
integer LoopCounter;

//inputs

//outputs

//counter for the for loop

ChangeMaker
cm0(.D1(A[1]),.D0(A[0]),.N2(A[4]),.N1(A[3]),.N0(A[2]),.NC(NC),.RD1(RD1),.RD0(RD0),.RN2(RN2),.RN1(RN1),.RN0(RN0));
//instantiated Changemaker module with assignments by name
//begin testing values
initial
begin
//for loop
for(LoopCounter=0; LoopCounter<32; LoopCounter=LoopCounter+1)
begin
#10000 A=LoopCounter;
//hold for 1000ns, set the input value
end
#10000 $finish();
end
endmodule

//end of test bench

Timing tables
Behavioral

Structural

QTY

BILL OF MATERIALS
NOMENCLATURE

DESCRIPTION

X1
X2
X2
X2

cd74hct04
cd74hct4075
cd74hct21
cd74hct11

6 INVERTERS
TRIPLE 3 INPUT OR GATE
DUAL 4 INPUT AND GATE
TRIPLE 3 INPUT AND GATE

Worst case propagation delay

NC=595ns
RN2=445ns
RN1=875ns
RN0=1025ns
RD1=875ns
RD0=875ns