TM

DDR4 Verification IP
Truechip's DDR4 Verification IP provides an effective
& efficient way to verify the components interfacing
with DDR4 interface of an ASIC/FPGA or SoC.
Truechip's DDR4 VIP is fully compliant with Standard
DDR4 Version JESD79-4 specification from JEDEC. This
VIP is a light weight VIP with easy plug-and-play
interface so that there is no hit on the design time and
the simulation time.

Deliverables

DDR4-SDRAM Model
DDR4 Monitor & Scoreboard
DDR4 Memory Controller BFM/Agent
Test-Bench Configurations
Test Suite (Available in Source code)
Basic Protocol Tests
Directed & Random Tests
Assertions & Cover Point Tests
Integration Guide, User Manual and Release Notes

Features
Key Benefits
Available in native SystemVerilog
(UVM/OVM/VMM) and Verilog
Unique development methodology to
ensure highest levels of quality
Availability of various Regression Test Suites
24X5 customer support
Unique and customizable licensing models
Exhaustive set of assertions and cover
points with connectivity example for all the
components
Consistency of interface, installation,
operation and documentation across all our
VIPs
DDR4 SDRAM VIP

TESTBENCH
TESTS

DDR4 Monitor

Dummy
Access
Manager

DDR4
Memory
Controller
DUT/BFM

DDR4 Interface

DDR4
Scoreboard

DDR4
SDRAM
Model
BFM/DUT

Compliant to JEDEC DDR4 SDRAM Specification version JESD79-4

Supports connection to any DDR4 Memory Controller IP
communicating with a JESD79-4 compliant DDR4 Memory Model
Supports configurable data buses of different sizes (x4, x8, and x16)
Available in all memory sizes from 2 Gb to 16 Gb
Supports CRC computation/validation across the data bus.
Supports Data Bus Inversion(DBI)
Supports configurable timing parameters and rank associations
Supports capturing all the valid DDR4 commands including Active,
Read, Write, Precharge
Supports CA parity for command/address bus
Supports Power-up Reset and initialization sequences
Supports Precharge Power-Down, Active Power-Down, Self-Refresh
operation
Reports various timing error signals, which can be used to check for
any timing errors
Provides full control to the user to enable / disable various types of
messages
Integrates easily in any verification environment
Supports full timing models or bus functional models
Multiple instances of Monitor can be instantiated in a Verification
Environment to support multiple Chip Selects
Supports advanced SystemVerilog features like constrained random
testing
Supports Callback / User Configuration in Monitor, Controller and
Memory Model BFMs
Supports wide variety of Dynamic as well as Static Error Injection
scenarios

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