Professional Documents
Culture Documents
Eighth Edition
Sampling
Principles of SDR
Technology
Products
Applications
Summary
Links
by
Rodger H. Hosking
Vice-President & Cofounder of Pentek, Inc.
Pentek, Inc.
One Park Way, Upper Saddle River, New Jersey 07458
Tel: (201) 818-5900 Fax: (201) 818-5904
Email: info@pentek.com http://www.pentek.com
Copyright 1998, 2001, 2003, 2006, 2008, 2009, 2010 Pentek Inc.
Last updated: January 2010
All rights reserved.
Contents of this publication may not be reproduced in any form without written permission.
Specifications are subject to change without notice.
Pentek, GateFlow, ReadyFow and VIM are registered trademarks of Pentek, Inc.
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Preface
2
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Sampling
Before we look at SDR and its various implementations in embedded systems, well review a theorem
fundamental to sampled data systems such as those
encountered in software defined radios.
fs/2
fs
Frequency
3fs/2
2fs
5fs/2
3fs
7fs/2
Nyquists Theorem:
Any signal can be represented by discrete
samples if the sampling frequency is at least twice
the bandwidth of the signal.
Zone 1
Zone 2
Zone 3
Zone 4
Zone 5
Zone 6
Zone 7
Figure 1
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Sampling
Sampling Basics
fs/2
fs
3fs/2
2fs
5fs/2
3fs
7fs/2
fs/2
fs
3fs/2
Energy
Baseband Sampling
2fs
5fs/2
3fs
7fs/2
No Signal Energy
Zone 1
Zone 2
Zone 3
Zone 4
Zone 5
Zone 6
Zone 7
Zone 1
Figure 2
Zone 3
Zone 4
Zone 5
Zone 6
Zone 7
Figure 4
Folded Signals
Fall On Top of
Each Other
Zone 2
fs/2
Figure 3
4
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Sampling
Undersampling
fs/2
fs
3fs/2
2fs
5fs/2
No Signal Energy
Zone 1
Zone 2
3fs
Folded signals
still fall on top of
each other - but
now there is
energy in
only one sheet !
7fs/2
fs/2
No Signal Energy
Zone 3
Zone 4
Zone 5
Zone 6
Zone 7
Figure 5
Figure 6
Summary
Baseband sampling requires the sample frequency to
be at least twice the signal bandwidth. This is the same
as saying that all of the signals fall within the first
Nyquist zone.
Also note that the odd zones fold with the lower
frequency at the left (normal spectrum) and the even
zones fold with the lower frequency at the right (reversed
spectrum).
5
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Principles of SDR
SPEAKER
ANTENNA
MIXER TRANSLATES
INPUT SIGNAL BAND
to IF FREQUENCY
ANALOG
MIXER
RF
AMP
IF AMP
(FILTER)
DEMODULATOR
(Detector)
Signal
AUDIO
AMP
ANALOG LOCAL
OSCILLATOR
ANALOG
LOCAL
OSCILLATOR
FIF
FRF
Figure 8
Figure 7
6
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Principles of SDR
RF
TUNER
Analog
IF Signal
A/D
CONV
Digital IF
Samples
DIGITAL
MIXER
Digital
Baseband
Samples
LOWPASS
FILTER
DSP
DIGITAL
LOCAL
OSC
Figure 9
Signal
MIXER TRANSLATES
INPUT SIGNAL
BAND to DC
IF BW
DIGITAL LOCAL
OSCILLATOR
FLO = FSIG
Figure 10
FSIG
7
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Principles of SDR
A/D
CONV
90O
Digital IF
Samples
DIGITAL
MIXER
Filtering
LOWPASS
FILTER
Digital
Baseband
Samples
DIGITAL
LOCAL
OSC
Tuning Freq
F1
F2
Decimation
F3
Figure 12
Decimated
Filter Output
8
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Principles of SDR
Digital
Baseband
Samples
DSP
INTERPOLATION
FILTER
Fs/N
Digital
Baseband
Samples DIGITAL
Digital IF
Samples
MIXER
Fs
Fs
DUC
Digital Up
Converter
D/A
CONV
Analog
IF
Signal
RF
Upconverter
Analog
RF
Signal
Power
Amplifier
DIGITAL
LOCAL
OSC
Figure 13
Digital
Baseband
Samples
Fs/N
INTERPOLATION
FILTER
Digital
Baseband
Samples DIGITAL
MIXER
Fs
DUC
Digital Up
Converter
Digital IF
Samples
Fs
DIGITAL
LOCAL
OSC
Figure 14
9
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Principles of SDR
Fs
INTERPOLATING
LOW PASS
FIR FILTER
BASEBAND
INPUT
Digital
Baseband
Samples
I
Q
Fs/N
INTERPOLATED
OUTPUT
Digital
Baseband
Samples
INTERPOLATION
FILTER
Fs
DUC
Digital Up
Converter
DIGITAL
MIXER
Fs
DIGITAL
LOCAL
OSC
INTERPOLATION
FACTOR = N
INTERPOLATED
BASEBAND INPUT
Baseband Input
Digital IF
Samples
TRANSLATED OUTPUT
MIXER
LOCAL
OSCILLATOR
F = IF Freq
Interpolating
Filter Output
Sample Rate: Fs
Figure 15
IF Freq
Figure 16
10
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Principles of SDR
DDC Processing
A/D
CONV
DUC Processing
Translation
Filtering
DIGITAL
MIXER
LOWPASS
FILTER
Fs
DIGITAL
LOCAL
OSC
DSP
Fb
Fb
Translation
INTERPOLATE
FILTER
DIGITAL
MIXER
D/A
CONV
Fs
N
N
Deci mation
Inter polation
Bandwidth
Bandwidth
Freq uency
Tuning
DSP
Filtering
DIGITAL
LOCAL
OSC
Freq uency
Tuning
Figure 18
Figure 17
The bandwidth knob represents the programmability of the decimation factor to select the desired
baseband signal bandwidth.
11
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Principles of SDR
A/D
CONV
Digital IF
Samples
DIGITAL
MIXER
SDR Tasks
LOWPASS
FILTER
Fs/N
Fs
DIGITAL
LOCAL
OSC
Digital
Baseband
Samples
Fs/N
Digital
Baseband
Samples
INTERPOLATION
FILTER
DUC
Digital Down
Converter
Digital
Baseband
Samples DIGITAL
MIXER
Fs
DUC
Digital Up
Converter
Digital IF
Samples
Fs
D/A
CONV
DIGITAL
LOCAL
OSC
Figure 19
Figure 20
12
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Technology
Schematic processors
Boolean processors
Gates, registers, counters, multipliers
Control logic
Glue logic
Figure 22
Often these programmable logic devices were onetime factory-programmed parts that were soldered down
and never changed after the design went into production.
13
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Technology
Figure 23
Figure 24
14
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Technology
Parallel Processing
Hardware Multipliers for DSP
FPGAs can now have over 500 hardware multipliers
Flexible I/O
Supports a variety of devices, buses and interface standards
High Speed
Available IP cores optimized for special functions
Figure 26
Figure 25
15
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Technology
Model
Model
Feature
Feature
7141-430
7141-430
7141-420
7141-420
7142-428
7142-428
7151
7151
7152
7152
7153
7153
Input
InputChannels
Channels
11
22
44
44
44
44
Max
MaxSample
SampleRate
Rate
125
125MHz
MHz
125
125MHz
MHz
125
125MHz
MHz
200
200MHz
MHz
200
200MHz
MHz
200
200MHz
MHz
Input
Input Resolution
Resolution
14-Bit
14-Bit
14-Bit
14-Bit
14-Bit
14-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
DDC
DDCChannels
Channels
256
256
22or
or44
44
256
256
32
32
22or
or44
Decimation
DecimationRange
Range
1K-10K
1K-10K
Core:
Core:2,4,8,16,32,64
2,4,8,16,32,64
GC4016:
GC4016:32to
32to16k
16k
22to
to64K
64K
Steps
Stepsof
of11
128
128to
to1024
1024
Steps
Stepsof
of64
64
16
16to
to8192
8192
Steps
Stepsof
of88
22Ch:
Ch:22to
to65536
65536
44Ch:
Ch:22to
to256
256
No.
No.of
ofFilter
FilterTaps
Taps
24*DEC/512
24*DEC/512
Core:
Core:28*DEC
28*DEC
28*DEC
28*DEC
24*DEC/64
24*DEC/64
28*DEC/8
28*DEC/8
28*DEC
28*DEC
Power
PowerMeters
Meters
None
None
None
None
None
None
None
None
32
32
22or
or44
Thresh
ThreshDetectors
Detectors
None
None
None
None
None
None
None
None
32
32
22or
or44
Channel
ChannelSummers
Summers
None
None
None
None
None
None
None
None
32
32channels
channels
22or
or44channels
channels
Output
OutputFormat
Format
Normal
NormalI/Q
I/Q
I/Q,
I/Q,Offset,
Offset,
Inverse,
Inverse,Real
Real
I/Q,
I/Q,
Offset,
Offset,Inverse
Inverse
I/Q,
I/Q,
Offset,
Offset,Inverse
Inverse
I/Q,
I/Q,
Offset,
Offset,Inverse
Inverse
I/Q,
I/Q,
Offset,
Offset,Inverse
Inverse
Output
OutputResolution
Resolution
16-Bit
16-Bit
16-Bit,
16-Bit,24-Bit
24-Bit
16-Bit,
16-Bit,24-Bit
24-Bit
16-Bit,
16-Bit,24-Bit
24-Bit
16-Bit,
16-Bit,24-Bit
24-Bit
16-Bit,
16-Bit,24-Bit
24-Bit
Tuning
TuningFrequency
Frequency
32-bits
32-bits--00to
toFs
Fs
32-bits
32-bits--00to
toFs
Fs
32-bits
32-bits--00to
toFs
Fs
32-bits
32-bits--00to
toFs
Fs
32-bits
32-bits--00to
toFs
Fs
32-bits
32-bits--00to
toFs
Fs
Phase
PhaseOffset
Offset
--
32-bits
32-bits180
180deg
deg
32-bits
32-bits180
180deg
deg
32-bits
32-bits180
180deg
deg
32-bits
32-bits180
180deg
deg
32-bits
32-bits180
180deg
deg
Gain
GainControl
Control
32
32bits
bits
32
32bits
bits
32
32bits
bits
32
32bits
bits
32
32bits
bits
32
32bits
bits
DAC
DAC Interpolation
Interpolation
None
None
22--32768
32768
22--32768
32768
None
None
None
None
None
None
Figure 27
16
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Technology
Logic Cells
Slices*
CLB Flip-Flops
Block RAM (kb)
DSP Hard IP
DSP Slices
Serial Gbit Transceivers
PCI Express Blocks
SelectIO
Virtex-II Pro
Virtex-4
Virtex-5
Virtex-6
VP50, VP70
FX, LX, SX
LXT, SXT
53K74K
24K33K
47K66K
4,1765,904
18x18 Multipliers
132328
41K152K
18K68K
49K93K
1,7286,768
DSP48
64512
020
448768
46K156K
7K24K
150K207K
2,1608,784
DSP48E
48640
1216
480640
128K476K
20K74K
160K595K
9,50438,304
DSP48E
4802,016
20
2
600
*Virtex-II Pro and Virtex-4 Slices actually require 2.25 Logic Cells;
Virtex-5 and Virtex-6 Slices actually require 6.4 Logic Cells
Figure 28
17
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Products
PMC, PMC/XMC, CompactPCI, PCI, PCI Express and VMEbus Software Radio
Half-length
PCI Express Board
PCI Board
PMC/XMC Module
CompactPCI Board
Full-length
PCI Express Board
VMEbus Board
Figure 29
18
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Products
Multiband Receivers
Model 7131 PMC
Model 7631A
PCI
Model 7131
PMC
Figure 30
Model 7331
3U cPCI
Model 7231D
6U cPCI
19
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Products
Sample
Clock A In
LVDS Clock A
RF In
TIMING BUS
GENERATOR A
XTL
OSC A
RF In
RF
XFORMR
RF
XFORMR
AD6645
105 MHz
14-bit A/D
AD6645
105 MHz
14-bit A/D
RF Out
LVDS Sync A
Clock/Sync/Gate
Bus A
SYNC
INTERRUPTS
& CONTROL Clock/Sync/Gate
Bus B
LVDS Gate A
TTL Gate/
Trigger
TTL Sync
14
16
16
TIMING BUS
GENERATOR B
Sample
Clock B In
16-bit D/A
16-bit D/A
32
FLASH
16 MB
24
14
XTL
OSC B
To All
Sections
RF XFORMR
GC4016
4-CHANNEL
DIGITAL
RECEIVER
16
LVDS Sync B
LVDS Clock B
RF XFORMR
DAC5686
DIGITAL UPCONVERTER
14
LVDS Gate B
RF Out
16
VIRTEX-II Pro FPGA
XC2VP50
DSP Channelizer Digital Delay Demodulation Decoding Control etc.
Control/
Status
32
DDR
SDRAM
128 MB
Model 7140
PMC/XMC
32
DDR
SDRAM
128 MB
32
DDR
SDRAM
256 MB
PCI BUS
(64 Bits / 66 MHz)
64
PCI 2.2 INTERFACE
(64 Bits / 66 MHz)
8X
64
P15 XMC
P4 PMC
VITA 42.0
FPGA I/O
(Serial RapidIO, (Option 104)
PCI-Express, etc.)
Figure 31
These resources include a quad digital downconverter, a digital upconverter with dual D/A converters, 512 MB DDR SDRAM delay memory and the PCI
bus. The FPGA also serves as a control and status
engine with data and programming interfaces to each of
the on-board resources. Factory-installed FPGA functions
include data multiplexing, channel selection, data packing,
gating, triggering, and SDRAM memory control.
20
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Products
Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores
Model 7140-420 PMC/XMC Model 7240-420 6U cPCI
Model 7340-420 3U cPCI Model 7640-420 PCI
CH A
RF In
RF
XFORMR
AD6645
105 MHz
14-bit A/D
DDC C
DDC D
MEMORY
D/A A
CONTROL
D/A B
&
A/D A
DATA ROUTING
A/D B
Sample
Clock A In
Clock/Sync
Bus
RF
XFORMR
AD6645
105 MHz
14-bit A/D
XTAL
OSC A
A B C D
CLOCK &
SYNC
GENERATOR
Sample
Clock B In
MEMORY
MEMORY
MUX
GC4016 DIGITAL
DOWNCONVERTR
A/D A
A/D B
DDC A
DDC B
M
U
X
WIDEBAND
DIGITAL
DOWNCONVERTR A
DECIMATION: 2 64
A/D A
A/D B
DDC A
DDC B
M
U
X
WIDEBAND
DIGITAL
DOWNCONVERTR A
DECIMATION:.2 64
A B C D
XTAL
OSC B
128 MB DDR
SDRAM
128 MB DDR
SDRAM
256 MB DDR
SDRAM
MEM W
FIFO
MEM W
FIFO
A/D A
FIFO
A/D B
FIFO
WB DDC A
DDC A
WB DDC B
DDC B
MUX
DDC A
FIFO
MUX
DDC B
FIFO
PCI BUS
64 bit /
66 MHz
PCI 2.2
INTERFACE
DDC C
FIFO
CH A
RF Out
RF
XFORMR
CH B
RF Out
RF
XFORMR
16-bit
500 MHZ
D/A
DAC 5686
DIGITAL
16-bit UPCONVERTER
500 MHZ
D/A
MUX
CIC
FILTER
CFIR
FILTER
MUX
MEMORY
D/A A FIFO
MEMORY
D/A B FIFO
DDC D
FIFO
D/A A
FIFO
D/A B
FIFO
INTERPOLATION CORE
XC2VP50
Figure 32
The Pentek IP Core 420 includes a dual highperformance wideband DDC and an interpolation filter.
Factory-installed in the Model 7140 FPGA, they extend
the range of both the GC4016 ASIC DDC and the
DAC5686 DUC.
Like the GC4016, each of the core 420 DDCs
translates any frequency band within the input bandwidth range down to zero frequency. A complex FIR low
pass filter removes any out-of-band frequency components.
An output decimator and formatter deliver either complex
or real data. An input gain block scales both I and Q
data streams by a 16-bit gain term.
21
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Products
RF
XFORMR
AD6645
105 MHz
14-bit A/D
MEM W
FIFO
MEM W
FIFO
CH B
RF In
Sample
Clock A In
Clock/Sync
Bus
RF
XFORMR
AD6645
105 MHz
14-bit A/D
1
DDC 1
Local Oscillator, Mixer, Filter
MUX
XTAL
OSC A
M
U
X
A B C D
CLOCK &
SYNC
GENERATOR
Sample
Clock B In
MUX
GC4016 DIGITAL
DOWNCONVERTR
A B C D
OUT A
DDC A
2
DDC 1
Local Oscillator, Mixer, Filter
255
DDC 255
Local Oscillator, Mixer, Filter
256
DDC 256
Local Oscillator, Mixer, Filter
OUT B
DDC B
OUT C
DDC C
OUT D
DDC D
DDC A
FIFO
M
U
X
DDC B
FIFO
DDC C
FIFO
DDC D
FIFO
PCI 2.2
INTERFACE
INT
XTAL
OSC B
CH A
RF Out
RF
XFORMR
16-bit
500 MHZ
D/A
CH B
RF Out
RF
XFORMR
16-bit
500 MHZ
D/A
PCI BUS
64 bit /
66 MHz
D/A A
FIFO
DAC 5686
DIGITAL
UPCONVERTER
XC2VP50
D/A B
FIFO
Figure 33
22
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Products
LVDS Clock A
RF In
TIMING BUS
GENERATOR A
XTL
OSC A
RF In
RF
XFORMR
RF
XFORMR
LTC2255
AD6645
105
125 MHz
LTC2255
AD6645
105
125 MHz
14-BIT
14-bit A/D
A/D
14-BIT
14-bit A/D
A/D
RF Out
LVDS Sync A
LVDS Gate A
Clock/Sync/Gate
Bus A
SYNC
TTL Gate/
Trigger
INTERRUPTS
& CONTROL Clock/Sync/Gate
Bus B
TTL Sync
14
LVDS Clock B
FRONT
PANEL
CONNECTOR
16
16
Sample
Clock B In
16-bit D/A
16-bit D/A
32
FLASH
24
16 MB
14
XTL
OSC B
To All
Sections
RF XFORMR
GC4016
4-CHANNEL
DIGITAL
RECEIVER
16
LVDS Sync B
TIMING BUS
GENERATOR B
RF XFORMR
DAC5686
DIGITAL UPCONVERTER
14
LVDS Gate B
RF Out
16
VIRTEX-II Pro FPGA
XC2VP50
DSP Channelizer Digital Delay Demodulation Decoding Control etc.
Control/
Status
Model 7141
PMC/XMC
32
DDR
32
DDR
32
DDR
SDRAM
128 MB
SDRAM
128 MB
SDRAM
256 MB
PCI BUS
(64 Bits / 66 MHz)
64
PCI 2.2 INTERFACE
(64 Bits / 66 MHz)
64
P4 PMC
P15 XMC
FPGA I/O
VITA 42.0
(Serial RapidIO, (Option 104)
PCI-Express, etc.)
Figure 34
These resources include a quad digital downconverter, a digital upconverter with dual D/A converters,
512 MB DDR SDRAM delay memory and the PCI
bus. The FPGA also serves as a control and status
engine with data and programming interfaces to each of
the on-board resources. Factory-installed FPGA functions
include data multiplexing, channel selection, data packing,
gating, triggering, and SDRAM memory control.
23
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores
Model 7141-420 PMC/XMC Model 7241-420 6U cPCI Model 7341-420 3U cPCI
Model 7641-420 PCI Model 7741-420 Full-length PCIe Model 7841-420 Half-length PCIe
CH A
RF In
RF
XFORMR
LTC2255
AD6645
125
105 MHz
14-bit A/D
DDC C
DDC D
MEMORY
D/A A
CONTROL
D/A B
&
A/D A
DATA ROUTING
A/D B
Sample
Clock A In
Clock/Sync
Bus
RF
XFORMR
LTC2255
AD6645
125
105 MHz
14-bit A/D
XTAL
OSC A
A B C D
CLOCK &
SYNC
GENERATOR
Sample
Clock B In
MEMORY
MEMORY
MUX
GC4016 DIGITAL
DOWNCONVERTR
A/D A
A/D B
DDC A
DDC B
M
U
X
WIDEBAND
DIGITAL
DOWNCONVERTR A
DECIMATION: 2 64
A/D A
A/D B
DDC A
DDC B
M
U
X
WIDEBAND
DIGITAL
DOWNCONVERTR A
DECIMATION:.2 64
A B C D
XTAL
OSC B
128 MB DDR
SDRAM
128 MB DDR
SDRAM
256 MB DDR
SDRAM
MEM W
FIFO
MEM W
FIFO
A/D A
FIFO
A/D B
FIFO
WB DDC A
DDC A
WB DDC B
DDC B
MUX
DDC A
FIFO
MUX
DDC B
FIFO
PCI BUS
64 bit /
66 MHz
PCI 2.2
INTERFACE
DDC C
FIFO
CH A
RF Out
CH B
RF Out
RF
XFORMR
RF
XFORMR
16-bit
500 MHZ
D/A
DAC 5686
DIGITAL
16-bit UPCONVERTER
500 MHZ
D/A
MUX
CIC
FILTER
CFIR
FILTER
MUX
MEMORY
D/A A FIFO
MEMORY
D/A B FIFO
DDC D
FIFO
D/A A
FIFO
D/A B
FIFO
INTERPOLATION CORE
XC2VP50
Figure 35
The Pentek IP Core 420 includes a dual highperformance wideband DDC and an interpolation filter.
Factory-installed in the Model 7141 FPGA, they extend
the range of both the GC4016 ASIC DDC and the
DAC5686 DUC.
Each of the core 420 DDCs translates any frequency
band within the input bandwidth range down to zero
frequency. A complex FIR low pass filter removes any outof-band frequency components. An output decimator and
formatter deliver either complex or real data. An input gain
block scales both I and Q data streams by a 16-bit gain
term.
24
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
RF
XFORMR
LTC2255
AD6645
125
105 MHz
14-bit A/D
MEM W
FIFO
MEM W
FIFO
CH B
RF In
Sample
Clock A In
Clock/Sync
Bus
RF
XFORMR
LTC2255
AD6645
125
105 MHz
14-bit A/D
1
DDC 1
Local Oscillator, Mixer, Filter
MUX
XTAL
OSC A
2
DDC 1
Local Oscillator, Mixer, Filter
M
U
X
A B C D
CLOCK &
SYNC
GENERATOR
Sample
Clock B In
MUX
GC4016 DIGITAL
DOWNCONVERTR
A B C D
OUT A
DDC A
255
DDC 255
Local Oscillator, Mixer, Filter
256
DDC 256
Local Oscillator, Mixer, Filter
OUT B
DDC B
OUT C
DDC C
OUT D
DDC D
DDC A
FIFO
M
U
X
DDC B
FIFO
DDC C
FIFO
DDC D
FIFO
PCI 2.2
INTERFACE
INT
XTAL
OSC B
CH A
RF Out
RF
XFORMR
16-bit
500 MHZ
D/A
CH B
RF Out
RF
XFORMR
16-bit
500 MHZ
D/A
PCI BUS
64 bit /
66 MHz
D/A A
FIFO
DAC 5686
DIGITAL
UPCONVERTER
XC2VP50
D/A B
FIFO
Figure 36
25
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
LVDS Clock A
RF In
TIMING BUS
GENERATOR A
XTL
OSC A
RF In
RF In
RF In
RF Out
RF
XFORMR
RF
XFORMR
RF
XFORMR
RF
XFORMR
RF
XFORMR
LTC2255
125MHz
INTERRUPTS
14-bit
A/D
Clock/Sync/Gate
& CONTROL
Bus B
LTC2255
125MHz
14-bit A/D
LTC2255
125MHz
14-bit A/D
LTC2255
125MHz
14-bit A/D
16-bit D/A
LVDS Sync A
LVDS Gate A
TTL Gate/
Trigger
TTL Sync
Clock/Sync/Gate
Bus A
SYNC
14
14
14
DAC5686
DIGITAL
UPCONVERTER
14
LVDS Gate B
32
LVDS Sync B
LVDS Clock B
TIMING BUS
GENERATOR B
XTL
OSC B
To All
Sections
VIRTEX-4 FPGA
XC4VSX55
DSP Channelizer Digital Delay Demodulation Decoding Control etc.
Control/
Status
Model 7142
PMC/XMC
32
DDR 2
32
DDR 2
32
DDR 2
SDRAM
256 MB
SDRAM
256 MB
SDRAM
256 MB
64
LOCAL
BUS
32
32
32
HI-SPEED
BUSES
VIRTEX-4 FPGA
XC4VFX60 or XC4VFX100
PCI 2.2
INTERFACE
SERIAL
INTERFACE
PCI BUS
(64 Bits / 66 MHz)
64
P15 XMC
VITA 42.0
P4 PMC
FPGA I/O
(Option 104)
Figure 37
Versions of the 7142 are also available as a PCIe fulllength board (Models 7742 and 7742D dual density),
PCIe half-length board (Model 7842), PCI board
(Model 7642), 6U cPCI (Models 7242 and 7242D dual
density), and 3U cPCI (Model 7342).
26
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Transceivers with Four Multiband DDCs and Interpolation Filter Installed Cores
Model 7142-428 PMC/XMC Model 7242-428 6U cPCI Model 7342-428 3U cPCI
Model 7642-428 PCI Model 7742-428 Full-length PCIe Model 7742-428 Half-length PCIe
CH A
RF In
CH B
RF In
CH C
RF In
CH D
RF In
RF
XFORMR
RF
XFORMR
RF
XFORMR
RF
XFORMR
LTC2255
AD6645
125
105 MHz
14-bit A/D
LTC2255
125 MHz
14-bit A/D
LTC2255
125 MHz
14-bit A/D
LTC2255
125 MHz
14-bit A/D
Sample
Clock In
Clock/Sync
Bus
CLOCK &
SYNC
GENERATOR
XTAL
OSC A
XTAL
OSC B
A/D A
A/D B
A/D C
A/D D
D/A
A/D A
A/D B
A/D C
A/D D
M
U
X
DIGITAL
DOWNCONVERTR A
STAGE 1
DECIMATION: 2 256
DIGITAL
DOWNCONVERTR A
STAGE 2
DECIMATION: 1 256
A/D A
A/D B
A/D C
A/D D
M
U
X
DIGITAL
DOWNCONVERTR B
STAGE 1
DECIMATION: 2 256
DIGITAL
DOWNCONVERTR B
STAGE 2
DECIMATION: 1 256
DIGITAL
DOWNCONVERTR C
STAGE 1
DECIMATION: 2 256
DIGITAL
DOWNCONVERTR
C
.
STAGE 2
DECIMATION: 1 256
A/D A
A/D B
A/D C
A/D D
A/D A
A/D B
A/D C
A/D D
256 MB DDR
SDRAM
MEMORY
CONTROL &
DATA ROUTING
M
U
X
M
U
X
DIGITAL
DOWNCONVERTR D
STAGE 1
DECIMATION: 2 256
DIGITAL
DOWNCONVERTR D
STAGE 2
DECIMATION: 1 256
256 MB DDR
SDRAM
256 MB DDR
SDRAM
MEM W
FIFO
MEM W
FIFO
A/D A
DDC A
A/D B
MUX
A/D A
FIFO
DDC B
A/D C
MUX
A/D B
FIFO
DDC C
A/D D
MUX
A/D C
FIFO
DDC D
MUX
A/D D
FIFO
PCI BUS
64 bit /
66 MHz
PCI 2.2
INTERFACE
RF Out
RF
XFORMR
16-bit
500 MHZ
DAC 5686
16-bit
D/A
500 MHZ
DIGITAL
D/A
UPCONVERTER
CIC
FILTER
CFIR
FILTER
MUX
MEMORY
D/A FIFO
D/A
FIFO
XC4VSX55
INTERPOLATION CORE
Figure 38
The Pentek IP Core 428 includes four highperformance multiband DDCs and an interpolation
filter. Factory-installed in the Model 7142 FPGA,
they add DDCs to the Model 7142 and extend the
range of its DAC5686 DUC.
The Core 428 downconverter translates any frequency
band within the input bandwidth range down to zero
frequency. The DDCs consist of two cascaded decimating FIR filters. The decimation of each DDC can be set
independently. After each filter stage is a post filter gain
stage. This gain may be used to amplify small signals
after out-of-band signals have been filtered out.
27
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
256-Channel DDC Installed Core with Quad 200 MHz, 16-bit A/D
Model 7151 PMC Model 7251 6U cPCI Model 7351 3U cPCI
Model 7651 PCI Model 7751 Full-length PCIe Model 7851 Half-length PCIe
CH A
RF In
RF
XFORMR
ADS5485
AD6645
200
105 MHz
16-bit
14-bit A/D
CH B
RF In
RF
XFORMR
ADS5485
200 MHz
16-bit A/D
CH C
RF In
RF
XFORMR
ADS5485
200 MHz
16-bit A/D
CH D
RF In
Sample
Clock In
RF
XFORMR
ADS5485
200 MHz
16-bit A/D
TIMING BUS
GENERATOR
PPS In
TTL In
Clock / Gate /
Sync / PPS
A/D A
A/D B
A/D C
A/D D
M
U
X
DIGITAL
DOWNCONVERTR
BANK 1: CH 1 - 64
DECIMATION: 128 - 1024
A/D A
A/D B
A/D C
A/D D
M
U
X
DIGITAL
DOWNCONVERTR
.
BANK 2: CH 65 - 128
DECIMATION: 128 - 1024
A/D A
A/D B
A/D C
A/D D
M
U
X
DIGITAL
DOWNCONVERTR
BANK 3: CH 129 - 192
DECIMATION: 128 - 1024
A/D A
A/D B
A/D C
A/D D
M
U
X
DIGITAL
DOWNCONVERTR
BANK 4: CH 193 - 256
DECIMATION: 128 - 1024
MUX
A/D A
FIFO
I&Q
A/D B
DDC BANK 2
MUX
A/D B
FIFO
I&Q
A/D C
DDC BANK 3
MUX
A/D C
FIFO
I&Q
A/D D
DDC BANK 4
MUX
A/D D
FIFO
I&Q
DDC BANK 1
PCI BUS
64 bit /
66 MHz
PCI 2.2
INTERFACE
Sync Bus
XTAL
OSC
XC5VSX95T
Figure 39
The Model 7151 PMC module is a 4-channel highspeed digitizer with a factory-installed 256-channel
DDC core. The front end of the module accepts four
RF inputs and transformer-couples them into four
16-bit A/D converters running at 200 MHz. The
digitized output signals pass to a Virtex-5 FPGA for
routing, formatting and DDC signal processing.
28
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
32-Channel DDC Installed Core with Quad 200 MHz, 16-bit A/D
Model 7152 PMC Model 7252 6U cPCI Model 7352 3U cPCI
Model 7652 PCI Model 7752 Full-length PCIe Model 7852 Half-length PCIe
CH A
RF In
RF
XFORMR
ADS5485
AD6645
200
105 MHz
16-bit
14-bit A/D
CH B
RF In
RF
XFORMR
ADS5485
200 MHz
16-bit A/D
CH C
RF In
RF
XFORMR
ADS5485
200 MHz
16-bit A/D
CH D
RF In
RF
XFORMR
ADS5485
200 MHz
16-bit A/D
Sample
Clock In
TIMING BUS
GENERATOR
M
U
X
A/D A
A/D B
A/D C
A/D D
M
U
X
A/D A
A/D B
A/D C
A/D D
M
U
X
A/D A
A/D B
A/D C
A/D D
M
U
X
PPS In
TTL In
Clock / Gate /
Sync / PPS
Sync Bus
XTAL
OSC
DIGITAL
DOWNCONVERTR I & Q
BANK 1: CH 1 - 8
POWER
DEC: 16 - 8192
METER &
THRESHOLD
DETECT
DIGITAL
DOWNCONVERTR I & Q
BANK 2: CH 9 - 16
POWER.
DEC: 16 - 8192
METER &
THRESHOLD
DETECT
DIGITAL
DOWNCONVERTR I & Q
BANK 3: CH 17 - 24
DEC: 16 - 8192
POWER
METER &
THRESHOLD
DETECT
DIGITAL
DOWNCONVERTR I & Q
BANK 4: CH 25 - 32
POWER
DEC: 16 - 8192
METER &
THRESHOLD
DETECT
8x4
CHANNEL
SUMMATION
SUM
A/D B
MUX
BANK 1
A/D A
FIFO
A/D B
BANK 2 MUX
A/D B
FIFO
A/D C
BANK 3 MUX
A/D C
FIFO
A/D D
BANK 4 MUX
A/D D
FIFO
PCI BUS
64 bit /
66 MHz
PCI 2.2
INTERFACE
XC5VSX95T
Figure 40
The Model 7152 PMC module is a 4-channel highspeed digitizer with a factory-installed 32-channel DDC
core. The front end of the module accepts four RF
inputs and transformer-couples them into four
16-bit A/D converters running at 200 MHz. The
digitized output signals pass to a Virtex-5 FPGA for
routing, formatting and DDC signal processing.
Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples. Any number of channels
can be enabled within each bank, selectable from 0 to 8.
Each bank includes an output sample interleaver that
delivers a channel-multiplexed stream for all enabled
channels within the bank. Gain and phase control, power
meters and threshold detectors are included.
Versions of the 7152 are also available as a PCIe fulllength board (Models 7752 and 7752D dual density), PCIe
half-length board (Model 7852), PCI board (Model 7652),
6U cPCI (Models 7252 and 7252D dual density), or 3U
cPCI (Model 7352).
29
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
4-Channel Beamformer Installed Core with four 200 MHz, 16-bit A/Ds
Model 7153 PMC/XMC Model 7253 6U cPCI Model 7353 3U cPCI
Model 7653 PCI Model 7753 Full-length PCIe Model 7853 Half-length PCIe
CH A
RF In
200 MHz
16-bit A/D
CH B
RF In
200 MHz
16-bit A/D
CH C
RF In
200 MHz
16-bit A/D
CH D
RF In
200 MHz
16-bit A/D
PPS
A/D A
A/D B
A/D C
A/D D
Timing
Clock
Sync
A/D A
A/D B
A/D C
A/D D
XTAL
OSC
Sum Out
M
U
X
DDC 1
DEC: 2 - 256
POWER METER
& THRESHOLD
DETECTOR
DDC 2
DEC: 2 - 256
I&Q
A/D A
A/D B
A/D C
A/D D
M
U
X
M
U
X
A/D B
M
U
X
M
U
X
SUMMER
4X
M
U
X
Aurora
Gigabit
Serial
Interface
A/D A
I&Q
A/D A
A/D B
A/D C
A/D D
Clock
& SYNC
Bus
Sum In
DIGITAL DOWN
CONVERTER CORE
A/D A
A/D B
A/D C
A/D D
Sample
Clock
Gate /
Trigger
P15
XMC
4X
DDC 3
DEC: 2 - 256
A/D C
M
U
X
A/D D
M
U
X
I&Q
PCI-X
Bus
64-bits
100 MHz
DDC 4
DEC: 2 - 256
Gain & Phase Adj
POWER METER
& THRESHOLD
DETECTOR
I&Q
PCI-X
I/F
XC5VSX50T FPGA
Figure 41
In addition to the DDCs, the 7153 features a complete beamforming subsystem. Each channel contains
programable I & Q phase and gain adjustments followed
by a power meter that continuously measures the individual
average power output. The time constant of the averaging
interval for each meter is programmable up to 8 ksamples.
The power meters present average power measurements for
each channel in easy-to-read registers. Each channel also
includes a threshold detector that sends an interrupt to
the processor if the average power level of any DDC
falls below or exceeds a programmable threshold.
30
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Dual SDR Transceivers with 400 MHz A/D, 800 MHz D/A, and Virtex-5 FPGAs
Model 7156 PMC/XMC Model 7256 6U cPCI Model 7356 3U cPCI
Model 7656 PCI Model 7756 Full-length PCIe Model 7856 Half-length PCIe
RF In
Sample Clock In
PPS In
TIMING BUS
GENERATOR
Clock/ Sync /
Gate / PPS
Sample Clk
Sync Clk
Gate A
Gate B
Sync
PPS
RF Out
RF
XFORMR
RF
XFORMR
RF
XFORMR
RF
XFORMR
ADS5474
400 MHz
14-bit A/D
ADS5474
400 MHz
14-bit A/D
800 MHz
16-bit D/A
800 MHz
16-bit D/A
DIGITAL UPCONVERTER
14
14
32
Control/
Status
VCXO
RF Out
RF In
PROCESSING FPGA
To All
Sections
Timing Bus
32
DDR 2
32
DDR 2
SDRAM
512 MB
SDRAM
512 MB
16
64
FLASH
4X
4X
4X
GTP
32 MB
INTERFACE FPGA
VIRTEX-5: LX30T, SX50T or FX70T
Model 7156
PMC/XMC
LVDS
P4 PMC
FPGA
I/O
32
PCI-X
32
64
PCI-X BUS
(64 Bits
100 MHz)
GTP
4X
P15 XMC
VITA 42.x
(PCIe, etc.)
Figure 42
A 5-channel DMA controller and 64 bit/100 MHz PCIX interface assures efficient transfers to and from the module.
Two 4X switched serial ports implemented with the
Xilinx Rocket I/O interfaces, connect the FPGA to the
XMC connector with two 2.5 GB/sec data links to the
carrier board.
31
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Dual SDR Transceivers with 500 MHz A/D, 800 MHz D/A, and Virtex-5 FPGAs
Model 7158 PMC/XMC Model 7258 6U cPCI Model 7358 3U cPCI
Model 7658 PCI Model 7758 Full-length PCIe Model 7858 Half-length PCIe
RF In
Sample Clock /
Reference Clock In
PPS In
TTL Gate / Trig
TTL Sync / PPS
RF Out
RF In
RF
XFORMR
RF
XFORMR
RF
XFORMR
RF
XFORMR
ADS5463
500 MHz
12-bit A/D
ADS5463
500 MHz
12-bit A/D
800 MHz
16-bit D/A
800 MHz
16-bit D/A
DIGITAL UPCONVERTER
Clock/ Sync /
Gate / PPS
Sample Clk
Sync Clk
Gate A
Gate B
Sync
PPS
14
14
Control/
Status
VCXO
RF Out
32
PROCESSING FPGA
VIRTEX 5: LX50T, LX155T, SX50T, SX95T or FX100T
To All
Sections
LVDS
Timing Bus
32
DDR 2
32
DDR 2
SDRAM
256 MB
SDRAM
256 MB
16
64
FLASH
4X
4X
4X
GTP
32 MB
INTERFACE FPGA
VIRTEX-5: LX30T, SX50T or FX70T
Model 7158
PMC/XMC
LVDS
P4 PMC
FPGA
I/O
32
PCI-X
32
64
PCI-X BUS
(64 Bits
100 MHz)
GTP
4X
P15 XMC
VITA 42.x
(PCIe, etc.)
Figure 43
32
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA
Model 71620 - XMC
RF In
Sample Clk /
Reference Clk In
TIMING BUS
GENERATOR
Clock / Sync /
Gate / PPS
RF In
RF In
RF Out
RF Out
RF
XFORMR
RF
XFORMR
RF
XFORMR
RF
XFORMR
RF
XFORMR
200 MHz
16-BIT A/D
200 MHz
16-BIT A/D
200 MHz
16-BIT A/D
800 MHz
16-BIT D/A
800 MHz
16-BIT D/A
DIGITAL UPCONVERTER
14
14
14
32
To All
Sections
VCXO
FPGA
VIRTEX-6 LX130T, LX240T, LX365T, SX95T or SX475T
Control /
Status
Timing Bus
LVDS
16
Model 71620
XMC
16 16
QDRII+
SRAM
8 MB
16
QDRII+
SRAM
8 MB
16
16 16
QDRII+
SRAM
8 MB
16
QDRII+
SRAM
8 MB
DDR3
SDRAM
256MB
DDR3
SDRAM
256MB
DDR3
SDRAM
256MB
GTP
GTP
GTP
16
FLASH
32 MB
P14 PMC
FPGA
I/O
40
x8
P15 XMC
PCIe
x4
x4
P16 XMC
VITA 42.x
Figure 44
The 71620 architecture supports up to four independent memory banks which can be configured with
all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory.
The Model 71620 includes an industry-standard
interface fully compliant with PCI Express Gen. 2 bus
specifications. The x8 lane interface includes multiple DMA
controllers for efficient transfers to and from the module.
33
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Model 6821-422
RF Input
50 ohms
215 MHz
12-Bit A/D
AD9430
Ext Clock In
50 ohms
XTAL
OSC
Fs
LVDS
I/O
128 MB
SDRAM
16 MB
FLASH
32
16
XILINX
VIRTEX-II
PRO FPGA
XC2VP50
CLOCK, SYNC
& TRIGGER
GENERATOR
128 MB
SDRAM
16 MB
FLASH
32
16
XILINX
VIRTEX-II
PRO FPGA
XC2VP50
32
32
4x Switched
Serial Fabric
1.25 GB/sec
4x Switched
Serial Fabric
1.25 GB/sec
VMEbus
32
128k
FIFO
128k
FIFO
32
32
FPDP-II
Out A
Slot 1
FPDP-II
Out C
Slot 2
LVDS
I/O
64
Fs/2
Front
Panel
LVDS
Timing
Bus
32
128k
FIFO
128k
FIFO
32
32
FPDP-II
Out B
Slot 1
FPDP-II
Out D
Slot 2
Model 6821
Figure 45
Because the sampling rate is well beyond conventional ASIC digital downconverters, none are included
on the board.
34
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Model 6822-422
RF Input
50 ohms
Ext Clock In
50 ohms
XTAL
OSC
Fs
128 MB
SDRAM
LVDS Clock
& Sync Bus
16 MB
FLASH
32
16
XILINX
VIRTEX-II
PRO FPGA
XC2VP50
215 MHz
12-Bit A/D
AD9430
128 MB
SDRAM
16 MB
FLASH
Control and Status
To All Sections
32
16
XILINX
VIRTEX-II
PRO FPGA
XC2VP50
4x Switched
Serial Fabric
1.25 GB/sec
VMEbus
32
32
128k
FIFO
128k
FIFO
32
32
FPDP-II
Out A
Slot 1
FPDP-II
Out C
Slot 2
LVDS
I/O
64
CLOCK
GEN
Fs/2
RF Input
50 ohms
LVDS
I/O
215 MHz
12-Bit A/D
AD9430
32
32
4x Switched
Serial Fabric
1.25 GB/sec
128k
FIFO
128k
FIFO
32
32
FPDP-II
Out B
Slot 1
FPDP-II
Out D
Slot 2
Model 6822
Figure 46
Because the sampling rate is well beyond conventional ASIC digital downconverters, none are included
on the board.
35
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
RF INPUT
50 OHMS
2 GHz
10-Bit A/D
AT84AS008
10
4:1
DEMUX
AT84CS001
40
2:1
DEMUX
V4 FPGA
Fs
EXT
CLOCK
INPUT
XTAL
OSC
RF INPUT
50 OHMS
512 MB
DDR RAM
Fs/4
512 MB
DDR RAM
Fs/8 OUT
GATE A IN
GATE B IN
4:1
DEMUX
AT84CS001
Fs/4
Fs/8 IN
FPGA SYNC IN
10
GATE
TRIGGER
& SYNC
64
Fs/8
Fs
2 GHz
10-Bit A/D
AT84AS008
80
40
2:1
DEMUX
V4 FPGA
64
XILINX
VIRTEX-II
PRO FPGA
XC2VP70
80
32
128k
FIFO
32
128k
FIFO
16
VME SLAVE
INTERFACE
4x SWITCHED
SERIAL FABRIC
1.25 GB/SEC
VMEbus
FPDP-II
400 MB/sec
32
FPDP-II
400 MB/sec
32
FPDP-II
400 MB/sec
32
FPDP-II
400 MB/sec
16 MB
FLASH
32
128k
FIFO
32
128k
FIFO
Fs/8
32
4x SWITCHED
SERIAL FABRIC
1.25 GB/SEC
Model 6826
Figure 47
Because the sampling rate is well beyond conventional digital downconverters, none are included on the
board. A very high-speed digital downconverter IP core
36
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Front
Panel
Clock
Input
Front
Panel
Sync
Enable
Front
Panel
Sync
Input
TTL / PECL
SELECTOR
GATE
CONTROL
PROG
DELAY
REG
TTL / PECL
SELECTOR
POWER
SPLITTER
1:2
MUX
2:1
BUFFER
1:2
LVPECL
BUFFER
1:8
POWER
SPLITTER
BUFFER
1:2
1:8
TTL / PECL
SELECTOR
SYNC
CONTROL
REG
PROG
DELAY
BUFFER
1:2
MUX
2:1
TTL / PECL
SELECTOR
LVPECL
BUFFER
1:8
Ch 1
Ch 2
Ch 3 Front
Ch 4 Panel
Ch 5 Gate
Ch 6 Output
Ch 7
Ch 8
Ch 1
Ch 2
Ch 3 Front
Ch 4 Panel
Ch 5 Clock
Ch 6 Output
Ch 7
Ch 8
Ch 1
Ch 2
Ch 3 Front
Ch 4 Panel
Ch 5 Sync
Ch 6 Output
Ch 7
Ch 8
Model 6890
VME
Figure 48
37
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Front Panel
Gate Enable
GATE
CONTROL
Front Panel
GateInput
PROG
DELAY
MUX
2:1
Front Panel
Clock Input
MUX
2:1
BUFFER
1:2
GATE
LVPECL
BUFFER
1:8
REG
CLOCK
LVPECL
BUFFER
MUX
2:1
1:10
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 6
Ch 7
Ch 8
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 6
Ch 7
Ch 8
Clock
Sync
Sync Bus
Output 1
Gate
to Sync Bus
Outputs 2-8
Clock
Sync
Sync Bus
Output 2
Gate
Clock
Sync
Sync Bus
Output 3
Gate
Clock
Sync
to Sync Bus
Outputs 2-8
Sync Bus
Output 4
Gate
Clock
Sync
Sync Bus
Output 5
Gate
Front Panel
Sync Enable
REG
SYNC
CONTROL
Front Panel
Sync Input
PROG
DELAY
BUFFER
1:2
MUX
2:1
MUX
2:1
1:8
Gate
Sync Bus
Input
SYNC
LVPECL
BUFFER
Clock
Sync
Figure 49
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 6
Ch 7
Ch 8
Clock
Sync
Sync Bus
Output 6
Gate
to Sync Bus
Outputs 2-8
Clock
Sync
Sync Bus
Output 7
Gate
Clock
Sync
Sync Bus
Output 8
Model 6891
VME
38
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
CLOCK
SYNTHESIZER
AND JITTER
CLEANER
A
QUAD
VCXO
B
CLOCK
SYNTHESIZER
AND JITTER
CLEANER
B
QUAD
VCXO
C
CLOCK
SYNTHESIZER
AND JITTER
CLEANER
C
QUAD
VCXO
D
CLOCK
SYNTHESIZER
AND JITTER
CLEANER
D
Clock Out
1
Clock Out
2
Clock Out
3
Clock Out
4
Clock Out
5
Model 7190
PMC
Control
Clock Out
6
Clock Out
7
Clock Out
8
NON-VOLATILE
CONFIGURATION
MEMORY
PCI INTERFACE
32
PCI BUS
(32 Bits / 66 MHz)
Figure 50
39
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Model 9190
From
Module
Master
Source
Front
Panel
Input
SMA
Connectors
LVDS
DIFF.
RECEIVER
Timing
Signals
Timing
Signals
LINE
RCVRS
Timing
Signals
Multiplexer
Switches
Clock
Ext. Clock
OPTIONAL
INTERNAL
OSCILLATOR
LVDS
DIFF.
DRIVERS
To
Module
No. 1
LVDS
DIFF.
DRIVERS
To
Module
No. 2
LVDS
DIFF.
DRIVERS
To
Module
No. 80
LINE
DRIVERS
Front
Panel
Output
SMA
Connectors
Figure 51
40
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
Host
PC
Fibre
Channel
Adapter &
DMA
Controller
CLK B
CLOCK
& SYNC
BUS
DUAL
TIMING
BUS
GEN
32
128 MB
SDRAM
32
128 MB
SDRAM
32
256 MB
SDRAM
32
16 MB
FLASH
CH A
OUT
500 MHz
16bit D/A
500 MHz
16bit D/A
320
MHz
DUC
A
B
C
D
GC4016
QUAD
DDC
VIRTEX-II FPGA
CH B
OUT
VME64
UNIV II
Dual PCI
Node
DMA,
&
Memory
Controller
MPC7457
1 GHz
G4
PowerPC
VME
PMC Site
64 bits
66 MHz
PCI Bus 0
XILINX
VIRTEX-II
Pro
FPGA
XC2VP50
64
100 baseT
ETHERNET
PCI Bus 1
64
125 MHz
14bit A/D
CLK A
PCI 2.2
INTERFACE
64 bits/ 66 MHz
PCI Bridge
& DMA
CH B
IN
125 MHz
14bit A/D
PCI Bridge
& DMA
VIRTEX-II FPGA
160 MB/sec
ETHERNET
Fibre Channel
CH A
IN
Front
Panel
Front
Panel
SDRAM
1 GB
FLASH
L3
CACHE
Figure 52
41
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
CH 1 IN
125 MHz
14-BIT A/D
DIGITAL
DOWN
CONVERTER
CH 2 IN
125 MHz
14-BIT A/D
DIGITAL
DOWN
CONVERTER
CH 1 OUT
500 MHz
16-BIT D/A
GIGABIT ENET
DDR
SDRAM
USB 2.0
INTEL
PROCESSOR
SYSTEM
DRIVE
DIGITAL
UP
CONVERTER
PS/2 KEYBOARD
RAID
CONTROLLER
PS/2 MOUSE
CLK A IN
MODEL 7641-420
TRANSCEIVER
CLK B IN
TTL GATE/
TRIG IN
CLOCK
SYNC
BUS
SAMPLE
CLOCK
AND
SYNC
GENERATOR
XTAL
OSC
A
XTAL
OSC
B
DATA
DRIVES
DATA
DRIVES
DATA
DRIVES
DATA
DRIVES
RAID ARRAY
Figure 53
Included with this instrument is Penteks SystemFlow recording software.The RTS 2701 uses a native
NTFS record/playback file format for easy access by user
42
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Products
125 MHz
14-BIT A/D
DIGITAL
DOWN
CONVERTER
CH 2 IN
125 MHz
14-BIT A/D
DIGITAL
DOWN
CONVERTER
CH 1 OUT
500 MHz
16-BIT D/A
CH 1 IN
GIGABIT ENET
HIGH RESOLUTION
VIDEO DISPLAY
USB 2.0
DDR
SDRAM
DIGITAL
UP
CONVERTER
INTEL
PS/2 KEYBOARD
PROCESSOR
SYSTEM
DRIVE
PS/2 MOUSE
CLK A IN
TTL GATE/
TRIG IN
TTL SYNC IN
CLOCK
SYNC
BUS
RAID
CONTROLLER
MODEL 7641-420
TRANSCEIVER
CLK B IN
SAMPLE
CLOCK
AND
SYNC
GENERATOR
XTAL
OSC
A
XTAL
OSC
B
DATA
DRIVES
DATA
DRIVES
DATA
DRIVES
DATA
DRIVES
RAID ARRAY
Figure 54
The Pentek RTS 2721 is a turnkey real-time recording instrument supplied in a convenient briefcase-size
package that weighs just 30 pounds. Built on the
Windows XP professional workstation, it includes an
Intel processor, a high-resolution 17 in. LCD monitor
and a high-performance SATA RAID controller.
The RTS 2721 utilizes the Model 7641 multiband
transceiver PCI module with two 14-bit 125 MHz
A/Ds, ASIC DDC, and DUC with two 16-bit 500 MHz
D/As. The factory-installed IP core 420 provides a
dual wideband DDC and expands the decimation range
of the ASIC DDC. The core also includes an interpolation filter that expands the interpolation factor of the
ASIC DUC.
43
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Applications
44
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Applications
215 MHz
12-Bit A/D
AD9430
128 MB
SDRAM
Delayed Data
FPGA
FFT IP
CORE
Peaks
Power
PC
Controller
Tuning
32
DDC
CORE
32
FIFO
16 MB
FLASH
System Highlights
PowerPC controller also tunes DDC IP core in FPGA to the strongest signal frequencies
Delayed data from SDRAM feeds DDC IP core to compensate for FFT calculation time
DDC captures these moving signals in real time and downconverts them to baseband
Figure 55
45
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Applications
CH A
OUT
125 MHz
14bit A/D
320 MHz
DUC
500 MHz
16bit D/A
CH B
OUT
128 MB
SDRAM
32
128 MB
SDRAM
32
256 MB
SDRAM
32
125 MHz
14bit A/D
XILINX
VIRTEX-II
PRO
CH A IN
CH B IN
CH B IN
CLK A
4
4
64
XILINX
VIRTEX-II
PRO
DUAL TIMING
BUS GEN
CLK B
CLOCK
& SYNC
BUS
VP50
320 MHz
DUC
125 MHz
14bit A/D
CLK A
CLK B
DUAL TIMING
BUS GEN
125 MHz
14bit A/D
CLOCK
& SYNC
BUS
QUAD
DDC
GC4106
VP50
QUAD
DDC
GC4106
32
128 MB
SDRAM
32
128 MB
SDRAM
32
256 MB
SDRAM
4
4
CH B
OUT
PCI INTERFACE
32
PCI
16 MB
FLASH
16 MB
FLASH
P14
XMC
XMC //
PMC
PMC Site
Site
500 MHz
16bit D/A
64
PCI INTERFACE
To VME P2
CH A
OUT
32
PCI
Front Panel
Optical
Interface
FLASH
32 MB
DDR2
SDRAM
FLASH
256 MB
Dual
1000BT
Enet
Quad
RS232C
XMC //
XMC
PMC Site
Site
PMC
1 GB
PCI-X Bus 0
(64 Bits, 100 MHz)
SRIO
8x
4x
PCI-X Bus 1
(64 Bits, 100 MHz)
PCIe
PCIe to
to
PCI-X Bridge
PCI-X
Bridge
Dual
4x
2x
Zero
Latency
Crossbar
Switch
VME64x
2eSST
VME64x
Dual
Dual
4 Gb
4 Gbit
Fibre
Channel
Fibre Channel
Controller
2x
Gigabit
ENET-x
Dual
4x
Dual
4x
2x
VXS VITA 41
Dual
4x
Virtex-4 FPGA
XC4VFX60 / FX100
FLASH
32 MB
DDR2 SDRAM
FLASH
128
MB
1 GB
Figure 56
46
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Applications
CH A
OUT
320 MHz
DUC
500 MHz
16bit D/A
CH B
OUT
128 MB
SDRAM
32
128 MB
SDRAM
32
256 MB
SDRAM
32
64
PCI INTERFACE
XILINX
VIRTEX-II
PRO
VP50
125 MHz
14bit A/D
4
4
CH B IN
CH B IN
XILINX
VIRTEX-II
PRO
VP50
125 MHz
14bit A/D
CLK A
CLK B
DUAL TIMING
BUS GEN
CLK B
CLOCK
& SYNC
BUS
QUAD
DDC
GC4106
125 MHz
14bit A/D
CLOCK
& SYNC
BUS
QUAD
DDC
GC4106
4
4
320 MHz
DUC
32
128 MB
SDRAM
32
IP CORE
430
128 MB
SDRAM
32
256-CHAN
DIGITAL
DOWN
CONVERTER
256 MB
SDRAM
64
500 MHz
16bit D/A
CH B
OUT
PCI INTERFACE
32
P14
XMC
XMC //
PMC
PMC Site
Site
CH A IN
DUAL TIMING
BUS GEN
PCI
To VME P2
CH A IN
CLK A
IP CORE
CORE
IP
430
430
256-CHAN
256-CHAN
DIGITAL
DIGITAL
DOWN
DOWN
CONVERTER
CONVERTER
CH A
OUT
16 MB
FLASH
16 MB
FLASH
2x
PCI
Front Panel
Optical
Interface
32
DDR2
SDRAM
FLASH
32 MB
FLASH
256 MB
Dual
1000BT
Enet
Quad
RS232C
XMC //
XMC
PMC Site
Site
PMC
1 GB
PCI-X Bus 0
(64 Bits, 100 MHz)
SRIO
8x
8x
PCI-X Bus 1
(64 Bits, 100 MHz)
PCIe
PCIe to
to
PCI-X Bridge
PCI-X
Bridge
Dual
4x
2x
Zero
Latency
Crossbar
Switch
VME64x
2eSST
VME64x
Dual
Dual
4 Gb
4 Gbit
Fibre
Channel
Controller
Fibre Channel
2x
Gigabit
ENET-x
Dual
4x
Dual
4x
2x
Dual
4x
Virtex-4 FPGA
XC4VFX60 / FX100
32 MB
FLASH
DDR2 SDRAM
FLASH
128
MB
1 GB
VXS VITA 41
Figure 57
47
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Applications
XILINX
VIRTEX-4
FPGA
125 MHz
14bit A/D
CH C IN
CH D IN
CH A
OUT
125 MHz
14bit A/D
125 MHz
14bit A/D
With
4-chan.
DDC &
Interpol.
Filter
125 MHz
14bit A/D
CLK A
DUAL TIMING
BUS GEN
CLOCK
& SYNC
BUS
16 MB
FLASH
32
XMC
XMC //
PMC
PMC Site
Site
Optical
Interface
500 MHz
16bit D/A
32
256 MB
SDRAM
32
256 MB
SDRAM
32
256 MB
SDRAM
96
VIRTEX-4 FPGA
FX60 or FX100
64
I/O
PCI
XMC
P14
Dual
4x
MPC8641
Single/Dual Core
Front Panel
320 MHz
DUC
DDR2
SDRAM
FLASH
32 MB
FLASH
256 MB
Dual
1000BT
Enet
Quad
RS232C
XMC //
XMC
PMC Site
Site
PMC
To VME P2
1 GB
PCI-X Bus 0
(64 Bits, 100 MHz)
8x
4x
SRIO
PCI-X Bus 1
(64 Bits, 100 MHz)
PCIe
PCIe to
to
PCI-X Bridge
PCI-X
Bridge
Dual
4x
2x
Zero
Latency
Crossbar
Switch
VME64x
2eSST
VME64x
Dual
Dual
4 Gb
4 Gbit
Fibre
Channel
Controller
Fibre Channel
2x
Gigabit
ENET-x
2x
Dual
4x
Dual
4x
VXS VITA 41
Dual
4x
Virtex-4 FPGA
XC4VFX60 / FX100
32 MB
FLASH
DDR2 SDRAM
FLASH
128
MB
1 GB
Figure 58
FPGA. Factory-installed IP cores such as pulse compression and FFT are available and can be factory installed
in this FPGA.
48
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Applications
DDC
SUMMATION
BLOCK
Clock/Sync Cable
200 MHz
16-bit A/D
DDC
200 MHz
16-bit A/D
DDC
200 MHz
16-bit A/D
DDC
VIRTEX-5
FPGAs
CH A IN
CH B IN
CH B IN
CH C IN
CH C IN
CH D IN
CH D IN
DDC
200 MHz
16-bit A/D
DDC
200 MHz
16-bit A/D
DDC
200 MHz
16-bit A/D
DDC
SUMMATION
BLOCK
VIRTEX-5
FPGAs
DUAL TIMING
BUS GEN
CLOCK
& SYNC
BUS
CLOCK
& SYNC
BUS
Aurora
200 MHz
16-bit A/D
CLK A
CLK A
DUAL TIMING
BUS GEN
PCI-X
CH A IN
Aurora
PCI-X
P15
P15
To VME P2
XMC
XMC //
PMC
PMC Site
Site
Dual
1000BT
Enet
MPC8641
Single/Dual Core
FLASH
32 MB
XMC //
XMC
PMC Site
Site
PMC
DDR2
SDRAM
FLASH
256 MB
1 GB
PCI-X Bus 0
(64 Bits, 100 MHz)
SRIO
PCIe
PCIe to
to
PCI-X Bridge
PCI-X
Bridge
Front Panel
Serial
I/O
2x
2x
4x
4x
Dual
Dual
4 Gb
4 Gbit
Fibre
Channel
Fibre Channel
Controller
4x
4x
Zero
Latency
Crossbar
Switch
VME64x
2eSST
VME64x
PCI - X Bus 1
(64 Bits, 100 MHz)
8x
4x
4x
Virtex-4 FPGA
4x
Gigabit
ENET-x
2x
Dual
4x
VXS VITA 41
Aurora Engine
PCI-X Interface
FLASH
32 MB
DDR2 SDRAM
FLASH
128
MB
1 GB
Figure 59
49
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Summary
SDR Benefits
Freescale Altivec G4
PowerPC
Texas Instruments
C6000 DSPs
Single, Dual, Quad and
Octal Processor versions
PMC, PMC/XMC, PCI
and cPCI I/O peripherals
VME/VXS platforms
Figure 60
Since the entire circuitry uses digital signal processing, the characteristics are precise, predictable, and will
not drift with time, temperature or aging. This also
means excellent channel-to-channel matching and no need
for calibration, alignment or maintenance.
Full software development tools are available for workstations running Windows and Linux with many different
development system configurations available.
50
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Links
The following links provide you with additional information about the Pentek products
presented in this handbook: just click on the Model number. Links are also provided to other
handbooks or brochures that may be of interest in your software radio development projects.
Model
Description
Page
7131
7231
7331
7631A
7140
7240
7340
7640
7140-420
7240-420
7340-420
7640-420
7140-430
7240-430
7340-430
7640-430
7141
7241
7341
7641
7741
7841
7141-420
7241-420
7341-420
7641-420
7741-420
7841-420
7141-430
7241-430
7341-430
7641-430
7741-430
7841-430
7141-703
7142
7242
7342
7642
7742
7842
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
23
23
23
23
23
24
24
24
24
24
24
25
25
25
25
25
25
25
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26
26
26
26
26
51
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Links
Model
Description
Page
7142-428
7242-428
7342-428
7642-428
7742-428
7842-428
7151
7251
7351
7651
7751
7851
7152
7252
7352
7652
7752
7852
7153
7253
7353
7653
7753
7853
7156
7256
7356
7656
7756
7856
7158
7258
7358
7658
7758
7858
71620
27
27
27
27
27
27
28
28
28
28
28
28
29
29
29
29
29
29
30
30
30
30
30
30
31
31
31
31
31
31
32
32
32
32
32
32
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Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Links
Model
Description
Page
6821-422
6822-422
6826
6890
6891
7190
7290
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7690
7790
7890
9190
RTS 2504
4205
RTS 2701
RTS 2721
4207
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Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com