M.

TECH VLSI 2015-2016

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PROJECT TITLES

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High - Throughput Finite Field Multipliers Using Redundant Basis For Fpga
And Asic Implementations
A Generalized Algorithm And Reconfigurable Architecture For Efficient And
Scalable Orthogonal Approximation Of Dct
Low Delay Single Symbol Error Correction Codes Based On Reed Solomon
Codes
Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols
Technique For Dsrc Applications
Obfuscating Dsp Circuits Via High-Level Transformations
Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit
Encoding
An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal
Binary Common Sub-Expression Elimination Algorithm For Reconfigurable
Fir Filter Synthesis
Flexible Dsp Accelerator Architecture Exploiting Carry-Save Arithmetic
Low-Latency High-Throughput Systolic Multipliers Over For Nist
Recommended Pentanomials
A Synergetic Use Of Bloom Filters For Error Detection And Correction
Reliable Low-Power Multiplier Design Using Fixed-Width Replica
Redundancy Block
Recursive Approach To The Design Of A Parallel Self-Timed Adder
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
Efficient Sub Quadratic Space Complexity Architectures For Parallel Mpb
Single- And Double-Multiplications For All Trinomials Using Toeplitz MatrixVector Product Decomposition
Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient
Realization Of Multiple Constant Multiplications
Fast Sign Detection Algorithm For The Rns Moduli Set {2n+1 1, 2n 1, 2n}
Algorithm And Architecture For A Low-Power Content-Addressable Memory

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H.NO:8-3-162/A/82,SANJAYNAGAR, YOUSUFGUDA, HYDERABAD..

CONTACT: +91-9160516001, 9676700758,
MAIL ME:KRYPTONITSOLUTIONS@GMAIL.COM

M.TECH VLSI 2015-2016

Based On Sparse Clustered Networks
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Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip

Architectures
Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT
Processors
VLSI Computational Architectures For The Arithmetic Cosine Transform
A Generalization Of Addition Chains And Fast Inversions In Binary Fields
Low-Power And Area-Efficient Shift Register Using Pulsed Latches
Communication Optimization Of Iterative Sparse Matrix - Vector Multiply On
GPUs And FPGAs
A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of
Transducer Capacitance In Piezoelectric Energy Harvesting Systems
Low-Power Programmable PRPG With Test Compression Capabilities
One Minimum Only Trellis Decoder For Non Binary Low - Density Parity Check Codes
A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point
Arithmetic
Mixing Drivers In Clock-Tree For Power Supply Noise Reduction
A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For
Sub-mW Energy Harvesting Applications
Simplified Trellis MinMax Decoder Architecture For Nonbinary LowDensity Parity-Check Codes
New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication
Without Pre-Computation
Fault Tolerant Parallel Filters Based On Error Correction Codes
Comments On Low-Latency Digit-Serial Systolic Double Basis Multiplier
Over GF (2m ) Using Subquadrat Ic Toeplitz Matrix- Vector Product Approach
Skewed-Load Test Cubes Based On Functional Broadside Tests For A LowPower Test Set
Low-Complexity Tree Architecture For Finding The First Two Minima
Efficient Coding Schemes For Fault-Tolerant Parallel Filters

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H.NO:8-3-162/A/82,SANJAYNAGAR, YOUSUFGUDA, HYDERABAD..

CONTACT: +91-9160516001, 9676700758,
MAIL ME:KRYPTONITSOLUTIONS@GMAIL.COM

M.TECH VLSI 2015-2016

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Piecewise-Functional Broadside Tests Based On Reachable States

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A Multicycle Test Set Based On A Two-Cycle Test Set With Constant Primary
Input Vectors
Partially Parallel Encoder Architecture For Long Polar Codes
Novel Block-Formulation And Area-Delay - Efficient Reconfigurable
Interpolation Filter Architecture Formulti - Standard SDR Applications
An Optimized Modified Booth Recoder for Efficient Design of the AddMultiply Operator
Data Encoding Techniques for Reducing Energy Consumption in Network-onChip
A Methodology for Optimized Design of Secure Differential Logic Gates for
DPA Resistant Circuits
Fast Radix-10 Multiplication Using Redundant BCD Codes
A parallel radix-sort-based VLSI architecture for finding the first W
maximum/minimum values
Multifunction Residue Architectures for Cryptography
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low
Adaptation-Delay
32 Bit32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling
Multiplier With Operands Scheduler
Recursive Approach to the Design of a Parallel Self-Timed Adder
Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS
Technique for DSRC Applications
Statistical Analysis of MUX-Based Physical Unclonable Functions
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal FeedThrough Scheme
Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications
for Efficient FIR Filter Implementation
Efficient Integer DCT Architectures for HEVC
Critical-Path Analysis and Low-Complexity Implementation of the LMS
Adaptive Algorithm
A Method to Extend Orthogonal Latin Square Codes

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H.NO:8-3-162/A/82,SANJAYNAGAR, YOUSUFGUDA, HYDERABAD..

CONTACT: +91-9160516001, 9676700758,
MAIL ME:KRYPTONITSOLUTIONS@GMAIL.COM

M.TECH VLSI 2015-2016

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Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR

Digital Filter
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
On the Systematic Creation of Faithfully Rounded Truncated Multipliers and
Arrays
Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2Bit Decoding
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
Low-Complexity Low-Latency Architecture for Matching of Data Encoded
With Hard Systematic Error-Correcting Codes
AreaDelayPower Efficient Carry-Select Adder
Restoration-Based Procedures With Set Covering Heuristics for Static Test
Compaction of Functional Test Sequences
Scalable Montgomery Modular Multiplication Architecture with Low-Latency
and Low-Memory Bandwidth Requirement
Digitally Controlled Pulse Width Modulator for On-Chip Power Management
Input Test Data Volume Reduction for Skewed-Load Tests by Additional
Shifting of Scan-In States
Area-Delay Efficient Binary Adders in QCA
Sharing Logic for Built-In Generation of Functional Broadside Tests

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H.NO:8-3-162/A/82,SANJAYNAGAR, YOUSUFGUDA, HYDERABAD..

CONTACT: +91-9160516001, 9676700758,
MAIL ME:KRYPTONITSOLUTIONS@GMAIL.COM