International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882

Volume 3 Issue 1, April 2014

Analysis of Traff's Current Comparator in 90 nm CMOS Technology

Adyasha Rath1, Subhrajyoti Das2, Sweta Padma Dash3, Geeta Pattnaik4, Adyasa Samantaray5
M.Tech Student, School of Electronics Engineering, KIIT University, Bhubaneswar, India

1, 2,3,4,5

ABSTRACT
In this paper the Traff's current comparator is designed
using a current differencing stage is seen which
compares an input current with a reference current
maintaining high speed and low power. Earlier works
of current comparator neglected the current
differencing stage although the current differencing
stage forms an important part of the current
comparison process. The circuit has been simulated in
Cadence EDA tool in 90nm CMOS process technology
using Spectre simulator. Transient response confirms
the very high speed operation of the Current
Comparator when the current differencing stage is
added.
Keywords current difference, delay, positive
feedback, reference current, Traffs current
comparator

I.

The first CMOS current comparator was proposed by

D. Freitas and K. Current in [1]. Since then, many high
performance current comparators have been proposed.
H. Traff presented a simple and high-speed current
comparator in [2], but the output swing of Traffs
comparator could not reach the power supply rails.
Some generalised implementations of the Traffs
comparator have been carried out in [3] [10].
In this work the Traff's Current comparator [2] shows
improved performance when a current difference stage
is added. Previously current comparators neglected the
current differencing circuit which takes two currents as
input, one as reference current with respect to which
the input current input current is compared.
Simulations were carried out in 90nm process
technology in Cadence using EDA tool.

II.

INTRODUCTION

Comparators have always formed a vital component

for a varied type of analog systems including data
convertors and other front-end signal processing
applications. Many sensors such as temperature
sensors and photo sensors produce current signal as
output which can be compared using a current
comparator. The reduction in device sizes has
motivated the analog designers to design devices using
the current mode approach. Apparently the currentmode approach is found to be advantageous in terms of
speed, bandwidth, and decreased the need of high
supply voltages. However, high performance current
mode comparators have not been frequently published,
and only a few structures exist.
A very crucial component of this ADC is a current
comparator. It is a fundamental building block of
current-mode ADCs in order to increase the
conversion speeds. To a great extent this conversion
speed depends on the current comparator. However, in
current comparator design, trade-off between speed
and power dissipation occurs. A low power design
would mean lower speed and vice versa. The current
comparison process involves injecting one or two
currents into the comparator and distinguishing if the
current (or the difference of two currents) is positive or
negative. Other requirements include low input
impedance and rail-to-rail output voltage swing.

BASIC CURRENT COMPARATOR

CONCEPTS

A current comparator determines if a current signal

exceeds a given threshold and produces an output
voltage. A current-mode comparator receives an input
signal in the form of a current and compares it to a predefined threshold current. The output is in the form of
a voltage.
An ideal current comparator would allow the input
signal to settle very quickly, i.e. there would be no
capacitance on the input and it would be able to take
an infinitely small change in current and convert it into
voltage at the output of the device. Fig 1 shows the
transfer characteristics of an ideal current comparator.
VOL and VOH in the figure denote the limiting values of
the output logical states.

Fig. 1 Current Comparator Characteristics

www.ijsret.org

110

International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 3 Issue 1, April 2014

A current comparator basically consists of three

different stages:
(1)Current Difference Stage
(2)Gain Stage
(3)Output Stage
The current comparator works as follows:
When the reference current(Iref) is greater than the
input current(Iin) the comparator output is logic low
and vice-versa.
Iin>Iref, Vout = 1
Iin>Iref, Vout = 0

III.

TRAFFs CURRENT COMPARATOR

WITH CURRENT DIFFERENCING
STAGE

The current comparator takes current as input and

produces voltage as output. When the input current Iin
is greater than the reference current Iref the output
voltage is logic high i.e is pulled to VDD. Similarly
when the input current is less than the reference
current the output voltage is logic low. In Fig. 2 the
current differencing stage is shown which consists of
transistor M1-M12. The current differencing stage
takes two input currents. Generally for convenience we
take one as input current (Iin) and another as reference
current (Iref). The reference current is the threshold
current with which the input current is to be compared.

Fig. 3 Comparator Stage

The Traff's comparator perfomance was seen when an
extra current differencing stage was added. The circuit
was simulated in Cadence using 90nm process
technology.

IV.

SIMULATION & RESULTS

The current comparator was simulated in 90nm

process technology in Cadence using Spectre
simulator in Virtuoso platform. The reference current
Iref was taken as 1A and the input current Iin was
varied from 0.5A to 1.5A. The input current is
generally taken as Iin = Iref I. I refers to the
difference of input current from the reference current.
In our case the difference current was taken to be, I =
0.5 A. With VDD = 0.9V the transient analysis of the
circuit was carried out as shown in figure. The
transient response shown in Fig. 4 indicates the speed
of the current comparator.

Fig. 2 Current Difference Stage

The Traffs comparator as shown in Fig. 3 consists of
transistors MN-MP which pair up to form a class B
voltage buffer. The transistors M13-M18 form a
cascade of three CMOS inverters. The inverter M13M14 provides a positive feedback at node 1 thus
lowering the input impedance help in producing a railto-rail output voltage.

Fig. 4 Transient Response Analysis

The delay was found to be 0.72ns. Hence the speed of
operation was found to be 1.4GHz. The average power
consumption of the comparator was found to be
116.4W. The PDP of the current comparator was
found to be 0.084pJ.

www.ijsret.org

111

International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 3 Issue 1, April 2014

The corner analysis of the above current comparator

was carried out. It was seen to perform in all corners
i.e TT, FS, SF and SS except the FF corner. The corner
analysis results are seen in Table I.

deceases as current difference between the reference

and input current increases.

TABLE I
Corner Analysis Performance Results of the Current
Comparator
Corner
TT
FS
SF
SS

Delay
(ns)
0.72
0.79
0.69
0.82

Power
(W)
116.4
124.9
88.12
59.93

Slew Rate
(V/ns)
4.399
3.211
6.646
7.675

In Fig. 5 and Fig. 6 the variation of delay and power

with the current difference is plotted.
Fig. 7 Variation of PDP with Current Difference
The layout of the Traff comparator design is done
using Layout XL tool available in Cadence as shown
in Fig. 8.

Fig. 5 Variation of Delay with Current Difference

Fig. 8 Layout of Traffs Comparator in 90 nm CMOS
process technoogy

V.

CONCLUSION

The Traffs current comparator was found to exhibit a

speed of 1.4GHz at a current difference of 0.5 A.
The average power consumption of the comparator
was found to be 116.4W thus making it suitable for
low power applications.

REFERENCES
[1] D. A. Freitas and K. W. Current, "A CMOS
current comparator circuit," Electronics Letters, v. 19.
no. 17, p. 695-697. Aug. 1983.
Fig. 6 Variation of Power with Current Difference
The plot of PDP (Power Delay Product) against current
difference is shown in Fig. 6. It is seen that the PDP

[2] H. Traff, "Novel Approach to High Speed CMOS

Current Comparators", IEEE Proceedings - Electronic
Letters, vol.28, No.3, 1992.

www.ijsret.org

112

International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 3 Issue 1, April 2014

[3]K.W. Current, Current-mode CMOS multiplevalued logic circuits, IEEE J. Solid State Circuits, vol.
29, no. 2, pp. 95-107, Feb.1994.
[4] A.T.K. Tang and C. Toumazou, High performance
CMOS current comparator, Electron. Lett., vol. 30,
pp. 56, 1994.
[5] Byung-moo Min and Soo-won Kim, High
performance CMOS current comparator using resistive
feedback network , IEEE Proceedings - Electronic
Letters, Pages. 2074-2076, vol.34, Issue.22,1998.
[6] Lu Chen, Bingxue Shi, and Chun Lu, A High
Speed/Power Ratio Continuous-Time CMOS Current
Comparator , IEEE Proceedings Electronics,
Circuits and Systems, ICECS-2000, Pages. 883-886,
Vol.2, Dec- 2000.
[7] D.Banks, and C.Toumazou, Low-power highspeed current comparator design, IEEE Proceedings Electronic Letters, vol.44, No.3, 2008.
[8] Tang, X.; Pun, K.-P. "High-performance CMOS
current comparator," Electronics Letters , vol.45,
no.20, pp.1007-1009, September 24 2009.
[9] C.B.Kushwah, D.Soni, and R.S.Gamad, New
Design of CMOS Current Comparator, IEEE
Proceedings ICETET -2009, Pages.125-129, Dec2009.
[10] Chun Wei Lin,and Sheng Feng Lin, Low Input
Impedance Current Comparator Using in Pulse-Width
Modulation,
IEEE
ProceedingsICCE-2010,
Pages.127-130.

www.ijsret.org

113