International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882

Volume 3 Issue 1, April 2014

Analysis and Design of a Low Phase-noise Differential Ring-VCO in 90nm

CMOS Using Half-integral Subharmonic Locking Mechanism
Sweta Padma Dash1, Adyasha Rath2, Anindita Dash3, Geeta pattanaik4, Subhrajyoti Das5
1,2,3,4,5
School of Electronics Engineering, KIIT University ,Bhubaneswar

ABSTRACT
Implementation of a CMOS differential ring- VCO that
locks at half-integral(1.5, 2.5,3.5, .) as well as integral
(1, 2, 3, .) multiples of the injected reference
frequency fref are presented here. Half-integral
subharmonic locking main advantage is that, the output
phase noise can be lowered for a given output frequency
step when using integral subharmonic locking
mechanism because of the higher (2x) reference
frequency. Here a output phase noise of
-133.3dBc/Hz was obtained at 1MHz offset frequency
.At a VCO output frequency of 6.3 GHz when locked to
an integral subharmonic of fref = 528.33 MHz, at delay
of 37.8ps. The ring VCO consumes very less amount of
power i.e. 8.7mW at a supply voltage of 1v also a wide
range of frequency tuning range is obtained i.e. from
1.22GHz 6.55GHz. The ring-VCO was fabricated with
a 90nm CMOS process.

I.

INTRODUCTION

With the continuous advancement of CMOS

technologies circuit blocks are shrinking which is
becoming, very difficult to scale down RF/analog circuit
blocks due to the presence of large circuit elements,
especially passive components. Because of the lack in
scalability of RF/analog circuit blocks has becomes a
serious problem as they consume growing percentage of
expensive Si real estate. Voltage-controlled Ring
oscillators(VCOs) are attractive in terms of frequency
tuning range. Furthermore, they have the particularly
desirable property that inductors can be dispensed with
altogether, which makes ring-VCOs highly scalable. But
they have very poor phase-noise performance as inferior
to that of LC-VCOs' with comparable power
consumption. It has been quantitatively shown [1], [2]
that it is very difficult to lower the phase noise of a ringVCO to an acceptable level on its own without undue
power consumption. Nevertheless, low-phase-noise ringVCO is still a possibility if some noise-suppression
mechanism could be added. One such option would be

injection locking. Phase noise power functions of an

( ) is given by
injection locked VCO
( )=

( ).

( )+

( ).

( )

(1)

( ),
( ) and
( ) are phase noise
Where ,
power functions of an injection-locked VCO, a reference
signal, and a free-running VCO ,respectively, also
( ) and
( ) are low-pass and high-pass
transfer functions, respectively having same cutoff
frequency, which is known as the loop bandwidth.
It is proportional to the power and the frequency of the
injected signal which mainly affects the output noise at
low offset frequencies (relative to the carrier frequency)
and that the VCO noise becomes dominant as the offset
approaches the cutoff frequency.
In this paper, a method of reducing the phase noise with
subharmonically injection-locking mechanism is used
ring-without coarsening the output frequency step.

II. INJECTION LOCKING MECHANISM

The injection-locking mode to be used in VCOs will be
fundamental or subharmonic locking, in which the
frequency
of the injected reference signal is, respectively,
equal to or lower than the VCO output frequency . In
the ordinary integral subharmonic locking, the
subharmonic ratio

is given by l/n, where

n=2, 3, 4,.... Then, if a VCO is to be able to generate

frequencies with a fine step,
has to be low. Phase
noise originating from the VCO cannot be rejected as
efficiently as
and r are halved simultaneously,
because of the loop bandwidth [3]-[5]. As a result
phase noise increases.
To realize scalable low phase-noise high-resolution ringVCOs, proposed ring VCO is exploit to half-integral
subharmonic locking, in which the subharmonic ratio is
given by r =1/1.5,1/2,1/2.5,1/3,....[6]. Figure 1 shows

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 3 Issue 1, April 2014

the phase error correction technique by subharmonic

injection technique.

integral subharmonic locking due to topological

symmetry is explained here.

III. PROPOSED ARCHITECTURE

The proposed ring-VC.O is shown in Fig. 3. It is based
on a four-stage differential ring oscillator. The reference
signal is injected into the delay cell as rail-to -rail pulses
. A schematic of the four stage proposed delay cell with
a voltage controlled differential load is shown in Fig. 4.
The load comprises a pMOS latch, which produces delay
or phaser notation required for satisfying the oscillation
condition. In the commonly-used delay cells with a
pMOS resistive load, the range of the control voltage
that has a reasonable sensitivity is limited to 0 V to the
pMOS threshold voltage.
Fig. 1. Phase error correction
If, injections are given both at the rising and falling
edges of a 50-%-duty-cycle reference signal using half
integral locking mechanism as shown in Fig. 2, phase
error would not accumulate as much as in the case
where only one injection is given every 1/fref.

Fig. 2. Half integral subharmonic injection

Considering a feedback system with nonlinearity[6] an
injection-locked oscillator, can be understood by the
possibility of locking to some non integral
subharmonics. This model is an extension of that for
integral subharmonic locking [7].
However, no explanation has been given as to which
subharmonies might actually be selected for locking.
Considering the symmetry condition the selection rule
for locking frequency can be obtained [8].
In theory, by designing an oscillator so that it possesses
necessary symmetry properties, it can be made to lock to
desired subharmonics.
In the following section ,the architecture is analyzed and
redesigned which is proposed by Kobayashi in 90nm
CMOS process. The design of an injection-locked
CMOS differential ring-VCO which is capable of half

Fig.3. Delay cell

Fig. 4. Four stage ring VCO

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 3 Issue 1, April 2014

In the proposed delay cell, the pMOS transistors PM3

and PM7 are added in order to make the sensitive range
rail-to-rail (0 V to 1 V), thereby offering superior
controllability. Incidentally, this design also makes the
delay cell suitable for the use in PLLs. Those nMOS
transistors are considerably smaller than other transistors
constituting the load. As the control voltage rises, PM3
and PM7 lower the output voltages Vout1 and Vout2
and enhance the latching action . To widen the frequency
tuning range, a simple replica bias circuit is adopted as
shown in fig.5. which reduces the tail current as the
oscillation frequency becomes lower. The ring-VCO has
a frequency -tuning range of 1.22 GHz to 6.55 GHz
when free-running narrow pulses are injected into a
delay cell as shown in fig.4 by switching NM0 and NM1
in Fig . 3. This topology is known as the direct injectionlocking scheme [9]. The amplitude of the reference
pulses is rail-to-rail. This is to ensure that applied and
also to make the switches exhibit nonlinearity.
Otherwise, the symmetry and nonlinearity required for
half integral subharmoni locking could be lost.

Fig. 6. Transient analysis of delay cell

Fig. 7. Phase noise curve of proposed delay cell

Fig. 5. Replica Bias Circuit

IV. MEASUREMENT RESULTS

The circuit is simulated using EDA tool in Cadence
Spectre simulator in Virtuoso ADL environment in
90nm Process. Fig. 6. Shows the transient analysis of the
proposed delay cell. A. 37.8 ps-wide reference input
pulses were injected with
= MHz at output
frequency of = 6.35GHz into the oscillator at a
supply voltage of 1v at control voltage range from 0
0.8V. A wide frequency tuning range is obtained from
1.22GHz 6.55 GHz .

Fig. 8. Layout of the proposed VCRO

A phase noise of- 133.5dBc/Hz is obtained with
injection locking mechanism which is shown in fig. 7.

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 3 Issue 1, April 2014

Table I shows the comparison between different type of

VCOs from which all the analysis were done.

Fig. 8. Shows the layout of the proposed ring oscillator

with a power consumption of 8.7mW.

Table 1. Performance summary and comparison of ring VCOs

Ref.

[14]

[12]

This work

CMOS(nm)

350

130

90

VCO

ring

ring

Ring

(GHz)

0.9

1.6

6.3

Power(mW)

130

5.1

8.7

Offset (MHz)

0.33

Phase noise (dBc/Hz)

-127

-118

-133.3

V. CONCLUSION
A low-phase-noise wide-frequency-range injectionlocked based on a differential ring VCO is proposed
by using a replica bias circuit and pMOS resistive

loads, we successfully suppressed variations in the

spurious level and the phase noise across the tuning
range i.e. -133.3dBc/Hz with a very low power
consumption of 8.7mW with a 81% of tuning range.

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