.

;;

INDIAN INSTITUTE OF TECHNOLOGY, KHARAGPUR

Date: ............ FNIAN, Time: 1:13 Hrs., Full Marks: 60, No of students: 351
Majors: ECFJCSEIEE/IE/QE, 2nd yr B.Tech(H)/B.Afefi(H)!M:Se
End Semester Examination, Semester: Autumn/Spftng, 2012

Subject: Introduction to Electronics (EC21103)

NOTE:

l. All waveform sketches I diagrams must be neatly drawn and clearly labeled.

2. The final answers (numerical values with unit) should be underlined or enclosed within box ~
3. Answers must be brief and to the point. Partial credit will be awarded for correct attempt.

4. For every problem, start your answer from a new page. Avoid writing answers of the various parts of a
single question at different locations in your answer-script.
'5. Assume the following parameter values, unless a parameter value is specifically given with the problem:
Dielectric constants: o = 8.854 X w- [F/rn].
t"r of Si02 =3.9
Boltzmann Constant, k = 1.38 X w- 23 [ J I K]
5 [eVjK]
= 8.617 X
Charge of an electron, q = -1.602 X w- 19 [C]
At room temperature or 300K:
Intrinsic carrier concentration, n; = 1010 [cm- 3 J
Thermal voltage, Vrn = 25.9 X w- 3 [VJ
Mobility of the electrons, Jln = 1400[cm2 /V.s]
sinh(x) = ~(ex- e-x)
Open-loop gain of an ideal OP-AMP (A 0 ) is oo [VIV]
Output resistance of an ideal OP-AMP (Rout) is 0 [Q]
Channel length modulation for NMOS (An)= 0 [V-1]

w-

Mobility of the holes /lp = 500[cm jV.s]

P-N junction reverse saturation current, Is= w- 15 [A]
P-N junction forward cut-in voltage, V-y = 0. 7[V]
P-N junction forward-bias ON-voltage, VDoN = 0. 7[V]
Diode large-signal forward resistance, Rf = O[Q]
Diode break-down voltage, Vsn = oo[V]
Early voltage of BIT, VA = oo[V]
Gate-oxide capacitance. Cox= 3 X w- 8 [Fjcm 2 ]
Channel-length modulation parameter, A= o[V- 1 ]
cosh(x) =~(ex+ e-x)
Input resistance of an ideal OP-AMP (R.;n) is oo (Q]
Bandwidth of an ideal OP-AMP (f3dB )isoo [Hz]
Channel length modulation for PMOS (Ap) 0 [V-1]

6. For any value related to any device parameter or circuit parameter, which you may find not given with a
problem, assume suitable value for such parameter.

1. Consider the MOSFET circuit in Fig. l. The variables and parameters associated with this circuit are listed below.
JlnCox = 100

[11A/V 2], /lpCox

= 50 [tlA/V 2 ], Vrn

= IVrP I = 1 [V],

( ~ )n = ~f~:l, and ( ~ )p = ;1~:1

Voo

Voo

Cz St

Sz

C3

~~~
R4 v
R

Mn

out

Fig. 1
CONTINUED

'
-2-

R1 = R2 = R3 == R4 = R5 = /4; = 5 [KS1), C1 = C2 = C3 = C4 = 10 [JLF],

Vvv = 10 [VJ, VBl = VB2 = 5 [V), Vinl = Vw2 = 1 sin(2000nt) [mV].
Switches 5 1 and 5 2 both are initially closed.
(a) Find the DC drain current (Ivn) and the DC voltage between the drain and the source (Vvsn) of the nMOS Mn.
(b) Find the DC drain current (Ivp) and the DC voltage between the drain and the source (Vvsp) of the pMOS Mp.
(c) Now, switch 5 1 is closed and switch 5 2 is open. Draw the waveforms Vin 1(t) and Vout (t) for two cycles of the
waveform.
(d) Now, switch 51 is open and switch 52 is closed. Draw the waveforms V;n 2 (t) and Vout(t) for two cycles of the
waveform.

(e) Now, switches 5 1 and 5 2 both are closed.

form

Draw the waveform Vout(t) for two cycles of the wave(1,1,2,2,3 marks)

2. Consider the circuit in Fig. 2. The variables and parameters associated with the circuit are given below.
. Vrn = IVrPI = 1 [VJ, JlnCox = 100 [JLA/V 2 ], JlpCox =50 {J1A/V 2 },
Voo

Voo

VOUT

l
Fig. 2

( Tw) n_-

11''mj

11m.

_ (W)
_
an d (w)
T p1T p2-

(b) Assume VIN

= 1 [V]. Find VouT

= 4 [V]. Find VouT

(c) Assume VIN

= 7 [VJ. Find VouT

(a) Assume VIN

21'
'mj uVDD-_ S[V]
11m.

3. In the OP-AMP circuit of Fig. 3 assume R1

(2,2,2 marks)

= R2 = R3 = R4 = R5 = R.
c

CONTINUED

-3-

(a) Find the analytical expression of the closed-loop voltage gain of the circuit assuming ideal OP-AMP. For a
sinusoidal input signal of frequency fin.= 10 [KHz], R = 1 [Kf2]. and C = 1 11F calculate the closed loop
voltage gain.
3

(b) Now assume open-loop voltage gain A 0 = 10 [VjV]. Find the analytical expression of the closed-loop voltage
gain of the circuit. Fot a sinusoidal input signal of frequency f;,. = 10 [KHz], R = I [Kf2], and C = 1 11F
calculate the closed loop voltage gain.
(3,4 marks)

4. Consider the OP-AMP circuit of Fig. 4 using ideal OP-AMP.

R,

VINI

~-'\1\.1\--'-f

VIN2 --'V\fl.r-,..-..,

Fig.4

(a) Find out the simplest expression for the common-mode voltage gain Ac M in terms oft:.
(b) Find out the simplest expression for the differential mode voltage gain Adiff in terms oft:.
(c) Compute the CMRR (Common Mode Rejection Ratio) for~:= 0.1.

(2,2,1 marks)

5. Using the required number of ideal OP-AMPs and other circuit elements, design a circuit that computes the following
input-output relationship:

Vout

= k1 cosh( k2vm), for +ve values of Vin

k 1, k are constants.
2

(5 marks)

6. Consider the OP-AMP circuit of Fig. 5 using ideal OP-AMP.

For the BIT, VsE,ON

= 0. 7 [V]

(if BIT forward-active), (3

= 100, VsAT+ = +5 [V],

VsAr-

-5 [V]. VJN

Fig. 5

2sin(20007Tt) [V].

sl is closed. Draw the waveform Vour(t) for two cycles of the waveform.
Switch sl is open. Draw the waveform Vour(t) for two cycles of the waveform.

(a) Switch
(b)

(1,4 marks)

7. Answer the following questions.

(a) Convert from decimal to octal: (53) 10 .
(b) Convert from hexadecimal to decimal: (BAD) 16
(c) Add the following two base-5 numbers: (0124) 5 and (0421)5.
(d) Subtract (00010101)3 from (00101010)3 in 3's complement form.

(1, I, I ,2 marks)

CONTINUED

-4-

AB
00
CD

01

11

10

01

I'

11

10

00

Fig.6

8. For the K-map in Fig. 6, express the Boolean function, Y = f(A.B,C,D); find the simplest S-0-P (Sum of Products)
and P-0-S (Product of Sums) forms of Y.
(2,2 marks)
9. Implement a 6-input-to-1-output multiplexer whose block diagram is given in Fig. 7(a) using minimum number
of 2-input-to-1-output multiplexers (shown in Fig. 7(b)). Do not use the Control (Select) input values "000" and
"Ill".
(3marks)
S2 Sl SO

2-10-1
MUX

"=6-
AI

Fig. 7(a)

Fig. 7(b)

10. In the state transition diagram of Fig. 8, transition from one state to another state takes place with respect to the rising
edge of the CLK (clock) signal.

Fig. 8

(a) Draw the complete truth table showing the current states (XnYnZn) and next states (Xn+l Yn+!Zn+! ).
(b)
(c)
(d)
(e)

Draw the corresponding state transition matrix.

Draw the complete Kamaugh maps for all three boolean variables that represent the next state.
Find out the boolean expressions of all three variables in S-0-P (Sum of Products) form.
Design a complete circuit using D-FFs and NAND gates. More than 2 inputs are allowed for any NAND
gate.
(1,1,3,3,3 marks)