Professional Documents
Culture Documents
Abstract
The clock gating can enable the clock signals from the
CDN (clock distribution network). This technique could
be activating the clock which is needed for the operation
of the circuit. The unnecessary clock signals are not
activated during the clock gating. This saves the
dynamic power of the circuit. The auto gated flip-flops
which are to be using clock gating technique for only
small power consumption. The novel approach we are
going to design the circuit based on look ahead clock
gating which is to be used for the timing constraints for
each clock pulses. The enabling clock pulses for the
derived timing signals to the gated logic which is to be
saves the power from the flip-flops. The look ahead
technique can also to be reducing the delay and the
distortions from the circuit for the achievement of the
application level. This could be applied into the parallel
bus specific clock gating for application level
implementation. This can be adopted for the all sectional
view from particular architecture implementation. This
process could be available for the structural level
implementation for all the CMOS logic gates for the
integrated chip. This architecture can be designed and
verified by using TANNER EDA tool.
Key points: - Clock Gating, Auto Gated Flip-Flop,
Parallel Bus specific clock gating
I.
INTRODUCTION
www.ijsret.org
192
International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 3, March 2015
II.
EXISTING
SYSTEM
DRIVEN CLOCK GATING
DATA
III.
PROPOSED
SYSTEM
GATED FLIP-FLOP
AUTO
www.ijsret.org
193
International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 3, March 2015
IMPLEMENTATION
OF
AUTO GATED FLIP-FLOP
THE
www.ijsret.org
194
International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 3, March 2015
V.
SIMULATION RESULTS
www.ijsret.org
195
International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 3, March 2015
VI.
CONCLUSION
ACKNOWLEDGEMENT
I wish to acknowledge the efforts of my Project
Guide Mr. Arul Kumar M and the head of the
department Dr.R.Deepa for their guidance which helped
me work hard towards producing this research work.
[4] C. Chunhong, K. Changjun, and S. Majid, Activitysensitive clock tree construction for low power, in
Proc. ISLPED, 2002, pp. 279282.
[5] A. Farrahi, C. Chen, A. Srivastava, G. Tellez, and M.
Sarrafzadeh, Activity- driven clock design, IEEE
Trans. Comput. Aided Des. Integr. Circuits Syst., vol.
20, no. 6, pp. 705714, Jun. 2001.
[6] W. Shen, Y. Cai, X. Hong, and J. Hu, Activity and
register placement aware gated clock network design,
in Proc. ISPD, 2008, pp. 182189.
[7] Synopsys Design Compiler, Version E-2010.12-SP2.
[8] S. Wimer and I. Koren, The Optimal fan-out of
clock network for power minimization by adaptive
gating, IEEE Trans. VLSI Syst., vol. 20, no. 10, pp.
17721780, Oct. 2012.
[9] M. Donno, E. Macii, and L. Mazzoni, Power-aware
clock tree planning, in Proc. ISPD, 2004, pp. 138147.
[10] S. Wimer and I. Koren, Design flow for flip-flop
grouping in data driven clock gating, IEEE Trans. VLSI
Syst., to be published.
[11] M. Muller, S. Simon, H. Gryska, A. Wortmann, and
S. Buch, Low power synthesizable register files for
processor and IP cores, INTEGRATION, The VLSI J.,
vol. 39, pp. 131155, 2006.
[12] A. G. M. Strollo and D. De Caro, Low power flipflop with clock gating on master and slave latches,
Electron. Lett., vol. 36, no. 4, pp. 294295, Feb. 2000.
[13] C. E. Stroud, R. R. Munoz, and D. A. Pierce,
Behavioral model synthesis with Cones, IEEE Design
Test Comput., vol. 5, no. 3, pp. 2230, Jun. 1988.
[14] J. A. Bondy and U. S. R. Murty, Graph Theory. :
Srpinger, 2008.
[15] V. Kolmogorov, Blossom V: A new
implementation of a minimum cost perfect matching
algorithm, Math. Prog. Comp., pp. 4367, 2009.
REFERENCES
[1] V. G. Oklobdzija, Digital System Clocking HighPerformance and Low-Power Aspects. New York, NY,
USA: Wiley, 2003.
[2] L. Benini, A. Bogliolo, and G. De Micheli, A
survey on design techniques for system-level dynamic
power management, IEEE Trans. VLSI Syst., vol. 8, no.
3, pp. 299316, Jun. 2000.
[3] M. S. Hosny and W. Yuejian, Low power clocking
strategies in deep submicron technologies, in Proc.
IEEE Int. Conf. Integr. Circuit Design Technol., ICICDT
2008, pp. 143146.
www.ijsret.org
196