IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO.

3, MAY 1998

487

A Unity Power Factor Converter Using

Half-Bridge Boost Topology
Ramesh Srinivasan, Student Member, IEEE, and Ramesh Oruganti, Member, IEEE

Abstract A single-phase high-efficiency near-unity powerfactor (PF) half-bridge boost converter circuit, which has been
proposed earlier by other researchers, is presented with detailed
analysis. This converter is capable of operating under variable
PF. However, the focus of this paper is in achieving unity PF
operation only. The efficiency of this circuit is high because there
is only one series semiconductor on-state voltage drop at any
instant. The existence of an imbalance in the voltages of the
two dc-link capacitors, which was noted before, is confirmed
here. The cause for the imbalance is analyzed using appropriate
models, and a control method to eliminate it is discussed in detail.
Analysis and design considerations for the power circuit using
the fixed-band hysteresis current control (HCC) technique are
provided. The analytical results are verified through simulation
using switched and averaged circuit models of the scheme and
also through experimental work. At 90-V ac input and 300W 300-V output, the experimental prototype demonstrates an
efficiency of 96.23% and a PF of 0.998. This converter, with
its relatively high dc-output voltage, is well suited for the 110-V
utility supply system. A circuit modification for universal input
voltage range operation is also suggested.
Index TermsHalf-bridge boost topology, IEC 1000-3-2, power
factor correction, switch-mode rectifier.

I. INTRODUCTION

N ORDER to meet the requirements in the proposed

standards such as IEC 1000-3-2 on the quality of the
input current that can be drawn by low-power equipment, a
power-factor-correction (PFC) circuit is typically added at the
utility interface of an acdc switch-mode power supply. The
boost PFC circuit operating in continuous conduction mode
(CCM) is by far the popular choice for medium- and highpower (400 W to a few kilowatts) application. This is because
the continuous nature of the boost converters input current
results in low conducted electromagnetic interference (EMI)
compared to other active PFC topologies such as buckboost
and buck converters.
Some of the popular boost PFC circuits are shown in Fig. 1.
The operation of these circuits and several other issues, such
as control methods, small-signal modeling, and design aspects,
have been studied in detail by several researchers [1][4].
The number of series semiconductor devices at any time is
three in Fig. 1(a) whereas it is two in Fig. 1(b) and (c). Such a
reduction can be expected to improve efficiency significantly.
Considering the circuit in Fig. 1(a) and assuming sinusoidal
Manuscript received August 12, 1996; revised September 3, 1997. Recommended by Associate Editor, F. Tan.
The authors are with the Department of Electrical Engineering, National
University of Singapore, Singapore 11920, Singapore.
Publisher Item Identifier S 0885-8993(98)03347-X.

input current at unity power factor (PF)

input power
and
conduction loss in bridge rectifier
Here,
and
are the rms input voltage and current,
is
the form factor
, and
is the diode forward voltage
drop (assumed to be constant). With only conduction losses
considered
bridge efficiency
(1)
Equation (1) is plotted in Fig. 2 for different values of diode
forward voltage drop. The steep reduction in efficiency at
values, particularly at lower input voltages, suggests
higher
that by reducing the number of devices in series as done in
Fig. 1(b) and (c), one can reduce the total conduction voltage
drop in the semiconductor devices and significantly improve
the overall efficiency of the PFC circuit. The improvement
in efficiency in Fig. 1(b) and (c) is achieved, however, at an
increased cost due to the additional switching devices and to
the replacement of the line rectifier diodes by fast-recovery
diodes.
In this paper, we discuss the use of a half-bridge boost
acdc converter (Fig. 3) for PFC application. Although this
converter can be used for variable PF operation, the focus of
this paper is in achieving unity PF operation only. The main
advantage of this topology is that at any time there is only one
semiconductor on-state voltage drop which may be expected
to result in high operating efficiencies. Reference [5] also
suggests this topology for PFC application. Thus, our effort is
a followup of this earlier work. In the present work, detailed
steady-state analysis of this topology and analytical results
useful to the designer have been developed. Furthermore, a
rigorous explanation of the imbalance in the voltages of the
dc-link capacitors C1 and C2 (Fig. 3) reported in [5] has been
provided in this paper.
will
In the half-bridge circuit (Fig. 3), the output voltage
be at least twice the value of the peak of the input voltage for
proper boost operation (see Section II). Thus, for a 200270V (nominal 230-V) input voltage range, the output voltage
will have to be greater than 760 V. Such a high voltage
will call for high-voltage-rated semiconductor components and
passive elements and also severely stress the devices of any
downstream converter. However, for an 85130-V (nominal

08858993/98$10.00 1998 IEEE

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998

(a)

(b)

(c)
Fig. 1. Circuit variations of the boost PFC topology.

Fig. 3. Half-bridge boost PFC circuit.

Fig. 2. Typical variation of rectifier bridge efficiency with line voltage.

110-V) input voltage range, the output voltage will have to be

greater than 370 V only. This voltage level is well acceptable
and is also adopted currently in many commercial boost PFC
circuits. Thus, the half-bridge PFC is proposed in this paper
as a good option for the 110-V input voltage system. Since
universal input voltage range (85270 V) is often desirable in
many applications, Section VI suggests a circuit modification
for achieving the same.
In this paper, the converter is modeled using an averaged
circuit model (Section II-A1), which uses the pulse-widthmodulation (PWM) switch model proposed in [6]. By replacing the switches with averaged current/voltage sources, the
averaged model of the circuit allows accurate modeling of
the converter with the detailed switching action ignored. The
method is useful both for analytical modeling and for fast
large-signal simulation.
In Section II-A, a detailed analysis of the circuit is presented. The design details of a 300-V (output) 300-W prototype are discussed in Section III. Its operation was first
studied and verified using SABER [7] software simulation.

The simulation (switched model) and experimental results are

presented in Section IV. It was observed from these that the
voltages across the capacitors C1 and C2 are not always
equal in steady state as also noted in [5]. This imbalance
in the voltages can affect the performance of the circuit as
pointed out in the present paper. Section V discusses the
reason for this imbalance and provides details of a control
scheme for eliminating the same. The tradeoffs involved in the
design of this control scheme are discussed in Section V-B1.
The half-bridge converter, using the imbalance control, was
simulated, and also experimentally tested. The simulation
(averaged model) results along with the experimental results
are provided in Section V-B2, demonstrating the effectiveness
of the imbalance control technique.
II. CIRCUIT OPERATION
In Fig. 3, for the control action to be effective throughout
the line cycle, it is essential that the voltage across each of
the capacitors C1 and C2 be maintained to be greater than
the instantaneous value of the line voltage. The well-known
fixed-band hysteresis current control (HCC) technique (Fig. 4)
has been utilized to shape the input current to a sinusoid in
phase with the line voltage. The advantages of this method

SRINIVASAN AND ORUGANTI: UNITY POWER FACTOR CONVERTER USING BOOST TOPOLOGY

(a)

489

(b)

Fig. 4. Current waveforms in HCC technique. (a) Over one line cycle. (b) Over one switching cycle.

(a)

(b)

Fig. 5. The two modes of operation of the half-bridge circuit. (a) Mode 1: positive inductor-current-slope mode. (b) Mode 2: negative inductor-current-slope mode.

Fig. 6. Block schematic representation of a typical closed-loop system for PFC.

are: 1) simple implementation; 2) fast current dynamics; and

3) inherent peak current limiting capability.
is kept to within a
In this technique, the input current
about the reference current wave
by approband
priately switching the devices S1 and S2. Modes 1 and 2
[Figs. 4(b) and 5] correspond to the two modes of circuit
operation. When the inductor current hits the lower bound
is
(LB) at , S1 is turned on (Mode 1). S1 conducts if
greater than zero, otherwise, D1 conducts. In either case, as
the voltage across C1 is greater than the line voltage peak
(boost operation), the inductor current will have a positive
slope. When the inductor current hits the upper bound (UB)
at time , S2 is turned on (Mode 2). S2 or D2 conducts
depending on polarity. Again, as the voltage across the C2 is
always greater than the line voltage peak, the inductor current
will have a negative slope. The downward sloping inductor
current hits the LB at , thus completing one switching cycle.
As the switching frequency is several orders of magnitude

greater than line frequency, the locally averaged (averaged

over the switching cycle) inductor current is made to track
faithfully.
The overall output voltage is the sum of the individual
capacitor voltages and hence must be greater than twice the
input voltage peak. The converter is operated in closed loop
(Fig. 6) in order to regulate the output voltage
to a desired
level.
A. Steady-State Analysis
The aim of the analysis is to: 1) study and predict the
performance of the circuit and 2) establish design equations to
enable the selection of appropriate components for the power
circuit. The following assumptions are made in the analysis.
1) The line voltage varies sinusoidally and is given by the
, where
is the peak line
expression
voltage and
with
being the angular line
frequency.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998

Fig. 7. Averaged circuit model of the half-bridge circuit.

2) As the switching frequency is much higher than the line

frequency, the line voltage is assumed to be constant
during each inductor current switching cycle.
3) The output capacitors are large enough so that their voltage ripples (both the switching frequency and the line
frequency) can be neglected except while determining
the output voltage ripple in Section II-A2. Also, each of
the two capacitors has the same value equal to C.
4) For unity PF operation, neglecting switching compo, where
is the peak line current.
nents,
5) Converter losses are neglected. Therefore, applying inputoutput power balance
(2)
is the output power and is the load current.
where
6) Voltages across capacitors C1 and C2 are both greater
than the peak value of the line voltage . These are
assumed to be
and
, respectively, where
is a constant less than one. From the symmetry of the
circuit, it may appear at first glance that the value of
is exactly 0.5. However, an imbalance in the voltages
exist [5] and is confirmed and explored in Section V.
Using the switched model (Section II-A2), equations for
switching frequency and duty cycle variations over a line cycle
have been obtained. In Section II-A3, equations for: 1) current
through each capacitor; 2) ripple voltage across each capacitor;
3) output voltage ripple; and 4) device current stress have been
derived using the averaged model. The averaged circuit model
approach is discussed briefly in Section II-A1.
1) Averaged Model Versus Switched Model: In the averaged circuit model (Fig. 7), the switch assemblies are
replaced by controlled sources as suggested in [6]. Here,
the bidirectional switch S1-D1 is replaced by a voltage source
of value equal to the average voltage across it over a switching
cycle. This average value is equal to
, where is the
duty cycle of S1. Similarly, S2-D2 is replaced by a current
source
. Here, it must be noted that both switches
cannot be replaced by voltage sources. If this were done, then
the (average) currents through the individual switches cannot
be predicted. Likewise, both the switches cannot be modeled
by current sources. The averaged model can be used to obtain
several steady-state results of the system easily.
Besides steady-state analysis, the averaged model is very
useful in efficient simulation (using SPICE, SABER, etc.) of
complex systems such as the PFC circuit. Both simulation

time and the memory storage requirement for the output are
significantly less than in the simulation using actual switches.
Due to these, unlike with a switched model, the averaged
model simulation can be easily run several times to optimize
converter and controller performance.
The averaged model approach has been verified to give correct results for numerous systems including the one discussed
in this paper (see Section V-B2). It is found to be very useful
in closed-loop compensator design.
Despite the drawbacks in the simulation of the switched
model, it is still useful and necessary in the study of switching
transients and in the determination of quantities such as
peak voltage and current stress of the device, duty ratio,
and switching frequency variations. Thus, the two models
complement each other in their usefulness. The system under
study was simulated using both the averaged and switched
models.
2) Computation of Switching Frequency and Duty Cycle
(Using Switched Model): Referring to Figs. 4(b) and 5, the
expressions for
and
are given by
(3)
(4)
The expression for the switching frequency is therefore given
by

where
(5)
and
maximum switching frequency
It can be shown that

(6)

occurs at an angle
(7)

For equal to 0.5, would be equal to zero and . Thus, (7)

suggests that the maximum switching frequency occurs around
the zero crossings of the line voltage waveform. From (5),
it can also be shown that the minimum switching frequency
occurs at line voltage peaks and is given by

for

where

etc.
(8)

or

for

where

etc.
(9)

SRINIVASAN AND ORUGANTI: UNITY POWER FACTOR CONVERTER USING BOOST TOPOLOGY

491

(a)

(b)

Fig. 8. Variation of switching frequency and duty cycle over a line cycle ( = 0:5). (a) Switching frequency. (b) Duty cycle.

(a)

(b)

Fig. 9. Ripple voltage waveforms across capacitors ( = 0:5) across (a) C1 and (b) C2.

For a special case of equal to 0.5, both (8) and (9) will result
in the same value as may be expected. Fig. 8(a) shows the
variation of the normalized switching frequency
over a line cycle for equal to 0.5. From (3) and (4), the duty
cycle of switch S1 is given by
(10)

a) Low-frequency capacitor voltage ripple: The averaged capacitor currents

and
(Fig. 7) are given by
(14)
(15)
where is the dc-load current. Using (2) and (10) in (14) and
(15) and simplifying
(16)

for
over a line
Fig. 8(b) shows the variation of
cycle. The duty cycle is maximum at the negative peak of the
line voltage and minimum at the positive peak. The maximum
and minimum duty cycles are given by

(17)
The low-frequency capacitor ripple voltages

and

are
(18)

(11)
(19)

(12)
The duty cycle

for switch S2 is given by

The normalized variations of the ripple voltages over the line

cycle for equal to 0.5 and different values of
are shown
in Fig. 9. Unlike the conventional PFCs, the ripple voltages
across the half-bridge capacitors are not sinusoidal. Computing
the maximum and minimum values of (18) and (19) and taking
their differences, the peak-to-peak voltage ripples are

(13)
From (10) and (13), the average duty ratios of S1 and S2 are
and , respectively.
3) Circuit Analysis Using Averaged Model:

(20)

492

Fig. 10.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998

Normalized ripple voltage waveforms. (a)

Vc2 =(Io =!C ), and (c) Vo =(Io =!C ).

Vc1 =(Io =!C ),

(b)

Fig. 12. Variations of the diode and switch average currents with
 = 0:5).

(for

At the maximum value of input voltage

(24)
A more rigorous approach, however, would be to include the
effect of the ripple voltages and solve the resulting complex
inequality. Considering the voltage across C2
(25)

Fig. 11.

Output voltage ripple for

 = 0:48.

(21)
From (18) and (19), the overall output voltage ripple
given by

is

(22)
In Fig. 10, the normalized ripple voltage waveforms are
shown for
equal to 3.23 and for
equal to 0.5. The
output voltage ripple is small compared to the ripples across
the individual capacitors. It may be noted that for values of
different from 0.5, the output voltage ripple is not a pure
second-harmonic as in conventional boost PFCs. This is seen
from the waveform in Fig. 11, which is plotted based on (22)
for equal to 0.48. The line-frequency oscillations in Fig. 11
is also confirmed through simulations and experiments (Section IV). In closed-loop control, the line-frequency oscillations
at the output can increase the total harmonic distortion (THD)
of the input current.
b) Range of values for : As mentioned earlier, the voltages across C1 and C2 must each be greater than the input
voltage over the line cycle. Neglecting all ripple voltages for
C1
(23)

If drifts to a value outside this range, then for a part of the

cycle, the input voltage will be higher than one of the capacitor
voltages: boost action will cease and a large charging current
would be drawn from the ac input during this interval.
c) Device stresses: The peak blocking voltage
for the power switches is equal to output voltage . The peak
current
handled by the switches and the antiparallel
diodes is the input current peak equal to
. However,
to select a switch or a diode and carry out heat-sink design,
it is often the average or the rms current value which is of
greater importance. The averaged model employed here cannot
be used to predict the rms switch current which is influenced
by the switching action. The rms value is more easily obtained
through suitable simulation. In this work, the switch used is
an insulated gate bipolar junction transistor (IGBT) for which
the average value of the current is of greater relevance than
the rms value. Expressions for the device average currents are
obtained easily in the averaged model. It may be noted from
,
, and
the equations below that for
as would be expected
(26)
(27)
(28)
(29)
In Fig. 12, the average currents for
versus the boost
voltage gain
are depicted. The switch average current is
always lower than the diode average current. This suggests

SRINIVASAN AND ORUGANTI: UNITY POWER FACTOR CONVERTER USING BOOST TOPOLOGY

493

TABLE II
POWER CIRCUIT PARAMETERS AND COMPONENT VALUES

not a typical design example, but merely a means to verify

the analysis.
Fig. 13.

Power circuit of the experimental prototype.

DESIGN SPECIFICATIONS

TABLE I
HALF-BRIDGE BOOST PFC CIRCUIT

FOR THE

that the overall conduction loss can be quite small since the
conduction voltage drop of the diode is usually much smaller
than that of the active switch.
III. CIRCUIT IMPLEMENTATION
The implemented single-phase half-bridge converter is
shown in Fig. 13. The design specifications are given in
Table I. Aluminum electrolytic capacitors of value 1000 F
(400 V) with low equivalent-series resistance (ESR) of 80
m each were used for the capacitors C1 and C2. The boost
inductor was constructed from two core sets of Philips EC-70
core (material grade 3C8 ferrite), and the air-gap width was
experimentally adjusted to obtain an inductance of 1.27 mH.
An IGBT allows a fast recovery diode to be externally paralleled across it. Also, IGBTs on-voltage drop is low. Hence,
the IGBT (IRGBC40U) and diode (MUR1560) mounted on
suitable heat sinks were used.
The Unitrode UC3706 driver integrated circuit (IC) fed
by an isolated 15-V supply was used for the gate drive.
The output voltage feedback is obtained through a resistive
divider, while the line current was sensed using a Hall-effect
sensor (LEM module LA 50-P/SP 1). The sinusoidal signal for
shaping the input current was obtained from the line through
a small step-down transformer. The hysteresis band
was
set at 1.7 A. This results in about 20% ripple in the line
current at full-load power. The measured value of
in the
implementation was 1.67 A. The summary of the important
power circuit parameters and component values are presented
in Table II. It must be noted that the experimental circuit is

IV. DISCUSSION OF SIMULATION

AND EXPERIMENTAL RESULTS
Before building the experimental prototype, the operation
of the circuit and results of the analysis were verified using
SABER [7] simulation software. The simulation was done
using both the averaged and switched models. In the switched
model simulation, although a generic switch model was used,
certain nonidealities, such as nonzero on resistance and finite
off resistance of the switch, and practical values for its rise and
fall times were incorporated. Similarly, finite values of ESRs
were used for the inductor and capacitors. These nonidealities
are sometimes essential for the simulation to run.
Excluding component tolerances, the component values
used for the simulation and experimental prototype are identical (Table II). The circuit simulations were performed for 70-,
80-, and 90-V rms input. The simulation waveforms for 90-V
input rms are presented and compared with experimental ones
in this paper.
V,
Figs. 1418 correspond to the conditions
V, and
A. Fig. 14 shows both the
simulated (switched model) and experimental inductor current
waveforms. The operation of the HCC can be verified from the
fixed amplitude of the current ripple. Unlike the conventional
boost converters input current waveform, here there is no cusp
distortion [8] around the zero crossings. This is because even
during the zero crossings there is adequate voltage to drive the
inductor to meet the demanded slope of the reference current
waveform.
The PF of the input current and the values of the input harmonic components were recorded using the Voltechs
PM3000A equipment. A PF of 0.998 was measured. Table III
compares the measured harmonic values with the proposed
IEC 555-2 Class-A harmonic limits [9]. As IEC limits are
for 230 V, the specified IEC limits are multiplied by a factor
of 2.55 to obtain the corresponding harmonic levels for 90V input voltage. Clearly, the magnitudes of the harmonic
components are way below the IEC limits.
The low-frequency voltage ripple on the individual capacitors is shown in Fig. 15. Comparing these waveforms with
that obtained from the analysis (Fig. 9), it is seen that the
waveform shape and nature agree quite well. An imbalance
in the dc-voltage levels in the top (C2) and bottom (C1)

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998

(a)
Fig. 14.

(a)
Fig. 15.

(b)

Input current waveform: (a) simulated (switched model) and (b) experimental.

(b)

Voltage ripple across individual capacitors [(i) across C1 and (ii) across C2]: (a) simulated (switched model) and (b) experimental.

Fig. 16. Imbalance in the capacitor voltage waveforms [(i) voltage across
C1 and (ii) voltage across C2] (experimental).

capacitors was noticed both in experimental (Fig. 16) and

simulation results. The magnitude of imbalance was quite
arbitrary and not repeatable. The resulting line-frequency
harmonic in the overall output voltage ripple waveform is
shown in Fig. 17. These waveforms may be compared with
the analytical waveform in Fig. 11 drawn for an assumed
of 0.48. The reason for the imbalance is discussed in detail
in Section V.
Despite the imbalance, the output voltage can still be
controlled and regulated. Also, the input current waveform
remains unaffected as long as is within its range [see Section
II-A3b]. But there are cases when the imbalance causes the
voltage across one of the capacitors to be lower than the input
voltage peak. During such instances, the input current will be

out of control for the duration for which the input voltage
is greater than the capacitor voltagethe input current then
takes a shape similar to the input current waveform of a typical
rectifier-capacitor-load front-end circuit, as also pointed out in
Section II-A3b.
In Fig. 18, the variation of switching frequency with time
based on simulation (using switched model) is depicted. Com, the effect of
paring this with Fig. 8(a), drawn for
imbalance on the minimum switching frequency may be seen.
A comparison of the analytical, simulation, and experimental
results for the maximum and minimum switching frequencies
measured at 300-W and 300-V output is presented in Table IV.
The results agree quite well. Similar comparisons have been
made for the variations of duty cycle with time as well. These
are not presented here due to lack of space.
The variations of efficiency (measured with Voltechs
PM3000 A equipment) with respect to rms input voltage and
load are shown in Fig. 19. The efficiency is generally high
reaching a maximum of around 96.23% at an input voltage of
90 V and a load power of 225 W.
V. IMBALANCE

IN

CAPACITOR VOLTAGES

Reference [5] has noted the existence of the imbalance in

the capacitor voltages and has also suggested a possible way
of overcoming this. It has been mentioned in [5] that the
imbalance is caused due to some dc offsets in the controllers

SRINIVASAN AND ORUGANTI: UNITY POWER FACTOR CONVERTER USING BOOST TOPOLOGY

COMPARISON

OF THE

HARMONIC COMPONENTS

TABLE III
CURRENT AGAINST

OF THE INPUT

(a)
Fig. 17.

THE

495

PROPOSED IEC-555-2 LIMITS (300-W OUTPUT)

(b)

Output voltage ripple: (a) simulated (switched model) and (b) experimental.

Fig. 18. Variation of switching frequency with time, based on switched

model simulation.

analogue components. However, even the simulation results

obtained by us with ideal components exhibit the imbalance
phenomenon. Also, in [5], the method of overcoming the
imbalance is not discussed in detail. Therefore, in this work
we not only confirm the existence of the imbalance, but also
investigate its causes and provide details of a control scheme
for eliminating the same.
The averaged circuit model shown in Fig. 7 is redrawn
in Fig. 20. Here, the input voltage source and inductor are
replaced by a current source , since it is assumed that the
input current is fully controlled and follows the desired current
template. This model represents the original system even for
large-signal conditions except at the startup (when there may
be an input charging current surge) and for cases when the
is out of its range (Section II-A3b).

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998

(a)
Fig. 19.

(b)

Experimental efficiency results. (a) Variation with line voltage. (b) Variation with load power.

Equations (30) and (31) describe the dynamics of the system

and
across the capacitors C1 and C2,
with the voltages
respectively, being treated as the states of the system. Their
and
respective initial states are denoted by
and
(30)
and

(31)

It must be noted that the system represented by (30) and (31)

is not a linear system. This is because the term in the input
is dependent on the states of the system as seen from the
ratios
and
in the expression for in
(13). Now, let us consider the imbalance variable
defined
as
. Subtracting (31) from (30), the dynamics
of
are given by
and

(32)

Even though (30) and (31) are nonlinear, (32) is a firstorder linear differential equation. The solution of (32), after
substituting for
, is given by
(33)
From (33), it is seen that the imbalance caused by the initial
conditions of the system does not decay with time. The
dependence of the imbalance on the initial conditions, and
also the time at which the input is applied, explains why the
magnitude of the imbalance is arbitrary as observed both in
the experiment and simulation.
B. Elimination of Imbalance
The closed-loop control system with the imbalance control
is shown in Fig. 21. Here, the shaded blocks are extra blocks
added to the system in Fig. 6. The signal
is obtained
after multiplying
(output voltage of the controller
)
with the sinusoidal signal
in phase with the line voltage
waveform. Because of the fast inner current control loop, any
dynamics associated with it may be neglected while studying
the voltage-loop performance. Therefore, in the original system, the input line
is the same as
. The operation

Fig. 20. Model of the half-bridge circuit used to analyze the imbalance in
capacitor voltages.

of the imbalance control is first explained qualitatively and

later validated by mathematical analysis.
In Fig. 21, an additional state of the converter, namely,
is sensed. Our objective here is to force the dc value in
to
zero. This is done by feeding
through a gain block
and adding its output to
(34)
The input current will now track
instead of
.
In the averaged circuit model shown in Fig. 20, the current
source
is therefore replaced by
.
In the absence of any dc-input current component
, the load dc current
in Fig. 20 will flow through the
controlled sources only under steady state. Therefore

where
and
are the dc values of the currents through
the controlled sources.
(i.e.,
). This introduces a positive
Now, let
offset
in
. From (13), the average value
of
is equal to . Therefore, applying Kirchoffs current
for the dc currents, we note that
law (KCL) at junction
will increase by
, whereas
will increase by
(
magnitude will decrease). The dc-current
component
causes C2 to charge upthe component
causes C1 to discharge. As a consequence,
reduces. In steady state, the dc value of
is made
zero through this closed-loop action. In Section V-B1, we

SRINIVASAN AND ORUGANTI: UNITY POWER FACTOR CONVERTER USING BOOST TOPOLOGY

Fig. 21.

497

Closed-loop control system with imbalance control.

COMPARISON

OF

RESULTS

FOR

MAXIMUM

AND

TABLE IV
MINIMUM SWITCHING FREQUENCY

show mathematically that the dc imbalance becomes zero for

and also provides a method for the selection of a
.
suitable value for
In [5], instead of the product
being added to
,
, and the resulting variable
it has been subtracted from
is made to follow
by the current controller. Conceptually, this method is the same as the one discussed in the
previous paragraph. However, there is a significant difference
in the practical implementation. Subtracting
from
entails the use of a high-bandwidth operational amplifier (OA)
without
to pass the switching frequency component in
any appreciable filtering. In the proposed method, however,
has to
only the low-frequency signal
be passed through the OA. Therefore, an inexpensive low
bandwidth OA will suffice.
1) Choice of
: An appropriate value for the gain
may be chosen by considering the dynamics of
with
imbalance control. The input current in (32) is now replaced
by
as obtained in (34) to result in

OF

OPERATION (Po = 300 W

AND

Vo = 300 V)

where
is the time constant and is the variable
of integration. The constant in (36) is obtained by setting
time equal to zero in (38).
As
(Fig. 21) is nearly constant over a line cycle,
will be sinusoidal with no dc offset. The term with the
integral sign in (36) will therefore have only ac components
as seen later in (38). Hence, from (36) it is seen that the dc
imbalance caused by the initial conditions approaches zero
asymptotically in steady state. The settling time
for the
dc imbalance to decay to zero can be estimated to be equal
to
approximately. Making equal to
infinity (i.e.,
) in (36) once again verifies the existence
of the imbalance in the original system.
is given by
Under steady state,
(37)
Substituting (37) in (36) and performing the integration,
under steady state is given by
(38)

and

(35)

Equation (35) is an ordinary first-order differential equation.

Its solution is given by

(36)

Substituting (38) in (34), it is seen that even though the

dc component of
has been eliminated in steady state,
and, hence,
will still have the undesired linefrequency cosine and sine components. The sine component,
due to its negative sign, effectively reduces the amplitude of
the input current, which will cause the output voltage (hence,
the output power) to decrease if the system is not operated
under closed-loop control. For the system operated under
term in
will place more
closed-loop control, the

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998

(a)

(b)

(c)
Fig. 22. Averaged model simulation results after imbalance correction: (a) input current waveform, (b) voltage across individual capacitors [(i) across
C1 and (ii) across C2], and (c) output voltage ripple.

burden on the voltage error amplifier

and may even
result in its saturation. The cosine component causes the line
current to be displaced with respect to the line voltage, thereby
reducing the PF. The larger the value of
, the greater will
, the
be the reduction in PF. However, with a large value of
dc imbalance will settle fast as evident from (36). Therefore, a
design compromise must be made between high PF and small
settling time of the dc imbalance.
Using (34), (37), and (38), it may be shown that
PF

TABLE V
POWER FACTOR VERSUS u : A COMPARISON OF SIMULATED AND
ANALYTICAL RESULTS (@ 90-V INPUT AND 300-W OUTPUT)

real power
apparent power
(39)

Table V shows the close agreement obtained between the

values based on (39) and from
PFs obtained for different
averaged model simulation. It may be noted that for
greater
than 0.03, the PF decreases quite fast. From (39), for realizing
high PF

From Table V
(40)
may be considered as a good choice. This will result in a PF
equal to 0.995 and in a settling time equal to 127 ms, which
is about six and a half line cycles for a 50-Hz power system.

2) Simulation and Experimental Results of the Half-Bridge

Circuit with Imbalance Eliminated: The imbalance elimination technique was implemented in the SABER model as well
as in the experimental setup. The value for
was chosen as
0.02, which gives a value of
of 0.064. Simulations
were performed under different conditions to ensure that
the imbalance was eliminated. Fig. 22 shows one set of
simulation results performed at 90-V input and 300-V 300-W
output. The absence of the imbalance may be noticed clearly
from the output ripple voltage waveforms [Fig. 22(c)] and
from the voltage waveforms across the individual capacitors
[Fig. 22(b)]. These figures may be compared with Figs. 15 and
17 for the case with the imbalance.

SRINIVASAN AND ORUGANTI: UNITY POWER FACTOR CONVERTER USING BOOST TOPOLOGY

(a)
Fig. 23.

499

(b)

Experimental results after imbalance correction: (a) voltage across individual capacitors [(i) across C1 and (ii) across C2] and (b) output voltage ripple.

VII. CONCLUSION

Fig. 24.

Modification of the half-bridge for 230-V input range.

In the experiment, and were sensed conveniently with

was then obtained from these
respect to the power ground:
variables. Both
and
were scaled down to an appropriate
signal level with the same scaling factor equal to . Using
low-bandwidth operational amplifiers,
was then obtained. This was then added to
using a
summer to obtain
. The rest of the experimental circuit
remained the same as in Section III. The experimental results
shown in Fig. 23 were taken for a 90-V input and 300-V 300W output. The absence of the imbalance may be clearly seen
from the individual capacitor voltage waveforms [Fig. 23(a)]
and also from the output voltage ripple [Fig. 23(b)] waveform.
Fig. 23 may be compared with Figs. 16 and 17 for the case
with the imbalance.

VI. MODIFICATION FOR UNIVERSAL INPUT VOLTAGE RANGE

With the half-bridge circuit for the 230-V system, the dc-bus
voltage would be rather high (760 V). Due to this, this circuit
becomes less attractive for the universal input voltage range
(85270 V). However, with a modification (Fig. 24) using
two additional diodes and a single-pole double-throw switch,
the circuit can be made to operate from a 230-V system.
The switch can be implemented using a mechanical relay or
semiconductor devices. If the later is adopted, of course, the
advantage of less switch voltage drop is compromised.
If the switch is thrown to position 1, the half-bridge circuit
(Fig. 3) is suitable for low-input voltage results. Connecting
the switch to position 2 results in a variation of the circuit
arrangement shown in Fig. 1(b), suitable for high-input voltage
range. Although in switch position 2 the series drop has
increased by one, the efficiency may not be affected significantly as the increased voltage drop occurs at higher input
voltages.

A single-phase half-bridge boost circuit for PFC application,

which has been proposed earlier [5], is analyzed in detail. A
fixed-band HCC technique is used to shape the input current
to a sinusoid and in phase with the line voltage. Equations and
waveforms useful to the design engineer have been developed.
The results of the analysis were verified by simulation (both
switched and averaged models) and experiments performed on
a 300-V 300-W experimental prototype. In the experiment, a
PF of 0.998 was achieved at 90-V input and at full load (300
W).
An imbalance in the voltages of the dc-link capacitors,
which was noted in [5], was confirmed. The cause for the
imbalance is analyzed using appropriate models, and a control
method to eliminate the same was also discussed in detail.
This circuit is able to achieve high efficiency of around 96%
under low-input voltage condition due to a reduced number
of semiconductor on-state drops and the use of IGBT. The
reduced number of semiconductor on-state drops makes this
circuit suitable for use in low-input voltage (110-V) systems.
Besides, the bidirectional power flow capability of this circuit
makes it attractive in applications, where arbitrary input PFs
are desired.
The half-bridge circuit as it is is not very suitable for
universal input voltage operation due to the relatively high
dc-output voltage developed. To overcome this drawback, a
modification to the topology has also been suggested.
REFERENCES
[1] N. Mohan, T. M. Undeland, and R. J. Ferraro, Sinusoidal line current
rectification with a 100 kHz B-SIT step-up converter, in IEEE Power
Electronics Specialists Conf. Rec., June 1984, pp. 9298.
[2] F. A. Huliehel, F. C. Lee, and B. H. Cho, Small-signal modeling of
single-phase Boost high power factor converter with constant frequency
control, in IEEE Power Electronics Specialists Conf. Rec., June 1992,
pp. 475482.
[3] R. B. Ridley, Average small-signal analysis of the Boost power
factor correction circuit, Virginia Power Electronics Centre Publication
Series, vol. V, pp. 7991, 1994.
[4] L. Dixon, Average current mode control of switching power supplies,
Unitrode Power Supply Design Seminar Manual, pp. C1-1C1-14, 1991.
[5] J. T. Boys and A. W. Green, Current-forced single phase reversible
rectifier, Proc. Inst. Elect. Eng., vol. 136, pt. B, no. 5, pp. 205211,
1989.
[6] R. P. E. Tymerski, V. Vorperian, F. C. Lee, and W. T. Baumann,
Nonlinear modeling of PWM switch, IEEE Trans. Power Electron.,
vol. 4, no. 2, pp. 225233, 1989.
[7] SABER and POWER EXPRESS Users Guide, Analogy Inc., Beaverton,
OR, 1993.

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[8] P. C. Todd, UC3854 controlled, power factor correction circuit design,

Unitrode Product Applications Handbook, pp. 9-3629-381, 199394.
[9] Disturbances in supply systems caused by household appliances and
similar electrical equipment, Int. Electrotechnical Commission Rep.
555.2, 1994.

Ramesh Srinivasan (S93) received the B.Sc. degree in physics from University of Madras, Madras,
India, in 1987 and the M.E. degree in electrical
engineering from the Indian Institute of Science,
Bangalore, India, in August 1991. He has been
working toward the Ph.D. degree in electrical engineering at the National University of Singapore,
Singapore.
From August 1991 to November 1993, he was
working in industry in research and development.
He was involved in the design and development of
a variety of high-frequency high-density switch-mode power supplies and
uninterruptible power supply systems. His research interests are converter
topologies, modeling, simulation, and control, especially as applied to power
electronics. He is currently involved with an electric vehicle project at the
Singapore Polytechnic, Singapore.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998

Ramesh Oruganti (S83M85) received the

B.Tech. and M.Tech. degrees from the Indian
Institute of Technology, Madras, India, and the
Ph.D. degree from Virginia Polytechnic Institute
and State University, Blacksburg, in 1987.
He worked for two years at the Corporate R&D
Division of the General Electric Company on
advanced power converter systems. Since 1989,
he has been a Senior Lecturer in the Electrical
Engineering Department, National University
of Singapore. His research interests in power
electronics include soft-switched converters, active power factor improvement,
and converter modeling and control. He is currently the Director of the Center
for Power Electronics in the Faculty of Engineering, National University of
Singapore.
Dr. Oruganti is a Member of the honor societies of Phi Kappa Phi and
Eta Kappa Nu.