International Journal of Advanced Engineering Research and Technology (IJAERT) 270

Volume 2 Issue 7, October 2014, ISSN No.: 2348 8190

POWER OPTIMIZED 4-BIT BCD ADDER USING GDI TECHNIQUE

Thamaraimanalan.T, Santhiya.R, Kiruthiga.S
Assistant Professor, Electronics and Communication Engineering, Anna University Chennai, Coimbatore
Electronics and Communication Engineering, Anna University Chennai, Coimbatore

ABSTRACT
The Power and area are major factors in low power vlsi
design. To design a power optimized 4-bit BCD adder
the full adder is designed using GDI technique. The GDI
technique consumes low power because of it reduced
number of transistors compare to other design technique.
The simulation is done by using TANNER (EDA) tool
with 130nm technique and the result is compared with
other BCD adder circuits. The average power consumed
by the BCD adder is 1.384 w and the frequency is 200
MHZ with 1v supply voltage. The average power and
delay product are also considered while designing the
circuit.

using RCA topology, from that the carry output of one

full adder block is fed as the carry input for the next full
adder. To detect a carry in a logic circuit, two AND
gates and one OR gate have been used. Now, the full
adder design is the basic building block for designing the
proposed 4-bit BCD adder. The proper selection of the
full adder cell is important consideration for designing
BCD adder. The design criteria of a full adder are
actually multi-fold. The existing design used more
number of transistors. So the delay and power
consumption are relatively high.
Full adder equation:
Sum= A XOR B XOR C

KEYWORDS: Binary coded decimal (BCD), Electronic

Carry = A and B or B and C or C and A

Design Automation (EDA), Gate Diffusion Input(GDI).

I.

INTRODUCTION

The computer system uses binary data to process the

operation that is given to the system. The main factor
behind the binary data is the speed and its simplicity
compare to that of other number systems. But for
financial and commercial applications the decimal
number system is needed. In this case the binary data is
converted into decimal data and then it is again
converted into binary data.So significant amount of
delay is caused during the conversion. To reduce the
delay caused by the conversion the binary coded decimal
adder is used. The main building block of BCD adder is
full adder. It is used to produce binary addition result. If
the obtained result is below 9 then no need of correction
required. If the obtained result excess of 9 then the
decimal number 6 is added with the result for correction.
The full adder is basically a ripple carry adder. The
output of one full adder circuit is applied into input of
other full adder circuit. The speed of that adder is low
and then it consumes more amount of power. So in this
paper the full adder is designed using GDI technique. It
consumes low power compare to that of other full adder
circuits.

II.

Figure.1 circuit diagram of full adder using mux and xor

logic

A. EXISTING BCD ADDER DESIGN

In the conventional 4 bit BCD adder consist of two 4-bit

full adders. The full adder is designed with two XOR,
three AND, one OR gates. The designed full adder is
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Figure.2 BCD adder diagram

International Journal of Advanced Engineering Research and Technology (IJAERT) 271

Volume 2 Issue 7, October 2014, ISSN No.: 2348 8190

B. PROPOSED BCD ADDER DESIGN

In the proposed BCD adder a full adder is designed
using GDI technique. This technique allows to reduce
various parameters like power consumption, propagation
delay, and area of circuits. A basic GDI cell contains
four terminals namely G (common gate input of nMOS
and pMOS transistors), P (the outer diffusion node of
pMOS transistor), N (the outer diffusion node of nMOS
transistor), and D (common diffusion node of both
transistors).Basically the design looks like an inverter,
but the main differences are (i) GDI consist of three
inputs- G (gate input to NMOS/PMOS), P (input to
source of PMOS) and N (input to source of NMOS). (ii)
Bulks of both NMOS and PMOS are connected to N or
P (respectively), so it can be arbitrarily biased at contrast
with CMOS inverter. This design can implement a wide
variety of logic functions using only two transistors.
This method is suitable for design of fast, low-power
circuits, using a reduced number of transistors.

Figure.4 GDI based full adder

Figure.5 BCD adder using GDI technique

III.

Figure.3 Basic GDI circuit

POWER AND DELAY

CALCULATION

The power dissipation can be categorized mainly into

three parts, Switching Power dissipation, Short-Circuit
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International Journal of Advanced Engineering Research and Technology (IJAERT) 272

Volume 2 Issue 7, October 2014, ISSN No.: 2348 8190

Power dissipation, and Static Power dissipation. So the

total power can be expressed as,
P tot= p switch + p short + p leakage
While considering the power dissipated by a MOS
device, until recent years, the Static Leakage Power
component has been assumed to be negligible. But, in
the cases where we have to consider the sub-micron
technologies, or, deep-sub-micron technologies, this
assumption proving to be no longer true. Now, in
standby mode, the power dissipation that occurs in a
CMOS circuit is mainly due to the sub-threshold leakage
current. The sub- threshold current of a MOSFET can be
modeled as,
Isub=A

.( + )

(1- ).

Vg-gate voltage
Vs-source voltage
A-Area
k- proportionality constant
The propagation Delay through a transistor is generally
denoted as,
Pdelay=Cl Vdd/k(Vdd-Vth)
- Attenuation factor,Vdd-supply voltage
Vth-thershold voltage
Cl-load capacitance
The reduction of the vth can be useful to improve the
overall performance at low supply voltages. But, as we
reduce the vth of the transistor, leakage current starts
playing a dominant role. Thus, maintaining the
performance of the circuit as well as reducing the
Leakage Power dissipation becomes a key challenge for
designing any low-voltage, low power digital circuit.
Table 1.comparision of power, delay and number of
transistors of full adder design
s.no

Technique

power

Technology

XOR and
AND gates

9.38uw

45nm

No .of
transist
ors (for
1-bit
full
adder)
24

GDI

6.07uw

130nm

10

IV.

CONCLUSION

Power is the important factor in modern electronic

world. The power and area are directly proportional to
each other. If the area of the circuit is large the power
consumption is also large. So the full adder used in BCD
adder is designed with GDI technique and the full adder
used RIPPLE CARRY adder because of its small circuit
area and delay. The simulation result is done using
TANNER EDA with 130 nm technology.

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