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ECE380 Digital Logic

Flip-Flops, Registers and


Counters:
Flip-Flops

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-1

Flip-flops
• The gated latch circuits presented are level
sensitive and can change states more than
once during the ‘active’ period of the clock
signal
• Circuits (storage elements) that can change
their state no more than once during a clock
period are also useful
• Two types of circuits with such behavior
– Master-slave flip-flip
– Edge-triggered flip-flop

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-2

1
Master-slave D flip-flop
• Consists of 2 gated D latches
– The first, master, changes its state while clock=1
– The second, slave, changes its state while
clock=0

Master Slave
Q Qs
m
D D Q D Q Q

Clk Q Clk Q Q
Clock

38 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-3

Master-slave D flip-flop
• When clock=1, the master tracks the values of the D
input signal and the slave does not change
– Thus Qm follows any changes in D and Qs remains constant
• When the clock signal changes to 0, the master
stage stops following the changes in the D input
signal
• At the same time, the slave stage responds to the
value of Qm and changes states accordingly
• Since Qm does not change when clock=0, the slave
stage undergoes at most one change of state during
a clock cycle
• From an output point of view, the circuit changes Qs
(its output) at the negative edge of the clock signal

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-4

2
Master-slave D flip-flop

Clock

Qm

Q = Qs

D Q

clock Q

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-5

Edge-triggered flip-flop
• A circuit, similar in functionality to the master-slave
D flip-flop, can be constructed with 6 NAND gates
1 P3

P1
2
5 Q
D Q
Clock
P2 clock Q
6 Q
3
Positive-edge-triggered
D type flip-flop

D 4 P4 24 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-6

3
Edge-triggered flip-flop
• The previous circuit responds on the positive
edge of the clock signal
• A negative-edge triggered D flip-flop can be
constructed by replacing the NAND with NOR
gates

D Q D Q

clock Q clock Q
Positive-edge-triggered Negative-edge-triggered
D type flip-flop D type flip-flop

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-7

Comparing D storage elements

D
D Q Qa

clock
clk Q
clock

D Q Qb D

Qa
Q
Q
b
D Q Qc
Q
c
Q

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-8

4
Clear and preset inputs
• It may be desirable to specifically set (Q=1)
or clear (Q=0) a flip-flop
• Practical flip-flops often have preset and
clear inputs
– Generally, these inputs are asynchronous (they
do not depend on the clock signal)
Preset’
D Q As long as Preset’=0, Q=1

clock Q As long as Clear’=0, Q=0


Clear’

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-9

T flip-flop
• Another flip-flop type, the T flip-flop, can be
derived from the basic D flip-flop presented
• Feedback connections make the input signal D equal
to the value of Q or Q’ under control of a signal
labeled T

D Q Q
T
Q Q

Clock

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-10

5
T flip-flop
• The name T derives from the behavior of the
circuit, which ‘toggles’ its state when T=1
– This feature makes the T flip-flop a useful element
when constructing counter circuits

T Q(t+1) Clock
0 Q(t) T
1 Q’(t) Q

T Q

clock Q
Positive edge triggered
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-11

JK flip-flop
• The JK flip-flop can also be derived from
the basic D flip-flop such that
D=JQ’+K’Q
• The JK flip-flop combines aspects of the SR
and the T flip-flop
– It behaves as the SR flip-flop (where J=S and
K=R) for all values except J=K=1
– For J=K=1, it toggles like the T flip-flop

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-12

6
JK flip-flop

J
D Q Q
K Q Q

Clock

J K Q(t+1)
0 0 Q(t)
J Q
0 1 0 clock
1 0 1 K Q
1 1 Q’(t) Positive edge triggered
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-13

JK flip-flop timing diagram


Complete the following timing diagram
1
Clk
0
1
K
0
1
J
0
1
Q
0
1
Q
0
Time
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-14

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