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1
Counter state diagram
reset
A/Z1Z0=00
U=1 U=1
U=0 U=0
D/Z1Z0=11 B/Z1Z0=01
U=0 U=0
U=1 U=1
C/Z1Z0=10
2
State-assigned state table
• Choosing a state assignment of A=00, B=01, C=10
and D=11 makes sense here because the outputs
Z1Z0 become the outputs from the flip-flops directly
Next state
Present
Output
state U=0 U=1
Z1Z0
y2 y1
Y2Y1 Y2Y1
A 00 11 01 00
B 01 00 10 01
C 10 01 11 10
D 11 10 00 11
3
State table and next-state maps
y2y1
u 00 01 11 10
Next state 0 1 0 0 1
Present
Output
state U=0 U=1 1 1 0 0 1
Z1Z0
y2 y1
Y2Y1 Y2Y1 Y1=y1’
A 00 11 01 00
y2y1
B 01 00 10 01 u 00 01 11 10
C 10 01 11 10 0 1 0 1 0
D 11 10 00 11 1 0 1 0 1
Z0
Z1
U
clock
reset
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 28-8
4
Design using other flip-flop types
• For the T- or JK-type flip-flops, we must
derive the desired inputs to the flip-flops
• Begin by constructing a transition table for
the flip-flop type you wish to use
– This table simply lists required inputs for a given
change of state
• The transition table is used with the state-
assigned state table to construct an
excitation table
– The excitation table lists the required flip-flop
inputs that must be ‘excited’ to cause a transition
to the next state
Transition tables
J K Q Q+ Q Q+ J K T Q Q+ Q Q+ T
0 0 0 0 0 0 0 D 0 0 0 0 0 0
0 0 1 1 0 1 1 D 0 1 1 0 1 1
0 1 0 0 1 0 D 1 1 0 1 1 0 1
0 1 1 0 1 1 D 0 1 1 0 1 1 0
1 0 0 1
JK transition T transition
1 0 1 1 table table
1 1 0 1
1 1 1 0 The transition table lists required flip-flop
inputs to affect a specific change
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 28-10
5
T-type flip-flop implementation
Use entries from the transition table
to derive the flip-flop inputs based on
the state-assigned state table.
Q Q+ T
excitation table
0 0 0
0 1 1 Flip-flop inputs
Present
Output
1 0 1 state U=0 U=1
Z1Z0
1 1 0 y2 y1
Y2Y1 T2 T1 Y2Y1 T2 T1
00 11 11 01 01 00
01 00 01 10 11 01
10 01 11 11 01 10
11 10 01 00 11 11
6
Circuit diagram (T flip-flop)
Vcc
Vcc Z0
U Z1
clock
reset
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 28-13
Next state
Q Q+ J K
Present
state
Output 0 0 0 D
U=0 U=1 Z1Z0
y2 y1 0 1 1 D
Y2Y1 Y2Y1
00 11 01 00 1 0 D 1
01 00 10 01 1 1 D 0
10 01 11 10
JK transition
11 10 00 11 table
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 28-14
7
JK-type flip-flop implementation
Q Q+ J K Flip-flop inputs
Present
0 0 0 D state
Output
U=0 U=1 Z1Z0
0 1 1 D y2 y1
Y2Y1 J2K2 J1K1 Y2Y1 J2K2 J1K1
1 0 D 1 00 11 1D 1D 01 0D 1D 00
1 1 D 0 01 00 0D D1 10 1D D1 01
10 01 D1 1D 11 D0 1D 10
JK transition
table 11 10 D0 D1 00 D1 D1 11
8
Excitation table and K-maps
Flip-flop inputs
Present
Output
state U=0 U=1 Z1Z0
y2 y1
Y2Y1 J2K2 J1K1 Y2Y1 J2K2 J1K1
00 11 1D 1D 01 0D 1D 00
01 00 0D D1 10 1D D1 01
10 01 D1 1D 11 D0 1D 10
11 10 D0 D1 00 D1 D1 11
y2y1 y2y1
u 00 01 11 10 u 00 01 11 10
0 1 0 D D 0 D D 0 1
1 0 1 D D 1 D D 1 0
J2 =(y1⊕u)’ K2=(y1⊕u)’
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 28-17
Vcc Z0
U Z1
clock
reset
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 28-18