ECE380 Digital Logic

Synchronous Sequential Circuits:

State Assignment Problem,
Mealy State Machines

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-1

State assignment problem

• For the sequential circuit examples shown thus far,
we have considered only a simple, straightforward
state assignment
• Could another, different state assignment lead to a
simpler solution?
reset
w=1 Present Next state
Output
w=0 A/z=0 B/z=0 state w=0 w=1
z
y2 y1 Y2Y1 Y2Y1
w=0
w=0 w=1 A 00 00 01 0

C/z=1 B 01 00 10 0
C 10 00 10 1
11 dd dd d
w=1
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-2

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Alternate state assignment
• If we change the state assignment for the
previous problem such that A=00, B=01,
C=11 and 10 is the unused state, the state
assigned state table becomes the following

Present Next state Output Present Next state

Output
state w=0 w=1 z state w=0 w=1
z
A A B 0 y2 y1 Y2Y1 Y2Y1
B A C 0 A 00 00 01 0
C A C 1 B 01 00 11 0
C 11 00 11 1
10 dd dd d

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-3

Simplified circuit implementation

Y2 y
D Q 2
z
Y1=D1=w
Y2=D2=wy1 Q
z=y2

Y1 y
1
w D Q

Clock Q

Resetn

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-4

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State assignment problem
• In general, circuits are much larger than the
example given, and different state
assignments can have a significant impact on
the cost of the final implementation
• It is often impossible (impractical) to find the
best assignment for a large circuit because
the number of available states is large
• CAD tools usually perform state assignment
using heuristic techniques

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-5

State assignment guidelines

• Does not guarantee a minimum solution
• Assignments for states are adjacent if they
differ in only one state variable

1. States that have the same next state for a given

input should be given adjacent assignments
2. States that are the next state of the same state
should be given adjacent assignments
3. States that have the same output for a given
input should be given adjacent assignments
(groups ‘1’s on the output K-map)

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-6

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State assignment guidelines
1. States that have the
A W=1
same next state for a
given input should be C
given adjacent
assignments
B W=1

2. States that are the W=1 C

next state of the same
state should be given A
adjacent assignments
W=0 B

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-7

State assignment guidelines

• Keep the following in mind:
1. Assign the starting state to the ‘0’ cell on the
map (i.e. the starting state has all flip-flop
outputs=0)
2. Satisfy guideline 1 and multiple occurrences of
guideline 2 first
3. If the guidelines require that 3 or 4 states be
adjacent, place these states within a group of 4
adjacent squares on the map
4. Guideline 3 is less important than 1 or 2 unless
the circuit is to have multiple outputs

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-8

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Example Moore state diagram
reset

W=0 A/0
W=1

W=1
D/1 B/0 W=1
W=0
W=1
W=0
W=0
C/0
Detects 101 sequence
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-9

Example state assignment

• Two state variables y1y0
• According to guidelines
• A=00 reset
1. {A,D}, {B,D}, {A,C}
2. {A,D}, {B,C} W=0 A/0
3. {A,B,C} W=1

y0 W=1
D/1 B/0 W=1
y1 0 1
W=0
0 A=00 W=1
A C
B=11 W=0 W=0
1 D B C=01 C/0
D=10

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-10

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One hot encoding
• One possibility for state assignment is to use as
many state variables as there are states in a
sequential circuit
• For each state, all but one of the state variables are
0
• The variable whose value is 1 is deemed to be hot
– One-hot encoding method
• Increases the number of flip-flops needed for
implementation, but tends to lead to simpler output
expressions
– Simpler output expressions may lead to a faster circuit since
there may be less propagation delay from the flip-flop
outputs to the final outputs of the sequential circuit

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-11

Mealy state model

• Mealy model: circuit outputs depend on the
present state of the circuit and the primary
inputs, giving additional flexibility in
designing sequential circuits
• Greater flexibility often leads to simpler
circuits

w Combinational Combinational
Flip-flops
circuit circuit
Q f
clock
Mealy state machine
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-12

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Mealy state diagram
• For the Mealy model, outputs are no longer
associated with a particular state
– Outputs are associated with transitions between
states
• Typical Mealy model state diagram
– Detects w=11 sequence

reset
w=1/z=0

w=0/z=0 A B w=1/z=1

w=0/z=0

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-13

Mealy model state table

• The state table for a Mealy model FSM differs
from the Moore model FSM only in how the
outputs are viewed
reset
1/0

w/z 0/0 A B 1/1

0/0

Present Next state Output z

state w = 0 w = 1 w=0 w=1
A A B 0 0
B A B 0 1
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-14

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State-assigned state table

Present Next state Output

state w = 0 w = 1 w=0 w=1
y Y Y z z
A 0 0 1 0 0
B 1 0 1 0 1

w D Q
y
Clock Q

Resetn

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-15

Design example
• Construct a Mealy state diagram for a
sequence detector that detects the input
sequence w=101

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 29-16