Single-ended vs.

Differential SC Circuits
Single Ended

Differential

Number of Caps

1 (Cs)

2 (Cd)

Max Signal

1Vpp

2Vpp

Max Power

V2/2

2V2

Thermal Noise

kT/Cs

2kT/Cd

V2Cs/(2kT)

V2Cd/(kT)

SNR

Conclusion: For the same SNR, Cd = Cs/2, so

total capacitance is same, and no extra layout
area required for the capacitors

Charge Injection Cancellation

(Johns & Martin Switched Capacitor Circuit p.45)

Charge Injection Cancellation cont.

The switching sequence: Q3(2a) off Q2(2) off Q4(1a) on Q1(1) on
Clock Phase/Sequence
2 = 1, 2a = 1
1 = 0, 1a = 0
2a 0
2 0
1a 1
1 1

Switch state
Q2 and Q3 on
Q1 and Q4 off
Q3 off
Q2 off
Q4 on
Q1 on

1a 0

Q4 off

Charge Transfer
C2, C3 discharged
Q3 deposits q/2 in C2||C3
No injection since top plate of C2 is open
Q4 acquires q from CA
C2 charges to Vi; C3 charges to Vo
CA charges to C2Vi(n) + C3Vo(n) + q/2
Q4 deposits q/2 into CA

Net charge injection in CA: -q + q/2 +q/2 = 0

q cancel when 1 1

Integrator Using a Two-stage

(Buffered) OPAMP
AV

AO

s / p 1

Let Initial Values: VC1 = V1, VC2 = 0

I (V1 VO )

sC1C2
sC2 (V VO )
C1 C2

1
VO AV V V1
s / ( AO p ) 1/ AO

Pole at: ( 1/ AO ) AO p u
Settling level: VO ( s) s 0

C
1
1
1/ AO
C2

C2
C1 C2

Time Constant of OTA-SC Integrator

Open-loop Gain

gmV sCLVO sCSVO 0

g mV
VO
s(CL CS )

V1 VO

g mV
V1
s(CL CS )

At pole SP, V1 V , so:

sP

gm
C2 g m

CL CS CL (C1 C2 ) C1C2

Transient term:

esPt et /

1
sp

Unity-gain conventional integrator, assuming all Cs equal:

3C
gm

CS

C1C2
C1 C2

C2
C1 C2

First-Order Gm-C Filter

KCL at output:

(Vin Vout )sCX VinGM 1 Vout GM 2 Vout sCA

H ( s)

Vout
sC X GM 1

Vin s(C X C A ) GM 2

lim H ( s)

The specified transfer function is:

Equating the coefficients gives:

H ( s)

CX

k1s k0
s 0

k1
CA
1 k1

GM 1
GM 2

CX
(C X C A )

lim H ( s) k1 k1 1
s

0 k1 1 for positive CA and CX

k0
CA
1 k1

0
1 k1

CA
CA and CX can be chosen arbitrarily

k1 high frequency gain

Gm-C Biquads with Transmission Zeroes 0 or

2CA
Gm1

2CB

2CA

Iin
Vin

Gm3

Gm2
2CB

2CX

Gm4

Gm5
2CX

Iin

Vout

C X GM 5
GM 2GM 4
s2
s

C CB C X CB C A (C X CB )
V (s)
H ( s ) out
X
Vin ( s )
GM 3
GM 1GM 2
s2 s

C X CB C A (C X CB )

To calculate the input impedance, find Iin sCX (Vin Vout ) sCX Vin [1 H (s)]

I in
s 2CB s(GM 3 GM 5 ) GM 2 (GM 1 GM 4 ) / C A
Yin
sC X
Vin
s 2 (C X CB ) sGM 3 GM 1GM 2 / C A
For s ,

At DC,

Yin s

C X CB
C X CB

Vout Vin

GM 4
GM 1

Yin sC X

GM 1 GM 4
GM 1

Yin 0 for GM 1 GM 4

Dynamic Scaling GM-C Circuits

1. Let a cascade of N biquads realize H(s) = H1(s) H2(s) HN(s). Before starting the circuit
design, scle H1(s) so that k1|H1|(max) gives the largest allowable Vout1. Divide H2(s) by k1,
and repeat scaling for H2/k1. Continue until all N Hi(s) are scaled
2. Realize all stages, scale the intermediate voltage VCA across CA in the first biquad by an
appropriate k1A. Multiply incoming GMs (GM1 & GM2) by k1A, and divide outgoing GMs
(GM4) by k1A. Then, the output current will be unchanged. Continue for all N biquads

V2

Gm1

V1

Gm2

Gm3

VM

Gm4

Vout1

Note: This scaling procedure avoids the complications caused by CX in the scaling of VCB in
biquads where H is not zero at infinite frequencies. This does not take care of loading by CX!

Fixed-Bias Triode Transconductor

VDD
I1

I1
Rout

Q5
vi +

Feedback loop to hold V

constant, Rout low, I1 in
Q1/2. Hence, VGS constant,
iq proportional to vi+ - vi-,

Q1

Q2

Q6
vi -

1
W
GM nCox (vgs 9 VT )
rdsq
L 9

VC
I1-io1

I1+io1
Q9

Q7

Q3
I2

Q4

Q8
I2

vi vi
where iq
rdsq

Vgs9 is controlled by VC